pci root complex: support for tile architecture
This change enables PCI root complex support for TILEPro. Unlike TILE-Gx, TILEPro has no support for memory-mapped I/O, so the PCI support consists of hypervisor upcalls for PIO, DMA, etc. However, the performance is fine for the devices we have tested with so far (1Gb Ethernet, SATA, etc.). The <asm/io.h> header was tweaked to be a little bit more aggressive about disabling attempts to map/unmap IO port space. The hacky <asm/pci-bridge.h> header was rolled into the <asm/pci.h> header and the result was simplified. Both of the latter two headers were preliminary versions not meant for release before now - oh well. There is one quirk for our TILEmpower platform, which accidentally negotiates up to 5GT and needs to be kicked down to 2.5GT. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
This commit is contained in:
Chris Metcalf
@@ -15,7 +15,29 @@
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#ifndef _ASM_TILE_PCI_H
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#define _ASM_TILE_PCI_H
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#include <asm/pci-bridge.h>
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#include <linux/pci.h>
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/*
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* Structure of a PCI controller (host bridge)
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*/
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struct pci_controller {
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int index; /* PCI domain number */
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struct pci_bus *root_bus;
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int first_busno;
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int last_busno;
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int hv_cfg_fd[2]; /* config{0,1} fds for this PCIe controller */
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int hv_mem_fd; /* fd to Hypervisor for MMIO operations */
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struct pci_ops *ops;
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int irq_base; /* Base IRQ from the Hypervisor */
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int plx_gen1; /* flag for PLX Gen 1 configuration */
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/* Address ranges that are routed to this controller/bridge. */
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struct resource mem_resources[3];
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};
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/*
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* The hypervisor maps the entirety of CPA-space as bus addresses, so
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@@ -24,57 +46,13 @@
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*/
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#define PCI_DMA_BUS_IS_PHYS 1
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struct pci_controller *pci_bus_to_hose(int bus);
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unsigned char __init common_swizzle(struct pci_dev *dev, unsigned char *pinp);
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int __init tile_pci_init(void);
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void pci_iounmap(struct pci_dev *dev, void __iomem *addr);
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void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max);
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static inline void pci_iounmap(struct pci_dev *dev, void __iomem *addr) {}
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void __devinit pcibios_fixup_bus(struct pci_bus *bus);
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int __devinit _tile_cfg_read(struct pci_controller *hose,
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int bus,
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int slot,
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int function,
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int offset,
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int size,
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u32 *val);
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int __devinit _tile_cfg_write(struct pci_controller *hose,
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int bus,
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int slot,
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int function,
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int offset,
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int size,
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u32 val);
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/*
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* These are used to to config reads and writes in the early stages of
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* setup before the driver infrastructure has been set up enough to be
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* able to do config reads and writes.
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*/
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#define early_cfg_read(where, size, value) \
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_tile_cfg_read(controller, \
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current_bus, \
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pci_slot, \
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pci_fn, \
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where, \
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size, \
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value)
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#define early_cfg_write(where, size, value) \
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_tile_cfg_write(controller, \
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current_bus, \
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pci_slot, \
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pci_fn, \
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where, \
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size, \
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value)
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#define PCICFG_BYTE 1
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#define PCICFG_WORD 2
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#define PCICFG_DWORD 4
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#define TILE_NUM_PCIE 2
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#define pci_domain_nr(bus) (((struct pci_controller *)(bus)->sysdata)->index)
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@@ -88,33 +66,33 @@ static inline int pci_proc_domain(struct pci_bus *bus)
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}
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/*
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* I/O space is currently not supported.
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* pcibios_assign_all_busses() tells whether or not the bus numbers
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* should be reassigned, in case the BIOS didn't do it correctly, or
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* in case we don't have a BIOS and we want to let Linux do it.
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*/
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static inline int pcibios_assign_all_busses(void)
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{
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return 1;
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}
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#define TILE_PCIE_LOWER_IO 0x0
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#define TILE_PCIE_UPPER_IO 0x10000
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#define TILE_PCIE_PCIE_IO_SIZE 0x0000FFFF
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#define _PAGE_NO_CACHE 0
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#define _PAGE_GUARDED 0
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#define pcibios_assign_all_busses() pci_assign_all_buses
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extern int pci_assign_all_buses;
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/*
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* No special bus mastering setup handling.
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*/
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static inline void pcibios_set_master(struct pci_dev *dev)
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{
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/* No special bus mastering setup handling */
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}
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#define PCIBIOS_MIN_MEM 0
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#define PCIBIOS_MIN_IO TILE_PCIE_LOWER_IO
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#define PCIBIOS_MIN_IO 0
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/*
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* This flag tells if the platform is TILEmpower that needs
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* special configuration for the PLX switch chip.
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*/
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extern int blade_pci;
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extern int tile_plx_gen1;
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/* Use any cpu for PCI. */
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#define cpumask_of_pcibus(bus) cpu_online_mask
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/* implement the pci_ DMA API in terms of the generic device dma_ one */
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#include <asm-generic/pci-dma-compat.h>
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@@ -122,7 +100,4 @@ extern int blade_pci;
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/* generic pci stuff */
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#include <asm-generic/pci.h>
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/* Use any cpu for PCI. */
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#define cpumask_of_pcibus(bus) cpu_online_mask
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#endif /* _ASM_TILE_PCI_H */
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