iwlcore: support ICT interrupt

Add ICT interrupt handler support, ICT should improve CPU utilization
 since it does not require target read which is very expensive. This
 interrupt handler only added to 5000 cards and newer. Device will write
 interrupts to ICT shared table to inform driver about its interrupts.

These patches will not touch 3945 and 4965 interrupt handlers and tasklet.

Signed-off-by: Mohamed Abbas <mohamed.abbas@intel.com>
Signed-off-by: Reinette Chatre <reinette.chatre@intel.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
这个提交包含在:
Mohamed Abbas
2009-05-22 11:01:50 -07:00
提交者 John W. Linville
父节点 a2b0f02e47
当前提交 ef850d7cb3
修改 9 个文件,包含 483 行新增12 行删除

查看文件

@@ -97,6 +97,7 @@
#define CSR_UCODE_DRV_GP1_CLR (CSR_BASE+0x05c)
#define CSR_UCODE_DRV_GP2 (CSR_BASE+0x060)
#define CSR_LED_REG (CSR_BASE+0x094)
#define CSR_DRAM_INT_TBL_REG (CSR_BASE+0x0A0)
#define CSR_GIO_CHICKEN_BITS (CSR_BASE+0x100)
/* Analog phase-lock-loop configuration */
@@ -256,6 +257,11 @@
/* HPET MEM debug */
#define CSR_DBG_HPET_MEM_REG_VAL (0xFFFF0000)
/* DRAM INT TABLE */
#define CSR_DRAM_INT_TBL_ENABLE (1 << 31)
#define CSR_DRAM_INIT_TBL_WRAP_CHECK (1 << 27)
/*=== HBUS (Host-side Bus) ===*/
#define HBUS_BASE (0x400)
/*