Merge branch 'acpi-pm'
* acpi-pm: ACPI / bus: Move duplicate code to a separate new function mfd: Add support for Intel Sunrisepoint LPSS devices dmaengine: add a driver for Intel integrated DMA 64-bit mfd: make mfd_remove_devices() iterate in reverse order driver core: implement device_for_each_child_reverse() klist: implement klist_prev() Driver core: wakeup the parent device before trying probe ACPI / PM: Attach ACPI power domain only once PM / QoS: Make it possible to expose device latency tolerance to userspace ACPI / PM: Update the copyright notice and description of power.c
Este commit está contenido en:
Rafael J. Wysocki
@@ -85,6 +85,14 @@ config INTEL_IOP_ADMA
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help
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Enable support for the Intel(R) IOP Series RAID engines.
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config IDMA64
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tristate "Intel integrated DMA 64-bit support"
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select DMA_ENGINE
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select DMA_VIRTUAL_CHANNELS
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help
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Enable DMA support for Intel Low Power Subsystem such as found on
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Intel Skylake PCH.
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source "drivers/dma/dw/Kconfig"
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config AT_HDMAC
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@@ -14,6 +14,7 @@ obj-$(CONFIG_HSU_DMA) += hsu/
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obj-$(CONFIG_MPC512X_DMA) += mpc512x_dma.o
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obj-$(CONFIG_PPC_BESTCOMM) += bestcomm/
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obj-$(CONFIG_MV_XOR) += mv_xor.o
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obj-$(CONFIG_IDMA64) += idma64.o
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obj-$(CONFIG_DW_DMAC_CORE) += dw/
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obj-$(CONFIG_AT_HDMAC) += at_hdmac.o
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obj-$(CONFIG_AT_XDMAC) += at_xdmac.o
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710
drivers/dma/idma64.c
Archivo normal
710
drivers/dma/idma64.c
Archivo normal
@@ -0,0 +1,710 @@
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/*
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* Core driver for the Intel integrated DMA 64-bit
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*
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* Copyright (C) 2015 Intel Corporation
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* Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/bitops.h>
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#include <linux/delay.h>
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#include <linux/dmaengine.h>
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#include <linux/dma-mapping.h>
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#include <linux/dmapool.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include "idma64.h"
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/* Platform driver name */
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#define DRV_NAME "idma64"
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/* For now we support only two channels */
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#define IDMA64_NR_CHAN 2
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/* ---------------------------------------------------------------------- */
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static struct device *chan2dev(struct dma_chan *chan)
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{
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return &chan->dev->device;
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}
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/* ---------------------------------------------------------------------- */
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static void idma64_off(struct idma64 *idma64)
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{
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unsigned short count = 100;
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dma_writel(idma64, CFG, 0);
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channel_clear_bit(idma64, MASK(XFER), idma64->all_chan_mask);
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channel_clear_bit(idma64, MASK(BLOCK), idma64->all_chan_mask);
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channel_clear_bit(idma64, MASK(SRC_TRAN), idma64->all_chan_mask);
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channel_clear_bit(idma64, MASK(DST_TRAN), idma64->all_chan_mask);
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channel_clear_bit(idma64, MASK(ERROR), idma64->all_chan_mask);
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do {
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cpu_relax();
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} while (dma_readl(idma64, CFG) & IDMA64_CFG_DMA_EN && --count);
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}
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static void idma64_on(struct idma64 *idma64)
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{
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dma_writel(idma64, CFG, IDMA64_CFG_DMA_EN);
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}
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/* ---------------------------------------------------------------------- */
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static void idma64_chan_init(struct idma64 *idma64, struct idma64_chan *idma64c)
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{
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u32 cfghi = IDMA64C_CFGH_SRC_PER(1) | IDMA64C_CFGH_DST_PER(0);
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u32 cfglo = 0;
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/* Enforce FIFO drain when channel is suspended */
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cfglo |= IDMA64C_CFGL_CH_DRAIN;
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/* Set default burst alignment */
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cfglo |= IDMA64C_CFGL_DST_BURST_ALIGN | IDMA64C_CFGL_SRC_BURST_ALIGN;
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channel_writel(idma64c, CFG_LO, cfglo);
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channel_writel(idma64c, CFG_HI, cfghi);
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/* Enable interrupts */
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channel_set_bit(idma64, MASK(XFER), idma64c->mask);
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channel_set_bit(idma64, MASK(ERROR), idma64c->mask);
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/*
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* Enforce the controller to be turned on.
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*
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* The iDMA is turned off in ->probe() and looses context during system
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* suspend / resume cycle. That's why we have to enable it each time we
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* use it.
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*/
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idma64_on(idma64);
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}
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static void idma64_chan_stop(struct idma64 *idma64, struct idma64_chan *idma64c)
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{
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channel_clear_bit(idma64, CH_EN, idma64c->mask);
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}
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static void idma64_chan_start(struct idma64 *idma64, struct idma64_chan *idma64c)
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{
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struct idma64_desc *desc = idma64c->desc;
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struct idma64_hw_desc *hw = &desc->hw[0];
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channel_writeq(idma64c, SAR, 0);
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channel_writeq(idma64c, DAR, 0);
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channel_writel(idma64c, CTL_HI, IDMA64C_CTLH_BLOCK_TS(~0UL));
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channel_writel(idma64c, CTL_LO, IDMA64C_CTLL_LLP_S_EN | IDMA64C_CTLL_LLP_D_EN);
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channel_writeq(idma64c, LLP, hw->llp);
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channel_set_bit(idma64, CH_EN, idma64c->mask);
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}
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static void idma64_stop_transfer(struct idma64_chan *idma64c)
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{
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struct idma64 *idma64 = to_idma64(idma64c->vchan.chan.device);
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idma64_chan_stop(idma64, idma64c);
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}
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static void idma64_start_transfer(struct idma64_chan *idma64c)
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{
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struct idma64 *idma64 = to_idma64(idma64c->vchan.chan.device);
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struct virt_dma_desc *vdesc;
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/* Get the next descriptor */
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vdesc = vchan_next_desc(&idma64c->vchan);
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if (!vdesc) {
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idma64c->desc = NULL;
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return;
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}
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list_del(&vdesc->node);
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idma64c->desc = to_idma64_desc(vdesc);
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/* Configure the channel */
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idma64_chan_init(idma64, idma64c);
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/* Start the channel with a new descriptor */
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idma64_chan_start(idma64, idma64c);
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}
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/* ---------------------------------------------------------------------- */
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static void idma64_chan_irq(struct idma64 *idma64, unsigned short c,
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u32 status_err, u32 status_xfer)
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{
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struct idma64_chan *idma64c = &idma64->chan[c];
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struct idma64_desc *desc;
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unsigned long flags;
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spin_lock_irqsave(&idma64c->vchan.lock, flags);
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desc = idma64c->desc;
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if (desc) {
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if (status_err & (1 << c)) {
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dma_writel(idma64, CLEAR(ERROR), idma64c->mask);
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desc->status = DMA_ERROR;
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} else if (status_xfer & (1 << c)) {
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dma_writel(idma64, CLEAR(XFER), idma64c->mask);
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desc->status = DMA_COMPLETE;
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vchan_cookie_complete(&desc->vdesc);
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idma64_start_transfer(idma64c);
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}
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/* idma64_start_transfer() updates idma64c->desc */
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if (idma64c->desc == NULL || desc->status == DMA_ERROR)
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idma64_stop_transfer(idma64c);
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}
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spin_unlock_irqrestore(&idma64c->vchan.lock, flags);
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}
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static irqreturn_t idma64_irq(int irq, void *dev)
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{
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struct idma64 *idma64 = dev;
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u32 status = dma_readl(idma64, STATUS_INT);
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u32 status_xfer;
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u32 status_err;
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unsigned short i;
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dev_vdbg(idma64->dma.dev, "%s: status=%#x\n", __func__, status);
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/* Check if we have any interrupt from the DMA controller */
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if (!status)
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return IRQ_NONE;
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/* Disable interrupts */
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channel_clear_bit(idma64, MASK(XFER), idma64->all_chan_mask);
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channel_clear_bit(idma64, MASK(ERROR), idma64->all_chan_mask);
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status_xfer = dma_readl(idma64, RAW(XFER));
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status_err = dma_readl(idma64, RAW(ERROR));
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for (i = 0; i < idma64->dma.chancnt; i++)
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idma64_chan_irq(idma64, i, status_err, status_xfer);
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/* Re-enable interrupts */
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channel_set_bit(idma64, MASK(XFER), idma64->all_chan_mask);
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channel_set_bit(idma64, MASK(ERROR), idma64->all_chan_mask);
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return IRQ_HANDLED;
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}
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/* ---------------------------------------------------------------------- */
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static struct idma64_desc *idma64_alloc_desc(unsigned int ndesc)
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{
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struct idma64_desc *desc;
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desc = kzalloc(sizeof(*desc), GFP_NOWAIT);
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if (!desc)
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return NULL;
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desc->hw = kcalloc(ndesc, sizeof(*desc->hw), GFP_NOWAIT);
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if (!desc->hw) {
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kfree(desc);
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return NULL;
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}
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return desc;
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}
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static void idma64_desc_free(struct idma64_chan *idma64c,
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struct idma64_desc *desc)
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{
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struct idma64_hw_desc *hw;
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if (desc->ndesc) {
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unsigned int i = desc->ndesc;
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do {
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hw = &desc->hw[--i];
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dma_pool_free(idma64c->pool, hw->lli, hw->llp);
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} while (i);
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}
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kfree(desc->hw);
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kfree(desc);
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}
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static void idma64_vdesc_free(struct virt_dma_desc *vdesc)
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{
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struct idma64_chan *idma64c = to_idma64_chan(vdesc->tx.chan);
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idma64_desc_free(idma64c, to_idma64_desc(vdesc));
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}
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static u64 idma64_hw_desc_fill(struct idma64_hw_desc *hw,
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struct dma_slave_config *config,
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enum dma_transfer_direction direction, u64 llp)
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{
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struct idma64_lli *lli = hw->lli;
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u64 sar, dar;
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u32 ctlhi = IDMA64C_CTLH_BLOCK_TS(hw->len);
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u32 ctllo = IDMA64C_CTLL_LLP_S_EN | IDMA64C_CTLL_LLP_D_EN;
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u32 src_width, dst_width;
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if (direction == DMA_MEM_TO_DEV) {
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sar = hw->phys;
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dar = config->dst_addr;
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ctllo |= IDMA64C_CTLL_DST_FIX | IDMA64C_CTLL_SRC_INC |
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IDMA64C_CTLL_FC_M2P;
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src_width = min_t(u32, 2, __fls(sar | hw->len));
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dst_width = __fls(config->dst_addr_width);
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} else { /* DMA_DEV_TO_MEM */
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sar = config->src_addr;
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dar = hw->phys;
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ctllo |= IDMA64C_CTLL_DST_INC | IDMA64C_CTLL_SRC_FIX |
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IDMA64C_CTLL_FC_P2M;
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src_width = __fls(config->src_addr_width);
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dst_width = min_t(u32, 2, __fls(dar | hw->len));
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}
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lli->sar = sar;
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lli->dar = dar;
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lli->ctlhi = ctlhi;
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lli->ctllo = ctllo |
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IDMA64C_CTLL_SRC_MSIZE(config->src_maxburst) |
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IDMA64C_CTLL_DST_MSIZE(config->dst_maxburst) |
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IDMA64C_CTLL_DST_WIDTH(dst_width) |
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IDMA64C_CTLL_SRC_WIDTH(src_width);
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lli->llp = llp;
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return hw->llp;
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}
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static void idma64_desc_fill(struct idma64_chan *idma64c,
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struct idma64_desc *desc)
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{
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struct dma_slave_config *config = &idma64c->config;
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struct idma64_hw_desc *hw = &desc->hw[desc->ndesc - 1];
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struct idma64_lli *lli = hw->lli;
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u64 llp = 0;
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unsigned int i = desc->ndesc;
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|
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/* Fill the hardware descriptors and link them to a list */
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do {
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hw = &desc->hw[--i];
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llp = idma64_hw_desc_fill(hw, config, desc->direction, llp);
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desc->length += hw->len;
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} while (i);
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|
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/* Trigger interrupt after last block */
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lli->ctllo |= IDMA64C_CTLL_INT_EN;
|
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}
|
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|
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static struct dma_async_tx_descriptor *idma64_prep_slave_sg(
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struct dma_chan *chan, struct scatterlist *sgl,
|
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unsigned int sg_len, enum dma_transfer_direction direction,
|
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unsigned long flags, void *context)
|
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{
|
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struct idma64_chan *idma64c = to_idma64_chan(chan);
|
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struct idma64_desc *desc;
|
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struct scatterlist *sg;
|
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unsigned int i;
|
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|
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desc = idma64_alloc_desc(sg_len);
|
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if (!desc)
|
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return NULL;
|
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|
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for_each_sg(sgl, sg, sg_len, i) {
|
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struct idma64_hw_desc *hw = &desc->hw[i];
|
||||
|
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/* Allocate DMA capable memory for hardware descriptor */
|
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hw->lli = dma_pool_alloc(idma64c->pool, GFP_NOWAIT, &hw->llp);
|
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if (!hw->lli) {
|
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desc->ndesc = i;
|
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idma64_desc_free(idma64c, desc);
|
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return NULL;
|
||||
}
|
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|
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hw->phys = sg_dma_address(sg);
|
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hw->len = sg_dma_len(sg);
|
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}
|
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|
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desc->ndesc = sg_len;
|
||||
desc->direction = direction;
|
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desc->status = DMA_IN_PROGRESS;
|
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|
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idma64_desc_fill(idma64c, desc);
|
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return vchan_tx_prep(&idma64c->vchan, &desc->vdesc, flags);
|
||||
}
|
||||
|
||||
static void idma64_issue_pending(struct dma_chan *chan)
|
||||
{
|
||||
struct idma64_chan *idma64c = to_idma64_chan(chan);
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&idma64c->vchan.lock, flags);
|
||||
if (vchan_issue_pending(&idma64c->vchan) && !idma64c->desc)
|
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idma64_start_transfer(idma64c);
|
||||
spin_unlock_irqrestore(&idma64c->vchan.lock, flags);
|
||||
}
|
||||
|
||||
static size_t idma64_active_desc_size(struct idma64_chan *idma64c)
|
||||
{
|
||||
struct idma64_desc *desc = idma64c->desc;
|
||||
struct idma64_hw_desc *hw;
|
||||
size_t bytes = desc->length;
|
||||
u64 llp;
|
||||
u32 ctlhi;
|
||||
unsigned int i = 0;
|
||||
|
||||
llp = channel_readq(idma64c, LLP);
|
||||
do {
|
||||
hw = &desc->hw[i];
|
||||
} while ((hw->llp != llp) && (++i < desc->ndesc));
|
||||
|
||||
if (!i)
|
||||
return bytes;
|
||||
|
||||
do {
|
||||
bytes -= desc->hw[--i].len;
|
||||
} while (i);
|
||||
|
||||
ctlhi = channel_readl(idma64c, CTL_HI);
|
||||
return bytes - IDMA64C_CTLH_BLOCK_TS(ctlhi);
|
||||
}
|
||||
|
||||
static enum dma_status idma64_tx_status(struct dma_chan *chan,
|
||||
dma_cookie_t cookie, struct dma_tx_state *state)
|
||||
{
|
||||
struct idma64_chan *idma64c = to_idma64_chan(chan);
|
||||
struct virt_dma_desc *vdesc;
|
||||
enum dma_status status;
|
||||
size_t bytes;
|
||||
unsigned long flags;
|
||||
|
||||
status = dma_cookie_status(chan, cookie, state);
|
||||
if (status == DMA_COMPLETE)
|
||||
return status;
|
||||
|
||||
spin_lock_irqsave(&idma64c->vchan.lock, flags);
|
||||
vdesc = vchan_find_desc(&idma64c->vchan, cookie);
|
||||
if (idma64c->desc && cookie == idma64c->desc->vdesc.tx.cookie) {
|
||||
bytes = idma64_active_desc_size(idma64c);
|
||||
dma_set_residue(state, bytes);
|
||||
status = idma64c->desc->status;
|
||||
} else if (vdesc) {
|
||||
bytes = to_idma64_desc(vdesc)->length;
|
||||
dma_set_residue(state, bytes);
|
||||
}
|
||||
spin_unlock_irqrestore(&idma64c->vchan.lock, flags);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
static void convert_burst(u32 *maxburst)
|
||||
{
|
||||
if (*maxburst)
|
||||
*maxburst = __fls(*maxburst);
|
||||
else
|
||||
*maxburst = 0;
|
||||
}
|
||||
|
||||
static int idma64_slave_config(struct dma_chan *chan,
|
||||
struct dma_slave_config *config)
|
||||
{
|
||||
struct idma64_chan *idma64c = to_idma64_chan(chan);
|
||||
|
||||
/* Check if chan will be configured for slave transfers */
|
||||
if (!is_slave_direction(config->direction))
|
||||
return -EINVAL;
|
||||
|
||||
memcpy(&idma64c->config, config, sizeof(idma64c->config));
|
||||
|
||||
convert_burst(&idma64c->config.src_maxburst);
|
||||
convert_burst(&idma64c->config.dst_maxburst);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void idma64_chan_deactivate(struct idma64_chan *idma64c)
|
||||
{
|
||||
unsigned short count = 100;
|
||||
u32 cfglo;
|
||||
|
||||
cfglo = channel_readl(idma64c, CFG_LO);
|
||||
channel_writel(idma64c, CFG_LO, cfglo | IDMA64C_CFGL_CH_SUSP);
|
||||
do {
|
||||
udelay(1);
|
||||
cfglo = channel_readl(idma64c, CFG_LO);
|
||||
} while (!(cfglo & IDMA64C_CFGL_FIFO_EMPTY) && --count);
|
||||
}
|
||||
|
||||
static void idma64_chan_activate(struct idma64_chan *idma64c)
|
||||
{
|
||||
u32 cfglo;
|
||||
|
||||
cfglo = channel_readl(idma64c, CFG_LO);
|
||||
channel_writel(idma64c, CFG_LO, cfglo & ~IDMA64C_CFGL_CH_SUSP);
|
||||
}
|
||||
|
||||
static int idma64_pause(struct dma_chan *chan)
|
||||
{
|
||||
struct idma64_chan *idma64c = to_idma64_chan(chan);
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&idma64c->vchan.lock, flags);
|
||||
if (idma64c->desc && idma64c->desc->status == DMA_IN_PROGRESS) {
|
||||
idma64_chan_deactivate(idma64c);
|
||||
idma64c->desc->status = DMA_PAUSED;
|
||||
}
|
||||
spin_unlock_irqrestore(&idma64c->vchan.lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int idma64_resume(struct dma_chan *chan)
|
||||
{
|
||||
struct idma64_chan *idma64c = to_idma64_chan(chan);
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&idma64c->vchan.lock, flags);
|
||||
if (idma64c->desc && idma64c->desc->status == DMA_PAUSED) {
|
||||
idma64c->desc->status = DMA_IN_PROGRESS;
|
||||
idma64_chan_activate(idma64c);
|
||||
}
|
||||
spin_unlock_irqrestore(&idma64c->vchan.lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int idma64_terminate_all(struct dma_chan *chan)
|
||||
{
|
||||
struct idma64_chan *idma64c = to_idma64_chan(chan);
|
||||
unsigned long flags;
|
||||
LIST_HEAD(head);
|
||||
|
||||
spin_lock_irqsave(&idma64c->vchan.lock, flags);
|
||||
idma64_chan_deactivate(idma64c);
|
||||
idma64_stop_transfer(idma64c);
|
||||
if (idma64c->desc) {
|
||||
idma64_vdesc_free(&idma64c->desc->vdesc);
|
||||
idma64c->desc = NULL;
|
||||
}
|
||||
vchan_get_all_descriptors(&idma64c->vchan, &head);
|
||||
spin_unlock_irqrestore(&idma64c->vchan.lock, flags);
|
||||
|
||||
vchan_dma_desc_free_list(&idma64c->vchan, &head);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int idma64_alloc_chan_resources(struct dma_chan *chan)
|
||||
{
|
||||
struct idma64_chan *idma64c = to_idma64_chan(chan);
|
||||
|
||||
/* Create a pool of consistent memory blocks for hardware descriptors */
|
||||
idma64c->pool = dma_pool_create(dev_name(chan2dev(chan)),
|
||||
chan->device->dev,
|
||||
sizeof(struct idma64_lli), 8, 0);
|
||||
if (!idma64c->pool) {
|
||||
dev_err(chan2dev(chan), "No memory for descriptors\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void idma64_free_chan_resources(struct dma_chan *chan)
|
||||
{
|
||||
struct idma64_chan *idma64c = to_idma64_chan(chan);
|
||||
|
||||
vchan_free_chan_resources(to_virt_chan(chan));
|
||||
dma_pool_destroy(idma64c->pool);
|
||||
idma64c->pool = NULL;
|
||||
}
|
||||
|
||||
/* ---------------------------------------------------------------------- */
|
||||
|
||||
#define IDMA64_BUSWIDTHS \
|
||||
BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
|
||||
BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
|
||||
BIT(DMA_SLAVE_BUSWIDTH_4_BYTES)
|
||||
|
||||
static int idma64_probe(struct idma64_chip *chip)
|
||||
{
|
||||
struct idma64 *idma64;
|
||||
unsigned short nr_chan = IDMA64_NR_CHAN;
|
||||
unsigned short i;
|
||||
int ret;
|
||||
|
||||
idma64 = devm_kzalloc(chip->dev, sizeof(*idma64), GFP_KERNEL);
|
||||
if (!idma64)
|
||||
return -ENOMEM;
|
||||
|
||||
idma64->regs = chip->regs;
|
||||
chip->idma64 = idma64;
|
||||
|
||||
idma64->chan = devm_kcalloc(chip->dev, nr_chan, sizeof(*idma64->chan),
|
||||
GFP_KERNEL);
|
||||
if (!idma64->chan)
|
||||
return -ENOMEM;
|
||||
|
||||
idma64->all_chan_mask = (1 << nr_chan) - 1;
|
||||
|
||||
/* Turn off iDMA controller */
|
||||
idma64_off(idma64);
|
||||
|
||||
ret = devm_request_irq(chip->dev, chip->irq, idma64_irq, IRQF_SHARED,
|
||||
dev_name(chip->dev), idma64);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
INIT_LIST_HEAD(&idma64->dma.channels);
|
||||
for (i = 0; i < nr_chan; i++) {
|
||||
struct idma64_chan *idma64c = &idma64->chan[i];
|
||||
|
||||
idma64c->vchan.desc_free = idma64_vdesc_free;
|
||||
vchan_init(&idma64c->vchan, &idma64->dma);
|
||||
|
||||
idma64c->regs = idma64->regs + i * IDMA64_CH_LENGTH;
|
||||
idma64c->mask = BIT(i);
|
||||
}
|
||||
|
||||
dma_cap_set(DMA_SLAVE, idma64->dma.cap_mask);
|
||||
dma_cap_set(DMA_PRIVATE, idma64->dma.cap_mask);
|
||||
|
||||
idma64->dma.device_alloc_chan_resources = idma64_alloc_chan_resources;
|
||||
idma64->dma.device_free_chan_resources = idma64_free_chan_resources;
|
||||
|
||||
idma64->dma.device_prep_slave_sg = idma64_prep_slave_sg;
|
||||
|
||||
idma64->dma.device_issue_pending = idma64_issue_pending;
|
||||
idma64->dma.device_tx_status = idma64_tx_status;
|
||||
|
||||
idma64->dma.device_config = idma64_slave_config;
|
||||
idma64->dma.device_pause = idma64_pause;
|
||||
idma64->dma.device_resume = idma64_resume;
|
||||
idma64->dma.device_terminate_all = idma64_terminate_all;
|
||||
|
||||
idma64->dma.src_addr_widths = IDMA64_BUSWIDTHS;
|
||||
idma64->dma.dst_addr_widths = IDMA64_BUSWIDTHS;
|
||||
idma64->dma.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
|
||||
idma64->dma.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
|
||||
|
||||
idma64->dma.dev = chip->dev;
|
||||
|
||||
ret = dma_async_device_register(&idma64->dma);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
dev_info(chip->dev, "Found Intel integrated DMA 64-bit\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int idma64_remove(struct idma64_chip *chip)
|
||||
{
|
||||
struct idma64 *idma64 = chip->idma64;
|
||||
unsigned short i;
|
||||
|
||||
dma_async_device_unregister(&idma64->dma);
|
||||
|
||||
/*
|
||||
* Explicitly call devm_request_irq() to avoid the side effects with
|
||||
* the scheduled tasklets.
|
||||
*/
|
||||
devm_free_irq(chip->dev, chip->irq, idma64);
|
||||
|
||||
for (i = 0; i < idma64->dma.chancnt; i++) {
|
||||
struct idma64_chan *idma64c = &idma64->chan[i];
|
||||
|
||||
tasklet_kill(&idma64c->vchan.task);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* ---------------------------------------------------------------------- */
|
||||
|
||||
static int idma64_platform_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct idma64_chip *chip;
|
||||
struct device *dev = &pdev->dev;
|
||||
struct resource *mem;
|
||||
int ret;
|
||||
|
||||
chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
|
||||
if (!chip)
|
||||
return -ENOMEM;
|
||||
|
||||
chip->irq = platform_get_irq(pdev, 0);
|
||||
if (chip->irq < 0)
|
||||
return chip->irq;
|
||||
|
||||
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
chip->regs = devm_ioremap_resource(dev, mem);
|
||||
if (IS_ERR(chip->regs))
|
||||
return PTR_ERR(chip->regs);
|
||||
|
||||
ret = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
chip->dev = dev;
|
||||
|
||||
ret = idma64_probe(chip);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
platform_set_drvdata(pdev, chip);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int idma64_platform_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct idma64_chip *chip = platform_get_drvdata(pdev);
|
||||
|
||||
return idma64_remove(chip);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
|
||||
static int idma64_pm_suspend(struct device *dev)
|
||||
{
|
||||
struct platform_device *pdev = to_platform_device(dev);
|
||||
struct idma64_chip *chip = platform_get_drvdata(pdev);
|
||||
|
||||
idma64_off(chip->idma64);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int idma64_pm_resume(struct device *dev)
|
||||
{
|
||||
struct platform_device *pdev = to_platform_device(dev);
|
||||
struct idma64_chip *chip = platform_get_drvdata(pdev);
|
||||
|
||||
idma64_on(chip->idma64);
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_PM_SLEEP */
|
||||
|
||||
static const struct dev_pm_ops idma64_dev_pm_ops = {
|
||||
SET_SYSTEM_SLEEP_PM_OPS(idma64_pm_suspend, idma64_pm_resume)
|
||||
};
|
||||
|
||||
static struct platform_driver idma64_platform_driver = {
|
||||
.probe = idma64_platform_probe,
|
||||
.remove = idma64_platform_remove,
|
||||
.driver = {
|
||||
.name = DRV_NAME,
|
||||
.pm = &idma64_dev_pm_ops,
|
||||
},
|
||||
};
|
||||
|
||||
module_platform_driver(idma64_platform_driver);
|
||||
|
||||
MODULE_LICENSE("GPL v2");
|
||||
MODULE_DESCRIPTION("iDMA64 core driver");
|
||||
MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
|
||||
MODULE_ALIAS("platform:" DRV_NAME);
|
||||
233
drivers/dma/idma64.h
Archivo normal
233
drivers/dma/idma64.h
Archivo normal
@@ -0,0 +1,233 @@
|
||||
/*
|
||||
* Driver for the Intel integrated DMA 64-bit
|
||||
*
|
||||
* Copyright (C) 2015 Intel Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __DMA_IDMA64_H__
|
||||
#define __DMA_IDMA64_H__
|
||||
|
||||
#include <linux/device.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/types.h>
|
||||
|
||||
#include "virt-dma.h"
|
||||
|
||||
/* Channel registers */
|
||||
|
||||
#define IDMA64_CH_SAR 0x00 /* Source Address Register */
|
||||
#define IDMA64_CH_DAR 0x08 /* Destination Address Register */
|
||||
#define IDMA64_CH_LLP 0x10 /* Linked List Pointer */
|
||||
#define IDMA64_CH_CTL_LO 0x18 /* Control Register Low */
|
||||
#define IDMA64_CH_CTL_HI 0x1c /* Control Register High */
|
||||
#define IDMA64_CH_SSTAT 0x20
|
||||
#define IDMA64_CH_DSTAT 0x28
|
||||
#define IDMA64_CH_SSTATAR 0x30
|
||||
#define IDMA64_CH_DSTATAR 0x38
|
||||
#define IDMA64_CH_CFG_LO 0x40 /* Configuration Register Low */
|
||||
#define IDMA64_CH_CFG_HI 0x44 /* Configuration Register High */
|
||||
#define IDMA64_CH_SGR 0x48
|
||||
#define IDMA64_CH_DSR 0x50
|
||||
|
||||
#define IDMA64_CH_LENGTH 0x58
|
||||
|
||||
/* Bitfields in CTL_LO */
|
||||
#define IDMA64C_CTLL_INT_EN (1 << 0) /* irqs enabled? */
|
||||
#define IDMA64C_CTLL_DST_WIDTH(x) ((x) << 1) /* bytes per element */
|
||||
#define IDMA64C_CTLL_SRC_WIDTH(x) ((x) << 4)
|
||||
#define IDMA64C_CTLL_DST_INC (0 << 8) /* DAR update/not */
|
||||
#define IDMA64C_CTLL_DST_FIX (1 << 8)
|
||||
#define IDMA64C_CTLL_SRC_INC (0 << 10) /* SAR update/not */
|
||||
#define IDMA64C_CTLL_SRC_FIX (1 << 10)
|
||||
#define IDMA64C_CTLL_DST_MSIZE(x) ((x) << 11) /* burst, #elements */
|
||||
#define IDMA64C_CTLL_SRC_MSIZE(x) ((x) << 14)
|
||||
#define IDMA64C_CTLL_FC_M2P (1 << 20) /* mem-to-periph */
|
||||
#define IDMA64C_CTLL_FC_P2M (2 << 20) /* periph-to-mem */
|
||||
#define IDMA64C_CTLL_LLP_D_EN (1 << 27) /* dest block chain */
|
||||
#define IDMA64C_CTLL_LLP_S_EN (1 << 28) /* src block chain */
|
||||
|
||||
/* Bitfields in CTL_HI */
|
||||
#define IDMA64C_CTLH_BLOCK_TS(x) ((x) & ((1 << 17) - 1))
|
||||
#define IDMA64C_CTLH_DONE (1 << 17)
|
||||
|
||||
/* Bitfields in CFG_LO */
|
||||
#define IDMA64C_CFGL_DST_BURST_ALIGN (1 << 0) /* dst burst align */
|
||||
#define IDMA64C_CFGL_SRC_BURST_ALIGN (1 << 1) /* src burst align */
|
||||
#define IDMA64C_CFGL_CH_SUSP (1 << 8)
|
||||
#define IDMA64C_CFGL_FIFO_EMPTY (1 << 9)
|
||||
#define IDMA64C_CFGL_CH_DRAIN (1 << 10) /* drain FIFO */
|
||||
#define IDMA64C_CFGL_DST_OPT_BL (1 << 20) /* optimize dst burst length */
|
||||
#define IDMA64C_CFGL_SRC_OPT_BL (1 << 21) /* optimize src burst length */
|
||||
|
||||
/* Bitfields in CFG_HI */
|
||||
#define IDMA64C_CFGH_SRC_PER(x) ((x) << 0) /* src peripheral */
|
||||
#define IDMA64C_CFGH_DST_PER(x) ((x) << 4) /* dst peripheral */
|
||||
#define IDMA64C_CFGH_RD_ISSUE_THD(x) ((x) << 8)
|
||||
#define IDMA64C_CFGH_RW_ISSUE_THD(x) ((x) << 18)
|
||||
|
||||
/* Interrupt registers */
|
||||
|
||||
#define IDMA64_INT_XFER 0x00
|
||||
#define IDMA64_INT_BLOCK 0x08
|
||||
#define IDMA64_INT_SRC_TRAN 0x10
|
||||
#define IDMA64_INT_DST_TRAN 0x18
|
||||
#define IDMA64_INT_ERROR 0x20
|
||||
|
||||
#define IDMA64_RAW(x) (0x2c0 + IDMA64_INT_##x) /* r */
|
||||
#define IDMA64_STATUS(x) (0x2e8 + IDMA64_INT_##x) /* r (raw & mask) */
|
||||
#define IDMA64_MASK(x) (0x310 + IDMA64_INT_##x) /* rw (set = irq enabled) */
|
||||
#define IDMA64_CLEAR(x) (0x338 + IDMA64_INT_##x) /* w (ack, affects "raw") */
|
||||
|
||||
/* Common registers */
|
||||
|
||||
#define IDMA64_STATUS_INT 0x360 /* r */
|
||||
#define IDMA64_CFG 0x398
|
||||
#define IDMA64_CH_EN 0x3a0
|
||||
|
||||
/* Bitfields in CFG */
|
||||
#define IDMA64_CFG_DMA_EN (1 << 0)
|
||||
|
||||
/* Hardware descriptor for Linked LIst transfers */
|
||||
struct idma64_lli {
|
||||
u64 sar;
|
||||
u64 dar;
|
||||
u64 llp;
|
||||
u32 ctllo;
|
||||
u32 ctlhi;
|
||||
u32 sstat;
|
||||
u32 dstat;
|
||||
};
|
||||
|
||||
struct idma64_hw_desc {
|
||||
struct idma64_lli *lli;
|
||||
dma_addr_t llp;
|
||||
dma_addr_t phys;
|
||||
unsigned int len;
|
||||
};
|
||||
|
||||
struct idma64_desc {
|
||||
struct virt_dma_desc vdesc;
|
||||
enum dma_transfer_direction direction;
|
||||
struct idma64_hw_desc *hw;
|
||||
unsigned int ndesc;
|
||||
size_t length;
|
||||
enum dma_status status;
|
||||
};
|
||||
|
||||
static inline struct idma64_desc *to_idma64_desc(struct virt_dma_desc *vdesc)
|
||||
{
|
||||
return container_of(vdesc, struct idma64_desc, vdesc);
|
||||
}
|
||||
|
||||
struct idma64_chan {
|
||||
struct virt_dma_chan vchan;
|
||||
|
||||
void __iomem *regs;
|
||||
|
||||
/* hardware configuration */
|
||||
enum dma_transfer_direction direction;
|
||||
unsigned int mask;
|
||||
struct dma_slave_config config;
|
||||
|
||||
void *pool;
|
||||
struct idma64_desc *desc;
|
||||
};
|
||||
|
||||
static inline struct idma64_chan *to_idma64_chan(struct dma_chan *chan)
|
||||
{
|
||||
return container_of(chan, struct idma64_chan, vchan.chan);
|
||||
}
|
||||
|
||||
#define channel_set_bit(idma64, reg, mask) \
|
||||
dma_writel(idma64, reg, ((mask) << 8) | (mask))
|
||||
#define channel_clear_bit(idma64, reg, mask) \
|
||||
dma_writel(idma64, reg, ((mask) << 8) | 0)
|
||||
|
||||
static inline u32 idma64c_readl(struct idma64_chan *idma64c, int offset)
|
||||
{
|
||||
return readl(idma64c->regs + offset);
|
||||
}
|
||||
|
||||
static inline void idma64c_writel(struct idma64_chan *idma64c, int offset,
|
||||
u32 value)
|
||||
{
|
||||
writel(value, idma64c->regs + offset);
|
||||
}
|
||||
|
||||
#define channel_readl(idma64c, reg) \
|
||||
idma64c_readl(idma64c, IDMA64_CH_##reg)
|
||||
#define channel_writel(idma64c, reg, value) \
|
||||
idma64c_writel(idma64c, IDMA64_CH_##reg, (value))
|
||||
|
||||
static inline u64 idma64c_readq(struct idma64_chan *idma64c, int offset)
|
||||
{
|
||||
u64 l, h;
|
||||
|
||||
l = idma64c_readl(idma64c, offset);
|
||||
h = idma64c_readl(idma64c, offset + 4);
|
||||
|
||||
return l | (h << 32);
|
||||
}
|
||||
|
||||
static inline void idma64c_writeq(struct idma64_chan *idma64c, int offset,
|
||||
u64 value)
|
||||
{
|
||||
idma64c_writel(idma64c, offset, value);
|
||||
idma64c_writel(idma64c, offset + 4, value >> 32);
|
||||
}
|
||||
|
||||
#define channel_readq(idma64c, reg) \
|
||||
idma64c_readq(idma64c, IDMA64_CH_##reg)
|
||||
#define channel_writeq(idma64c, reg, value) \
|
||||
idma64c_writeq(idma64c, IDMA64_CH_##reg, (value))
|
||||
|
||||
struct idma64 {
|
||||
struct dma_device dma;
|
||||
|
||||
void __iomem *regs;
|
||||
|
||||
/* channels */
|
||||
unsigned short all_chan_mask;
|
||||
struct idma64_chan *chan;
|
||||
};
|
||||
|
||||
static inline struct idma64 *to_idma64(struct dma_device *ddev)
|
||||
{
|
||||
return container_of(ddev, struct idma64, dma);
|
||||
}
|
||||
|
||||
static inline u32 idma64_readl(struct idma64 *idma64, int offset)
|
||||
{
|
||||
return readl(idma64->regs + offset);
|
||||
}
|
||||
|
||||
static inline void idma64_writel(struct idma64 *idma64, int offset, u32 value)
|
||||
{
|
||||
writel(value, idma64->regs + offset);
|
||||
}
|
||||
|
||||
#define dma_readl(idma64, reg) \
|
||||
idma64_readl(idma64, IDMA64_##reg)
|
||||
#define dma_writel(idma64, reg, value) \
|
||||
idma64_writel(idma64, IDMA64_##reg, (value))
|
||||
|
||||
/**
|
||||
* struct idma64_chip - representation of DesignWare DMA controller hardware
|
||||
* @dev: struct device of the DMA controller
|
||||
* @irq: irq line
|
||||
* @regs: memory mapped I/O space
|
||||
* @idma64: struct idma64 that is filed by idma64_probe()
|
||||
*/
|
||||
struct idma64_chip {
|
||||
struct device *dev;
|
||||
int irq;
|
||||
void __iomem *regs;
|
||||
struct idma64 *idma64;
|
||||
};
|
||||
|
||||
#endif /* __DMA_IDMA64_H__ */
|
||||
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