Merge tag 'ti-k3-dt-for-v5.10-part2' of git://git.kernel.org/pub/scm/linux/kernel/git/nmenon/linux into arm/dt
Second and final device tree updates towards 5.10-rc1 for TI K3 platform. * tag 'ti-k3-dt-for-v5.10-part2' of git://git.kernel.org/pub/scm/linux/kernel/git/nmenon/linux: (23 commits) arm64: dts: ti: k3-j7200-common-proc-board: Add USB support arm64: dts: ti: k3-j7200-common-proc-board: Configure the SERDES lane function arm64: dts: ti: k3-j7200-main: Add USB controller arm64: dts: ti: k3-j7200-main.dtsi: Add USB to SERDES lane MUX arm64: dts: ti: k3-j7200-main: Add SERDES lane control mux dt-bindings: ti-serdes-mux: Add defines for J7200 SoC arm64: dts: ti: k3-j721e-common-proc-board: align GPIO hog names with dtschema arm64: dts: ti: k3-j7200-common-proc-board: Add support for eMMC and SD card arm64: dts: ti: k3-j7200-main: Add support for MMC/SD controller nodes arm64: dts: ti: k3-j7200-som-p0: Add HyperFlash node arm64: dts: ti: k3-j7200-mcu-wakeup: Add HyperBus node arm64: dts: ti: k3-j7200-common-proc-board: Add I2C IO expanders arm64: dts: ti: k3-j7200: Add I2C nodes arm64: dts: ti: k3-j7200-common-proc-board: add mcu cpsw nuss pinmux and phy defs arm64: dts: ti: k3-j7200-mcu: add mcu cpsw nuss node arm64: dts: ti: k3-j7200-main: add main navss cpts node arm64: dts: ti: k3-j7200: add DMA support arm64: dts: ti: Add support for J7200 Common Processor Board arm64: dts: ti: Add support for J7200 SoC dt-bindings: arm: ti: Add bindings for J7200 SoC ... Link: https://lore.kernel.org/r/20201002134559.orvmgbns57qlyn3i@akan Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* This header provides constants for J721E WIZ.
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*/
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#ifndef _DT_BINDINGS_J721E_WIZ
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#define _DT_BINDINGS_J721E_WIZ
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#define SERDES0_LANE0_QSGMII_LANE1 0x0
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#define SERDES0_LANE0_PCIE0_LANE0 0x1
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#define SERDES0_LANE0_USB3_0_SWAP 0x2
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#define SERDES0_LANE1_QSGMII_LANE2 0x0
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#define SERDES0_LANE1_PCIE0_LANE1 0x1
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#define SERDES0_LANE1_USB3_0 0x2
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#define SERDES1_LANE0_QSGMII_LANE3 0x0
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#define SERDES1_LANE0_PCIE1_LANE0 0x1
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#define SERDES1_LANE0_USB3_1_SWAP 0x2
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#define SERDES1_LANE0_SGMII_LANE0 0x3
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#define SERDES1_LANE1_QSGMII_LANE4 0x0
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#define SERDES1_LANE1_PCIE1_LANE1 0x1
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#define SERDES1_LANE1_USB3_1 0x2
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#define SERDES1_LANE1_SGMII_LANE1 0x3
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#define SERDES2_LANE0_PCIE2_LANE0 0x1
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#define SERDES2_LANE0_SGMII_LANE0 0x3
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#define SERDES2_LANE0_USB3_1_SWAP 0x2
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#define SERDES2_LANE1_PCIE2_LANE1 0x1
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#define SERDES2_LANE1_USB3_1 0x2
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#define SERDES2_LANE1_SGMII_LANE1 0x3
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#define SERDES3_LANE0_PCIE3_LANE0 0x1
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#define SERDES3_LANE0_USB3_0_SWAP 0x2
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#define SERDES3_LANE1_PCIE3_LANE1 0x1
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#define SERDES3_LANE1_USB3_0 0x2
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#define SERDES4_LANE0_EDP_LANE0 0x0
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#define SERDES4_LANE0_QSGMII_LANE5 0x2
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#define SERDES4_LANE1_EDP_LANE1 0x0
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#define SERDES4_LANE1_QSGMII_LANE6 0x2
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#define SERDES4_LANE2_EDP_LANE2 0x0
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#define SERDES4_LANE2_QSGMII_LANE7 0x2
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#define SERDES4_LANE3_EDP_LANE3 0x0
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#define SERDES4_LANE3_QSGMII_LANE8 0x2
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#endif /* _DT_BINDINGS_J721E_WIZ */
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93
include/dt-bindings/mux/ti-serdes.h
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93
include/dt-bindings/mux/ti-serdes.h
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* This header provides constants for SERDES MUX for TI SoCs
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*/
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#ifndef _DT_BINDINGS_MUX_TI_SERDES
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#define _DT_BINDINGS_MUX_TI_SERDES
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/* J721E */
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#define J721E_SERDES0_LANE0_QSGMII_LANE1 0x0
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#define J721E_SERDES0_LANE0_PCIE0_LANE0 0x1
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#define J721E_SERDES0_LANE0_USB3_0_SWAP 0x2
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#define J721E_SERDES0_LANE0_IP4_UNUSED 0x3
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#define J721E_SERDES0_LANE1_QSGMII_LANE2 0x0
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#define J721E_SERDES0_LANE1_PCIE0_LANE1 0x1
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#define J721E_SERDES0_LANE1_USB3_0 0x2
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#define J721E_SERDES0_LANE1_IP4_UNUSED 0x3
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#define J721E_SERDES1_LANE0_QSGMII_LANE3 0x0
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#define J721E_SERDES1_LANE0_PCIE1_LANE0 0x1
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#define J721E_SERDES1_LANE0_USB3_1_SWAP 0x2
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#define J721E_SERDES1_LANE0_SGMII_LANE0 0x3
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#define J721E_SERDES1_LANE1_QSGMII_LANE4 0x0
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#define J721E_SERDES1_LANE1_PCIE1_LANE1 0x1
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#define J721E_SERDES1_LANE1_USB3_1 0x2
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#define J721E_SERDES1_LANE1_SGMII_LANE1 0x3
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#define J721E_SERDES2_LANE0_IP1_UNUSED 0x0
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#define J721E_SERDES2_LANE0_PCIE2_LANE0 0x1
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#define J721E_SERDES2_LANE0_USB3_1_SWAP 0x2
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#define J721E_SERDES2_LANE0_SGMII_LANE0 0x3
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#define J721E_SERDES2_LANE1_IP1_UNUSED 0x0
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#define J721E_SERDES2_LANE1_PCIE2_LANE1 0x1
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#define J721E_SERDES2_LANE1_USB3_1 0x2
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#define J721E_SERDES2_LANE1_SGMII_LANE1 0x3
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#define J721E_SERDES3_LANE0_IP1_UNUSED 0x0
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#define J721E_SERDES3_LANE0_PCIE3_LANE0 0x1
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#define J721E_SERDES3_LANE0_USB3_0_SWAP 0x2
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#define J721E_SERDES3_LANE0_IP4_UNUSED 0x3
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#define J721E_SERDES3_LANE1_IP1_UNUSED 0x0
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#define J721E_SERDES3_LANE1_PCIE3_LANE1 0x1
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#define J721E_SERDES3_LANE1_USB3_0 0x2
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#define J721E_SERDES3_LANE1_IP4_UNUSED 0x3
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#define J721E_SERDES4_LANE0_EDP_LANE0 0x0
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#define J721E_SERDES4_LANE0_IP2_UNUSED 0x1
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#define J721E_SERDES4_LANE0_QSGMII_LANE5 0x2
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#define J721E_SERDES4_LANE0_IP4_UNUSED 0x3
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#define J721E_SERDES4_LANE1_EDP_LANE1 0x0
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#define J721E_SERDES4_LANE1_IP2_UNUSED 0x1
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#define J721E_SERDES4_LANE1_QSGMII_LANE6 0x2
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#define J721E_SERDES4_LANE1_IP4_UNUSED 0x3
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#define J721E_SERDES4_LANE2_EDP_LANE2 0x0
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#define J721E_SERDES4_LANE2_IP2_UNUSED 0x1
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#define J721E_SERDES4_LANE2_QSGMII_LANE7 0x2
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#define J721E_SERDES4_LANE2_IP4_UNUSED 0x3
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#define J721E_SERDES4_LANE3_EDP_LANE3 0x0
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#define J721E_SERDES4_LANE3_IP2_UNUSED 0x1
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#define J721E_SERDES4_LANE3_QSGMII_LANE8 0x2
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#define J721E_SERDES4_LANE3_IP4_UNUSED 0x3
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/* J7200 */
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#define J7200_SERDES0_LANE0_QSGMII_LANE3 0x0
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#define J7200_SERDES0_LANE0_PCIE1_LANE0 0x1
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#define J7200_SERDES0_LANE0_IP3_UNUSED 0x2
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#define J7200_SERDES0_LANE0_IP4_UNUSED 0x3
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#define J7200_SERDES0_LANE1_QSGMII_LANE4 0x0
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#define J7200_SERDES0_LANE1_PCIE1_LANE1 0x1
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#define J7200_SERDES0_LANE1_IP3_UNUSED 0x2
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#define J7200_SERDES0_LANE1_IP4_UNUSED 0x3
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#define J7200_SERDES0_LANE2_QSGMII_LANE1 0x0
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#define J7200_SERDES0_LANE2_PCIE1_LANE2 0x1
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#define J7200_SERDES0_LANE2_IP3_UNUSED 0x2
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#define J7200_SERDES0_LANE2_IP4_UNUSED 0x3
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#define J7200_SERDES0_LANE3_QSGMII_LANE2 0x0
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#define J7200_SERDES0_LANE3_PCIE1_LANE3 0x1
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#define J7200_SERDES0_LANE3_USB 0x2
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#define J7200_SERDES0_LANE3_IP4_UNUSED 0x3
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#endif /* _DT_BINDINGS_MUX_TI_SERDES */
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