drm/radeon: add set_uvd_clocks callback for r7xx v3
v2: avoid 64bit divide v3: rv740 uses the evegreen upll configuration Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Jerome Glisse <jglisse@redhat.com>
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committed by
Alex Deucher

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2539eb02de
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ef0e6e657c
@@ -1183,6 +1183,7 @@ static struct radeon_asic rv770_asic = {
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.get_pcie_lanes = &r600_get_pcie_lanes,
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.set_pcie_lanes = &r600_set_pcie_lanes,
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.set_clock_gating = &radeon_atom_set_clock_gating,
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.set_uvd_clocks = &rv770_set_uvd_clocks,
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},
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.pflip = {
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.pre_page_flip = &rs600_pre_page_flip,
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