MIPS: Save/restore MSA context around signals
This patch extends sigcontext in order to hold the most significant 64 bits of each vector register in addition to the MSA control & status register. The least significant 64 bits are already saved as the scalar FP context. This makes things a little awkward since the least & most significant 64 bits of each vector register are not contiguous in memory. Thus the copy_u & insert instructions are used to transfer the values of the most significant 64 bits via GP registers. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6533/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Paul Burton
committed by
Ralf Baechle
Ralf Baechle
parent
a8ad136789
commit
eec43a224c
@@ -13,6 +13,7 @@
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* Copyright (C) 1999, 2001 Silicon Graphics, Inc.
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*/
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#include <asm/asm.h>
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#include <asm/asmmacro.h>
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#include <asm/errno.h>
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#include <asm/fpregdef.h>
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#include <asm/mipsregs.h>
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@@ -245,6 +246,218 @@ LEAF(_restore_fp_context32)
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END(_restore_fp_context32)
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#endif
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#ifdef CONFIG_CPU_HAS_MSA
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.macro save_sc_msareg wr, off, sc, tmp
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#ifdef CONFIG_64BIT
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copy_u_d \tmp, \wr, 1
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EX sd \tmp, (\off+(\wr*8))(\sc)
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#elif defined(CONFIG_CPU_LITTLE_ENDIAN)
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copy_u_w \tmp, \wr, 2
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EX sw \tmp, (\off+(\wr*8)+0)(\sc)
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copy_u_w \tmp, \wr, 3
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EX sw \tmp, (\off+(\wr*8)+4)(\sc)
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#else /* CONFIG_CPU_BIG_ENDIAN */
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copy_u_w \tmp, \wr, 2
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EX sw \tmp, (\off+(\wr*8)+4)(\sc)
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copy_u_w \tmp, \wr, 3
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EX sw \tmp, (\off+(\wr*8)+0)(\sc)
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#endif
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.endm
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/*
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* int _save_msa_context(struct sigcontext *sc)
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*
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* Save the upper 64 bits of each vector register along with the MSA_CSR
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* register into sc. Returns zero on success, else non-zero.
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*/
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LEAF(_save_msa_context)
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save_sc_msareg 0, SC_MSAREGS, a0, t0
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save_sc_msareg 1, SC_MSAREGS, a0, t0
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save_sc_msareg 2, SC_MSAREGS, a0, t0
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save_sc_msareg 3, SC_MSAREGS, a0, t0
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save_sc_msareg 4, SC_MSAREGS, a0, t0
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save_sc_msareg 5, SC_MSAREGS, a0, t0
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save_sc_msareg 6, SC_MSAREGS, a0, t0
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save_sc_msareg 7, SC_MSAREGS, a0, t0
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save_sc_msareg 8, SC_MSAREGS, a0, t0
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save_sc_msareg 9, SC_MSAREGS, a0, t0
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save_sc_msareg 10, SC_MSAREGS, a0, t0
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save_sc_msareg 11, SC_MSAREGS, a0, t0
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save_sc_msareg 12, SC_MSAREGS, a0, t0
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save_sc_msareg 13, SC_MSAREGS, a0, t0
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save_sc_msareg 14, SC_MSAREGS, a0, t0
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save_sc_msareg 15, SC_MSAREGS, a0, t0
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save_sc_msareg 16, SC_MSAREGS, a0, t0
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save_sc_msareg 17, SC_MSAREGS, a0, t0
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save_sc_msareg 18, SC_MSAREGS, a0, t0
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save_sc_msareg 19, SC_MSAREGS, a0, t0
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save_sc_msareg 20, SC_MSAREGS, a0, t0
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save_sc_msareg 21, SC_MSAREGS, a0, t0
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save_sc_msareg 22, SC_MSAREGS, a0, t0
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save_sc_msareg 23, SC_MSAREGS, a0, t0
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save_sc_msareg 24, SC_MSAREGS, a0, t0
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save_sc_msareg 25, SC_MSAREGS, a0, t0
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save_sc_msareg 26, SC_MSAREGS, a0, t0
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save_sc_msareg 27, SC_MSAREGS, a0, t0
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save_sc_msareg 28, SC_MSAREGS, a0, t0
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save_sc_msareg 29, SC_MSAREGS, a0, t0
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save_sc_msareg 30, SC_MSAREGS, a0, t0
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save_sc_msareg 31, SC_MSAREGS, a0, t0
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jr ra
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li v0, 0
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END(_save_msa_context)
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#ifdef CONFIG_MIPS32_COMPAT
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/*
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* int _save_msa_context32(struct sigcontext32 *sc)
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*
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* Save the upper 64 bits of each vector register along with the MSA_CSR
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* register into sc. Returns zero on success, else non-zero.
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*/
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LEAF(_save_msa_context32)
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save_sc_msareg 0, SC32_MSAREGS, a0, t0
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save_sc_msareg 1, SC32_MSAREGS, a0, t0
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save_sc_msareg 2, SC32_MSAREGS, a0, t0
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save_sc_msareg 3, SC32_MSAREGS, a0, t0
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save_sc_msareg 4, SC32_MSAREGS, a0, t0
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save_sc_msareg 5, SC32_MSAREGS, a0, t0
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save_sc_msareg 6, SC32_MSAREGS, a0, t0
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save_sc_msareg 7, SC32_MSAREGS, a0, t0
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save_sc_msareg 8, SC32_MSAREGS, a0, t0
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save_sc_msareg 9, SC32_MSAREGS, a0, t0
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save_sc_msareg 10, SC32_MSAREGS, a0, t0
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save_sc_msareg 11, SC32_MSAREGS, a0, t0
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save_sc_msareg 12, SC32_MSAREGS, a0, t0
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save_sc_msareg 13, SC32_MSAREGS, a0, t0
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save_sc_msareg 14, SC32_MSAREGS, a0, t0
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save_sc_msareg 15, SC32_MSAREGS, a0, t0
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save_sc_msareg 16, SC32_MSAREGS, a0, t0
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save_sc_msareg 17, SC32_MSAREGS, a0, t0
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save_sc_msareg 18, SC32_MSAREGS, a0, t0
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save_sc_msareg 19, SC32_MSAREGS, a0, t0
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save_sc_msareg 20, SC32_MSAREGS, a0, t0
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save_sc_msareg 21, SC32_MSAREGS, a0, t0
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save_sc_msareg 22, SC32_MSAREGS, a0, t0
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save_sc_msareg 23, SC32_MSAREGS, a0, t0
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save_sc_msareg 24, SC32_MSAREGS, a0, t0
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save_sc_msareg 25, SC32_MSAREGS, a0, t0
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save_sc_msareg 26, SC32_MSAREGS, a0, t0
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save_sc_msareg 27, SC32_MSAREGS, a0, t0
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save_sc_msareg 28, SC32_MSAREGS, a0, t0
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save_sc_msareg 29, SC32_MSAREGS, a0, t0
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save_sc_msareg 30, SC32_MSAREGS, a0, t0
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save_sc_msareg 31, SC32_MSAREGS, a0, t0
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jr ra
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li v0, 0
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END(_save_msa_context32)
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#endif /* CONFIG_MIPS32_COMPAT */
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.macro restore_sc_msareg wr, off, sc, tmp
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#ifdef CONFIG_64BIT
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EX ld \tmp, (\off+(\wr*8))(\sc)
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insert_d \wr, 1, \tmp
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#elif defined(CONFIG_CPU_LITTLE_ENDIAN)
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EX lw \tmp, (\off+(\wr*8)+0)(\sc)
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insert_w \wr, 2, \tmp
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EX lw \tmp, (\off+(\wr*8)+4)(\sc)
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insert_w \wr, 3, \tmp
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#else /* CONFIG_CPU_BIG_ENDIAN */
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EX lw \tmp, (\off+(\wr*8)+4)(\sc)
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insert_w \wr, 2, \tmp
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EX lw \tmp, (\off+(\wr*8)+0)(\sc)
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insert_w \wr, 3, \tmp
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#endif
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.endm
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/*
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* int _restore_msa_context(struct sigcontext *sc)
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*/
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LEAF(_restore_msa_context)
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restore_sc_msareg 0, SC_MSAREGS, a0, t0
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restore_sc_msareg 1, SC_MSAREGS, a0, t0
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restore_sc_msareg 2, SC_MSAREGS, a0, t0
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restore_sc_msareg 3, SC_MSAREGS, a0, t0
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restore_sc_msareg 4, SC_MSAREGS, a0, t0
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restore_sc_msareg 5, SC_MSAREGS, a0, t0
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restore_sc_msareg 6, SC_MSAREGS, a0, t0
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restore_sc_msareg 7, SC_MSAREGS, a0, t0
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restore_sc_msareg 8, SC_MSAREGS, a0, t0
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restore_sc_msareg 9, SC_MSAREGS, a0, t0
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restore_sc_msareg 10, SC_MSAREGS, a0, t0
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restore_sc_msareg 11, SC_MSAREGS, a0, t0
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restore_sc_msareg 12, SC_MSAREGS, a0, t0
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restore_sc_msareg 13, SC_MSAREGS, a0, t0
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restore_sc_msareg 14, SC_MSAREGS, a0, t0
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restore_sc_msareg 15, SC_MSAREGS, a0, t0
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restore_sc_msareg 16, SC_MSAREGS, a0, t0
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restore_sc_msareg 17, SC_MSAREGS, a0, t0
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restore_sc_msareg 18, SC_MSAREGS, a0, t0
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restore_sc_msareg 19, SC_MSAREGS, a0, t0
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restore_sc_msareg 20, SC_MSAREGS, a0, t0
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restore_sc_msareg 21, SC_MSAREGS, a0, t0
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restore_sc_msareg 22, SC_MSAREGS, a0, t0
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restore_sc_msareg 23, SC_MSAREGS, a0, t0
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restore_sc_msareg 24, SC_MSAREGS, a0, t0
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restore_sc_msareg 25, SC_MSAREGS, a0, t0
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restore_sc_msareg 26, SC_MSAREGS, a0, t0
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restore_sc_msareg 27, SC_MSAREGS, a0, t0
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restore_sc_msareg 28, SC_MSAREGS, a0, t0
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restore_sc_msareg 29, SC_MSAREGS, a0, t0
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restore_sc_msareg 30, SC_MSAREGS, a0, t0
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restore_sc_msareg 31, SC_MSAREGS, a0, t0
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jr ra
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li v0, 0
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END(_restore_msa_context)
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#ifdef CONFIG_MIPS32_COMPAT
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/*
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* int _restore_msa_context32(struct sigcontext32 *sc)
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*/
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LEAF(_restore_msa_context32)
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restore_sc_msareg 0, SC32_MSAREGS, a0, t0
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restore_sc_msareg 1, SC32_MSAREGS, a0, t0
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restore_sc_msareg 2, SC32_MSAREGS, a0, t0
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restore_sc_msareg 3, SC32_MSAREGS, a0, t0
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restore_sc_msareg 4, SC32_MSAREGS, a0, t0
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restore_sc_msareg 5, SC32_MSAREGS, a0, t0
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restore_sc_msareg 6, SC32_MSAREGS, a0, t0
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restore_sc_msareg 7, SC32_MSAREGS, a0, t0
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restore_sc_msareg 8, SC32_MSAREGS, a0, t0
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restore_sc_msareg 9, SC32_MSAREGS, a0, t0
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restore_sc_msareg 10, SC32_MSAREGS, a0, t0
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restore_sc_msareg 11, SC32_MSAREGS, a0, t0
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restore_sc_msareg 12, SC32_MSAREGS, a0, t0
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restore_sc_msareg 13, SC32_MSAREGS, a0, t0
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restore_sc_msareg 14, SC32_MSAREGS, a0, t0
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restore_sc_msareg 15, SC32_MSAREGS, a0, t0
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restore_sc_msareg 16, SC32_MSAREGS, a0, t0
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restore_sc_msareg 17, SC32_MSAREGS, a0, t0
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restore_sc_msareg 18, SC32_MSAREGS, a0, t0
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restore_sc_msareg 19, SC32_MSAREGS, a0, t0
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restore_sc_msareg 20, SC32_MSAREGS, a0, t0
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restore_sc_msareg 21, SC32_MSAREGS, a0, t0
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restore_sc_msareg 22, SC32_MSAREGS, a0, t0
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restore_sc_msareg 23, SC32_MSAREGS, a0, t0
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restore_sc_msareg 24, SC32_MSAREGS, a0, t0
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restore_sc_msareg 25, SC32_MSAREGS, a0, t0
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restore_sc_msareg 26, SC32_MSAREGS, a0, t0
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restore_sc_msareg 27, SC32_MSAREGS, a0, t0
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restore_sc_msareg 28, SC32_MSAREGS, a0, t0
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restore_sc_msareg 29, SC32_MSAREGS, a0, t0
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restore_sc_msareg 30, SC32_MSAREGS, a0, t0
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restore_sc_msareg 31, SC32_MSAREGS, a0, t0
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jr ra
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li v0, 0
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END(_restore_msa_context32)
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#endif /* CONFIG_MIPS32_COMPAT */
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#endif /* CONFIG_CPU_HAS_MSA */
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.set reorder
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.type fault@function
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