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Merge tag 'arc-4.14-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc

Browse Source 
Pull ARC updates from Vineet Gupta:

 - Support for HSDK board hosting a Quad core HS38x4 based SoC running
   @1GHz (and some prerrquisite changes such as ability to scoot the
   kernel code/data from start of memory map etc)

 - Quite a few updates for EZChip (Mellanox) platform

 - Fixes to fault/exception printing

* tag 'arc-4.14-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc: (26 commits)
  ARC: Re-enable MMU upon Machine Check exception
  ARC: Show fault information passed to show_kernel_fault_diag()
  ARC: [plat-hsdk] initial port for HSDK board
  ARC: mm: Decouple RAM base address from kernel link address
  ARCv2: IOC: Tighten up the contraints (specifically base / size alignment)
  ARC: [plat-axs103] refactor the DT fudging code
  ARC: [plat-axs103] use clk driver #2: Add core pll node to DT to manage cpu clk
  ARC: [plat-axs103] use clk driver #1: Get rid of platform specific cpu clk setting
  ARCv2: SLC: provide a line based flush routine for debugging
  ARC: Hardcode ARCH_DMA_MINALIGN to max line length we may have
  ARC: [plat-eznps] handle extra aux regs #2: kernel/entry exit
  ARC: [plat-eznps] handle extra aux regs #1: save/restore on context switch
  ARC: [plat-eznps] avoid toggling of DPC register
  ARC: [plat-eznps] Update the init sequence of aux regs per cpu.
  ARC: [plat-eznps] new command line argument for HW scheduler at MTM
  ARC: set boot print log level to PR_INFO
  ARC: [plat-eznps] Handle user memory error same in simulation and silicon
  ARC: [plat-eznps] use schd.wft instruction instead of sleep at idle task
  ARC: create cpu specific version of arch_cpu_idle()
  ARC: [plat-eznps] spinlock aware for MTM
  ...
This commit is contained in:
Linus Torvalds
2017-09-08 16:02:18 -07:00
parent 0d519f2d1e 1ee55a8f7f
commit ee89252b9e
41 changed files with 739 additions and 192 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
arch/arc/include/asm/cache.h
View File

@@ -47,7 +47,8 @@
: "r"(data), "r"(ptr)); \
})
#define ARCH_DMA_MINALIGN L1_CACHE_BYTES
/* Largest line length for either L1 or L2 is 128 bytes */
#define ARCH_DMA_MINALIGN 128
extern void arc_cache_init(void);
extern char *arc_cache_mumbojumbo(int cpu_id, char *buf, int len);
@@ -95,6 +96,8 @@ extern unsigned long perip_base, perip_end;
#define ARC_REG_SLC_CTRL 0x903
#define ARC_REG_SLC_FLUSH 0x904
#define ARC_REG_SLC_INVALIDATE 0x905
#define ARC_AUX_SLC_IVDL 0x910
#define ARC_AUX_SLC_FLDL 0x912
#define ARC_REG_SLC_RGN_START 0x914
#define ARC_REG_SLC_RGN_START1 0x915
#define ARC_REG_SLC_RGN_END 0x916

24
arch/arc/include/asm/entry-compact.h
View File

@@ -192,6 +192,12 @@
PUSHAX lp_start
PUSHAX erbta
#ifdef CONFIG_ARC_PLAT_EZNPS
.word CTOP_INST_SCHD_RW
PUSHAX CTOP_AUX_GPA1
PUSHAX CTOP_AUX_EFLAGS
#endif
lr r9, [ecr]
st r9, [sp, PT_event] /* EV_Trap expects r9 to have ECR */
.endm
@@ -208,6 +214,12 @@
* by hardware and that is not good.
*-------------------------------------------------------------*/
.macro EXCEPTION_EPILOGUE
#ifdef CONFIG_ARC_PLAT_EZNPS
.word CTOP_INST_SCHD_RW
POPAX CTOP_AUX_EFLAGS
POPAX CTOP_AUX_GPA1
#endif
POPAX erbta
POPAX lp_start
POPAX lp_end
@@ -265,6 +277,12 @@
PUSHAX lp_end
PUSHAX lp_start
PUSHAX bta_l\LVL\()
#ifdef CONFIG_ARC_PLAT_EZNPS
.word CTOP_INST_SCHD_RW
PUSHAX CTOP_AUX_GPA1
PUSHAX CTOP_AUX_EFLAGS
#endif
.endm
/*--------------------------------------------------------------
@@ -277,6 +295,12 @@
* by hardware and that is not good.
*-------------------------------------------------------------*/
.macro INTERRUPT_EPILOGUE LVL
#ifdef CONFIG_ARC_PLAT_EZNPS
.word CTOP_INST_SCHD_RW
POPAX CTOP_AUX_EFLAGS
POPAX CTOP_AUX_GPA1
#endif
POPAX bta_l\LVL\()
POPAX lp_start
POPAX lp_end

3
arch/arc/include/asm/irqflags-arcv2.h
View File

@@ -47,9 +47,6 @@
#define ISA_INIT_STATUS_BITS (STATUS_IE_MASK | STATUS_AD_MASK | \
(ARCV2_IRQ_DEF_PRIO << 1))
/* SLEEP needs default irq priority (<=) which can interrupt the doze */
#define ISA_SLEEP_ARG (0x10 | ARCV2_IRQ_DEF_PRIO)
#ifndef __ASSEMBLY__
/*

2
arch/arc/include/asm/irqflags-compact.h
View File

@@ -43,8 +43,6 @@
#define ISA_INIT_STATUS_BITS STATUS_IE_MASK
#define ISA_SLEEP_ARG 0x3
#ifndef __ASSEMBLY__
/******************************************************************

2
arch/arc/include/asm/page.h
View File

@@ -85,7 +85,7 @@ typedef pte_t * pgtable_t;
*/
#define virt_to_pfn(kaddr) (__pa(kaddr) >> PAGE_SHIFT)
#define ARCH_PFN_OFFSET virt_to_pfn(CONFIG_LINUX_LINK_BASE)
#define ARCH_PFN_OFFSET virt_to_pfn(CONFIG_LINUX_RAM_BASE)
#ifdef CONFIG_FLATMEM
#define pfn_valid(pfn) (((pfn) - ARCH_PFN_OFFSET) < max_mapnr)

10
arch/arc/include/asm/processor.h
View File

@@ -27,6 +27,13 @@ struct arc_fpu {
};
#endif
#ifdef CONFIG_ARC_PLAT_EZNPS
struct eznps_dp {
unsigned int eflags;
unsigned int gpa1;
};
#endif
/* Arch specific stuff which needs to be saved per task.
* However these items are not so important so as to earn a place in
* struct thread_info
@@ -38,6 +45,9 @@ struct thread_struct {
#ifdef CONFIG_ARC_FPU_SAVE_RESTORE
struct arc_fpu fpu;
#endif
#ifdef CONFIG_ARC_PLAT_EZNPS
struct eznps_dp dp;
#endif
};
#define INIT_THREAD { \

5
arch/arc/include/asm/ptrace.h
View File

@@ -19,6 +19,11 @@
#ifdef CONFIG_ISA_ARCOMPACT
struct pt_regs {
#ifdef CONFIG_ARC_PLAT_EZNPS
unsigned long eflags; /* Extended FLAGS */
unsigned long gpa1; /* General Purpose Aux */
#endif
/* Real registers */
unsigned long bta; /* bta_l1, bta_l2, erbta */

12
arch/arc/include/asm/spinlock.h
View File

@@ -247,9 +247,15 @@ static inline void arch_spin_lock(arch_spinlock_t *lock)
__asm__ __volatile__(
"1: ex %0, [%1] \n"
#ifdef CONFIG_EZNPS_MTM_EXT
" .word %3 \n"
#endif
" breq %0, %2, 1b \n"
: "+&r" (val)
: "r"(&(lock->slock)), "ir"(__ARCH_SPIN_LOCK_LOCKED__)
#ifdef CONFIG_EZNPS_MTM_EXT
, "i"(CTOP_INST_SCHD_RW)
#endif
: "memory");
/*
@@ -291,6 +297,12 @@ static inline void arch_spin_unlock(arch_spinlock_t *lock)
*/
smp_mb();
/*
* EX is not really required here, a simple STore of 0 suffices.
* However this causes tasklist livelocks in SystemC based SMP virtual
* platforms where the systemc core scheduler uses EX as a cue for
* moving to next core. Do a git log of this file for details
*/
__asm__ __volatile__(
" ex %0, [%1] \n"
: "+r" (val)

9
arch/arc/include/asm/switch_to.h
View File

@@ -26,10 +26,19 @@ extern void fpu_save_restore(struct task_struct *p, struct task_struct *n);
#endif /* !CONFIG_ARC_FPU_SAVE_RESTORE */
#ifdef CONFIG_ARC_PLAT_EZNPS
extern void dp_save_restore(struct task_struct *p, struct task_struct *n);
#define ARC_EZNPS_DP_PREV(p, n) dp_save_restore(p, n)
#else
#define ARC_EZNPS_DP_PREV(p, n)
#endif /* !CONFIG_ARC_PLAT_EZNPS */
struct task_struct *__switch_to(struct task_struct *p, struct task_struct *n);
#define switch_to(prev, next, last) \
do { \
ARC_EZNPS_DP_PREV(prev, next); \
ARC_FPU_PREV(prev, next); \
last = __switch_to(prev, next);\
ARC_FPU_NEXT(next); \