sparc: Use asm-generic/pci-dma-compat
This converts SPARC to use asm-generic/pci-dma-compat instead of the homegrown mechnism. SPARC32 has two dma_map_ops structures for pci and sbus (removing arch/sparc/kernel/dma.c, PCI and SBUS DMA accessor). The global 'dma_ops' is set to sbus_dma_ops and get_dma_ops() returns pci32_dma_ops for pci devices so we can use the appropriate dma mapping operations. Signed-off-by: FUJITA Tomonori <fujita.tomonori@lab.ntt.co.jp> Tested-by: Robert Reif <reif@earthlink.net> Acked-by: David S. Miller <davem@davemloft.net> Cc: tony.luck@intel.com Cc: fenghua.yu@intel.com LKML-Reference: <1249872797-1314-8-git-send-email-fujita.tomonori@lab.ntt.co.jp> Signed-off-by: Ingo Molnar <mingo@elte.hu>
This commit is contained in:
FUJITA Tomonori
committed by
Ingo Molnar
Ingo Molnar
parent
c2c07dbd87
commit
ee664a9252
@@ -14,10 +14,15 @@ extern int dma_set_mask(struct device *dev, u64 dma_mask);
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#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
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#define dma_is_consistent(d, h) (1)
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extern struct dma_map_ops *dma_ops;
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extern struct dma_map_ops *dma_ops, pci32_dma_ops;
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extern struct bus_type pci_bus_type;
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static inline struct dma_map_ops *get_dma_ops(struct device *dev)
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{
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#if defined(CONFIG_SPARC32) && defined(CONFIG_PCI)
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if (dev->bus == &pci_bus_type)
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return &pci32_dma_ops;
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#endif
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return dma_ops;
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}
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@@ -5,4 +5,7 @@
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#else
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#include <asm/pci_32.h>
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#endif
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#include <asm-generic/pci-dma-compat.h>
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#endif
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@@ -31,42 +31,8 @@ static inline void pcibios_penalize_isa_irq(int irq, int active)
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*/
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#define PCI_DMA_BUS_IS_PHYS (0)
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#include <asm/scatterlist.h>
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struct pci_dev;
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/* Allocate and map kernel buffer using consistent mode DMA for a device.
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* hwdev should be valid struct pci_dev pointer for PCI devices.
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*/
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extern void *pci_alloc_consistent(struct pci_dev *hwdev, size_t size, dma_addr_t *dma_handle);
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/* Free and unmap a consistent DMA buffer.
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* cpu_addr is what was returned from pci_alloc_consistent,
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* size must be the same as what as passed into pci_alloc_consistent,
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* and likewise dma_addr must be the same as what *dma_addrp was set to.
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*
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* References to the memory and mappings assosciated with cpu_addr/dma_addr
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* past this call are illegal.
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*/
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extern void pci_free_consistent(struct pci_dev *hwdev, size_t size, void *vaddr, dma_addr_t dma_handle);
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/* Map a single buffer of the indicated size for DMA in streaming mode.
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* The 32-bit bus address to use is returned.
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*
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* Once the device is given the dma address, the device owns this memory
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* until either pci_unmap_single or pci_dma_sync_single_for_cpu is performed.
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*/
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extern dma_addr_t pci_map_single(struct pci_dev *hwdev, void *ptr, size_t size, int direction);
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/* Unmap a single streaming mode DMA translation. The dma_addr and size
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* must match what was provided for in a previous pci_map_single call. All
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* other usages are undefined.
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*
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* After this call, reads by the cpu to the buffer are guaranteed to see
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* whatever the device wrote there.
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*/
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extern void pci_unmap_single(struct pci_dev *hwdev, dma_addr_t dma_addr, size_t size, int direction);
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/* pci_unmap_{single,page} is not a nop, thus... */
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#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) \
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dma_addr_t ADDR_NAME;
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@@ -81,69 +47,6 @@ extern void pci_unmap_single(struct pci_dev *hwdev, dma_addr_t dma_addr, size_t
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#define pci_unmap_len_set(PTR, LEN_NAME, VAL) \
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(((PTR)->LEN_NAME) = (VAL))
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/*
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* Same as above, only with pages instead of mapped addresses.
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*/
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extern dma_addr_t pci_map_page(struct pci_dev *hwdev, struct page *page,
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unsigned long offset, size_t size, int direction);
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extern void pci_unmap_page(struct pci_dev *hwdev,
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dma_addr_t dma_address, size_t size, int direction);
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/* Map a set of buffers described by scatterlist in streaming
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* mode for DMA. This is the scather-gather version of the
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* above pci_map_single interface. Here the scatter gather list
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* elements are each tagged with the appropriate dma address
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* and length. They are obtained via sg_dma_{address,length}(SG).
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*
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* NOTE: An implementation may be able to use a smaller number of
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* DMA address/length pairs than there are SG table elements.
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* (for example via virtual mapping capabilities)
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* The routine returns the number of addr/length pairs actually
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* used, at most nents.
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*
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* Device ownership issues as mentioned above for pci_map_single are
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* the same here.
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*/
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extern int pci_map_sg(struct pci_dev *hwdev, struct scatterlist *sg, int nents, int direction);
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/* Unmap a set of streaming mode DMA translations.
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* Again, cpu read rules concerning calls here are the same as for
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* pci_unmap_single() above.
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*/
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extern void pci_unmap_sg(struct pci_dev *hwdev, struct scatterlist *sg, int nhwents, int direction);
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/* Make physical memory consistent for a single
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* streaming mode DMA translation after a transfer.
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*
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* If you perform a pci_map_single() but wish to interrogate the
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* buffer using the cpu, yet do not wish to teardown the PCI dma
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* mapping, you must call this function before doing so. At the
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* next point you give the PCI dma address back to the card, you
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* must first perform a pci_dma_sync_for_device, and then the device
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* again owns the buffer.
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*/
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extern void pci_dma_sync_single_for_cpu(struct pci_dev *hwdev, dma_addr_t dma_handle, size_t size, int direction);
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extern void pci_dma_sync_single_for_device(struct pci_dev *hwdev, dma_addr_t dma_handle, size_t size, int direction);
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/* Make physical memory consistent for a set of streaming
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* mode DMA translations after a transfer.
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*
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* The same as pci_dma_sync_single_* but for a scatter-gather list,
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* same rules and usage.
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*/
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extern void pci_dma_sync_sg_for_cpu(struct pci_dev *hwdev, struct scatterlist *sg, int nelems, int direction);
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extern void pci_dma_sync_sg_for_device(struct pci_dev *hwdev, struct scatterlist *sg, int nelems, int direction);
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/* Return whether the given PCI device DMA address mask can
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* be supported properly. For example, if your device can
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* only drive the low 24-bits during PCI bus mastering, then
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* you would pass 0x00ffffff as the mask to this function.
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*/
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static inline int pci_dma_supported(struct pci_dev *hwdev, u64 mask)
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{
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return 1;
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}
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#ifdef CONFIG_PCI
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static inline void pci_dma_burst_advice(struct pci_dev *pdev,
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enum pci_dma_burst_strategy *strat,
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@@ -154,14 +57,6 @@ static inline void pci_dma_burst_advice(struct pci_dev *pdev,
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}
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#endif
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#define PCI_DMA_ERROR_CODE (~(dma_addr_t)0x0)
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static inline int pci_dma_mapping_error(struct pci_dev *pdev,
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dma_addr_t dma_addr)
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{
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return (dma_addr == PCI_DMA_ERROR_CODE);
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}
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struct device_node;
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extern struct device_node *pci_device_to_OF_node(struct pci_dev *pdev);
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@@ -35,37 +35,6 @@ static inline void pcibios_penalize_isa_irq(int irq, int active)
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*/
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#define PCI_DMA_BUS_IS_PHYS (0)
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static inline void *pci_alloc_consistent(struct pci_dev *pdev, size_t size,
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dma_addr_t *dma_handle)
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{
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return dma_alloc_coherent(&pdev->dev, size, dma_handle, GFP_ATOMIC);
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}
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static inline void pci_free_consistent(struct pci_dev *pdev, size_t size,
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void *vaddr, dma_addr_t dma_handle)
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{
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return dma_free_coherent(&pdev->dev, size, vaddr, dma_handle);
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}
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static inline dma_addr_t pci_map_single(struct pci_dev *pdev, void *ptr,
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size_t size, int direction)
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{
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return dma_map_single(&pdev->dev, ptr, size,
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(enum dma_data_direction) direction);
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}
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static inline void pci_unmap_single(struct pci_dev *pdev, dma_addr_t dma_addr,
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size_t size, int direction)
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{
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dma_unmap_single(&pdev->dev, dma_addr, size,
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(enum dma_data_direction) direction);
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}
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#define pci_map_page(dev, page, off, size, dir) \
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pci_map_single(dev, (page_address(page) + (off)), size, dir)
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#define pci_unmap_page(dev,addr,sz,dir) \
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pci_unmap_single(dev,addr,sz,dir)
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/* pci_unmap_{single,page} is not a nop, thus... */
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#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) \
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dma_addr_t ADDR_NAME;
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@@ -80,57 +49,6 @@ static inline void pci_unmap_single(struct pci_dev *pdev, dma_addr_t dma_addr,
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#define pci_unmap_len_set(PTR, LEN_NAME, VAL) \
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(((PTR)->LEN_NAME) = (VAL))
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static inline int pci_map_sg(struct pci_dev *pdev, struct scatterlist *sg,
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int nents, int direction)
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{
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return dma_map_sg(&pdev->dev, sg, nents,
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(enum dma_data_direction) direction);
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}
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static inline void pci_unmap_sg(struct pci_dev *pdev, struct scatterlist *sg,
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int nents, int direction)
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{
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dma_unmap_sg(&pdev->dev, sg, nents,
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(enum dma_data_direction) direction);
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}
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static inline void pci_dma_sync_single_for_cpu(struct pci_dev *pdev,
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dma_addr_t dma_handle,
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size_t size, int direction)
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{
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dma_sync_single_for_cpu(&pdev->dev, dma_handle, size,
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(enum dma_data_direction) direction);
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}
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static inline void pci_dma_sync_single_for_device(struct pci_dev *pdev,
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dma_addr_t dma_handle,
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size_t size, int direction)
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{
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/* No flushing needed to sync cpu writes to the device. */
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}
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static inline void pci_dma_sync_sg_for_cpu(struct pci_dev *pdev,
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struct scatterlist *sg,
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int nents, int direction)
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{
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dma_sync_sg_for_cpu(&pdev->dev, sg, nents,
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(enum dma_data_direction) direction);
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}
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static inline void pci_dma_sync_sg_for_device(struct pci_dev *pdev,
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struct scatterlist *sg,
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int nelems, int direction)
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{
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/* No flushing needed to sync cpu writes to the device. */
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}
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/* Return whether the given PCI device DMA address mask can
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* be supported properly. For example, if your device can
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* only drive the low 24-bits during PCI bus mastering, then
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* you would pass 0x00ffffff as the mask to this function.
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*/
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extern int pci_dma_supported(struct pci_dev *hwdev, u64 mask);
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/* PCI IOMMU mapping bypass support. */
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/* PCI 64-bit addressing works for all slots on all controller
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@@ -140,12 +58,6 @@ extern int pci_dma_supported(struct pci_dev *hwdev, u64 mask);
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#define PCI64_REQUIRED_MASK (~(dma64_addr_t)0)
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#define PCI64_ADDR_BASE 0xfffc000000000000UL
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static inline int pci_dma_mapping_error(struct pci_dev *pdev,
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dma_addr_t dma_addr)
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{
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return dma_mapping_error(&pdev->dev, dma_addr);
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}
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#ifdef CONFIG_PCI
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static inline void pci_dma_burst_advice(struct pci_dev *pdev,
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enum pci_dma_burst_strategy *strat,
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