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ARM: OMAP2+: raw read and write endian fix

Bladeren bron 
All OMAP IP blocks expect LE data, but CPU may operate in BE mode.
Need to use endian neutral functions to read/write h/w registers.
I.e instead of __raw_read[lw] and __raw_write[lw] functions code
need to use read[lw]_relaxed and write[lw]_relaxed functions.
If the first simply reads/writes register, the second will byteswap
it if host operates in BE mode.

Changes are trivial sed like replacement of __raw_xxx functions
with xxx_relaxed variant.

Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
Signed-off-by: Taras Kondratiuk <taras.kondratiuk@linaro.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This commit is contained in:
Victor Kamensky
2014-04-15 20:37:46 +03:00
gecommit door Tony Lindgren
bovenliggende 89ca3b8819
commit edfaf05c2f
36 gewijzigde bestanden met toevoegingen van 134 en 134 verwijderingen
Download Patch-bestand Download Diff-bestand Expand all files Collapse all files

42
arch/arm/mach-omap2/omap-wakeupgen.c
Bestand weergeven

@@ -60,19 +60,19 @@ static unsigned int omap_secure_apis;
*/
static inline u32 wakeupgen_readl(u8 idx, u32 cpu)
{
return __raw_readl(wakeupgen_base + OMAP_WKG_ENB_A_0 +
return readl_relaxed(wakeupgen_base + OMAP_WKG_ENB_A_0 +
(cpu * CPU_ENA_OFFSET) + (idx * 4));
}
static inline void wakeupgen_writel(u32 val, u8 idx, u32 cpu)
{
__raw_writel(val, wakeupgen_base + OMAP_WKG_ENB_A_0 +
writel_relaxed(val, wakeupgen_base + OMAP_WKG_ENB_A_0 +
(cpu * CPU_ENA_OFFSET) + (idx * 4));
}
static inline void sar_writel(u32 val, u32 offset, u8 idx)
{
__raw_writel(val, sar_base + offset + (idx * 4));
writel_relaxed(val, sar_base + offset + (idx * 4));
}
static inline int _wakeupgen_get_irq_info(u32 irq, u32 *bit_posn, u8 *reg_index)
@@ -231,21 +231,21 @@ static inline void omap4_irq_save_context(void)
}
/* Save AuxBoot* registers */
val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
__raw_writel(val, sar_base + AUXCOREBOOT0_OFFSET);
val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_1);
__raw_writel(val, sar_base + AUXCOREBOOT1_OFFSET);
val = readl_relaxed(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
writel_relaxed(val, sar_base + AUXCOREBOOT0_OFFSET);
val = readl_relaxed(wakeupgen_base + OMAP_AUX_CORE_BOOT_1);
writel_relaxed(val, sar_base + AUXCOREBOOT1_OFFSET);
/* Save SyncReq generation logic */
val = __raw_readl(wakeupgen_base + OMAP_PTMSYNCREQ_MASK);
__raw_writel(val, sar_base + PTMSYNCREQ_MASK_OFFSET);
val = __raw_readl(wakeupgen_base + OMAP_PTMSYNCREQ_EN);
__raw_writel(val, sar_base + PTMSYNCREQ_EN_OFFSET);
val = readl_relaxed(wakeupgen_base + OMAP_PTMSYNCREQ_MASK);
writel_relaxed(val, sar_base + PTMSYNCREQ_MASK_OFFSET);
val = readl_relaxed(wakeupgen_base + OMAP_PTMSYNCREQ_EN);
writel_relaxed(val, sar_base + PTMSYNCREQ_EN_OFFSET);
/* Set the Backup Bit Mask status */
val = __raw_readl(sar_base + SAR_BACKUP_STATUS_OFFSET);
val = readl_relaxed(sar_base + SAR_BACKUP_STATUS_OFFSET);
val |= SAR_BACKUP_STATUS_WAKEUPGEN;
__raw_writel(val, sar_base + SAR_BACKUP_STATUS_OFFSET);
writel_relaxed(val, sar_base + SAR_BACKUP_STATUS_OFFSET);
}
@@ -264,15 +264,15 @@ static inline void omap5_irq_save_context(void)
}
/* Save AuxBoot* registers */
val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
__raw_writel(val, sar_base + OMAP5_AUXCOREBOOT0_OFFSET);
val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
__raw_writel(val, sar_base + OMAP5_AUXCOREBOOT1_OFFSET);
val = readl_relaxed(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
writel_relaxed(val, sar_base + OMAP5_AUXCOREBOOT0_OFFSET);
val = readl_relaxed(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
writel_relaxed(val, sar_base + OMAP5_AUXCOREBOOT1_OFFSET);
/* Set the Backup Bit Mask status */
val = __raw_readl(sar_base + OMAP5_SAR_BACKUP_STATUS_OFFSET);
val = readl_relaxed(sar_base + OMAP5_SAR_BACKUP_STATUS_OFFSET);
val |= SAR_BACKUP_STATUS_WAKEUPGEN;
__raw_writel(val, sar_base + OMAP5_SAR_BACKUP_STATUS_OFFSET);
writel_relaxed(val, sar_base + OMAP5_SAR_BACKUP_STATUS_OFFSET);
}
@@ -306,9 +306,9 @@ static void irq_sar_clear(void)
if (soc_is_omap54xx())
offset = OMAP5_SAR_BACKUP_STATUS_OFFSET;
val = __raw_readl(sar_base + offset);
val = readl_relaxed(sar_base + offset);
val &= ~SAR_BACKUP_STATUS_WAKEUPGEN;
__raw_writel(val, sar_base + offset);
writel_relaxed(val, sar_base + offset);
}
/*