drm/i915: wrap GEN6_PMIMR changes
Just like we're doing with the other IMR changes. One of the functional changes is that not every caller was doing the POSTING_READ. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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committed by
Daniel Vetter

parent
43eaea1318
commit
edbfdb4560
@@ -1062,10 +1062,8 @@ hsw_vebox_get_irq(struct intel_ring_buffer *ring)
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spin_lock_irqsave(&dev_priv->irq_lock, flags);
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if (ring->irq_refcount++ == 0) {
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u32 pm_imr = I915_READ(GEN6_PMIMR);
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I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
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I915_WRITE(GEN6_PMIMR, pm_imr & ~ring->irq_enable_mask);
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POSTING_READ(GEN6_PMIMR);
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snb_enable_pm_irq(dev_priv, ring->irq_enable_mask);
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}
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spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
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@@ -1084,10 +1082,8 @@ hsw_vebox_put_irq(struct intel_ring_buffer *ring)
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spin_lock_irqsave(&dev_priv->irq_lock, flags);
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if (--ring->irq_refcount == 0) {
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u32 pm_imr = I915_READ(GEN6_PMIMR);
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I915_WRITE_IMR(ring, ~0);
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I915_WRITE(GEN6_PMIMR, pm_imr | ring->irq_enable_mask);
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POSTING_READ(GEN6_PMIMR);
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snb_disable_pm_irq(dev_priv, ring->irq_enable_mask);
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}
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spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
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}
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