MIPS: Add support for NXP PNX833x (STB222/5) into linux kernel
The following patch add support for the NXP PNX833x SOC. More specifically it adds support for the STB222/5 variant. It fixes the vectored interrupt issue. Signed-off-by: daniel.j.laird <daniel.j.laird@nxp.com> Signed-off-by: Jason Wessel <jason.wessel@windriver.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Daniel Laird
committed by
Ralf Baechle
Ralf Baechle
parent
537fa37c86
commit
edb6310aaa
172
arch/mips/include/asm/mach-pnx833x/gpio.h
Normal file
172
arch/mips/include/asm/mach-pnx833x/gpio.h
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@@ -0,0 +1,172 @@
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/*
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* gpio.h: GPIO Support for PNX833X.
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*
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* Copyright 2008 NXP Semiconductors
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* Chris Steel <chris.steel@nxp.com>
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* Daniel Laird <daniel.j.laird@nxp.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#ifndef __ASM_MIPS_MACH_PNX833X_GPIO_H
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#define __ASM_MIPS_MACH_PNX833X_GPIO_H
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/* BIG FAT WARNING: races danger!
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No protections exist here. Current users are only early init code,
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when locking is not needed because no cuncurency yet exists there,
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and GPIO IRQ dispatcher, which does locking.
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However, if many uses will ever happen, proper locking will be needed
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- including locking between different uses
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*/
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#include "pnx833x.h"
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#define SET_REG_BIT(reg, bit) do { (reg |= (1 << (bit))); } while (0)
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#define CLEAR_REG_BIT(reg, bit) do { (reg &= ~(1 << (bit))); } while (0)
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/* Initialize GPIO to a known state */
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static inline void pnx833x_gpio_init(void)
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{
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PNX833X_PIO_DIR = 0;
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PNX833X_PIO_DIR2 = 0;
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PNX833X_PIO_SEL = 0;
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PNX833X_PIO_SEL2 = 0;
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PNX833X_PIO_INT_EDGE = 0;
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PNX833X_PIO_INT_HI = 0;
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PNX833X_PIO_INT_LO = 0;
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/* clear any GPIO interrupt requests */
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PNX833X_PIO_INT_CLEAR = 0xffff;
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PNX833X_PIO_INT_CLEAR = 0;
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PNX833X_PIO_INT_ENABLE = 0;
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}
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/* Select GPIO direction for a pin */
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static inline void pnx833x_gpio_select_input(unsigned int pin)
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{
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if (pin < 32)
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CLEAR_REG_BIT(PNX833X_PIO_DIR, pin);
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else
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CLEAR_REG_BIT(PNX833X_PIO_DIR2, pin & 31);
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}
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static inline void pnx833x_gpio_select_output(unsigned int pin)
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{
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if (pin < 32)
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SET_REG_BIT(PNX833X_PIO_DIR, pin);
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else
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SET_REG_BIT(PNX833X_PIO_DIR2, pin & 31);
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}
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/* Select GPIO or alternate function for a pin */
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static inline void pnx833x_gpio_select_function_io(unsigned int pin)
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{
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if (pin < 32)
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CLEAR_REG_BIT(PNX833X_PIO_SEL, pin);
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else
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CLEAR_REG_BIT(PNX833X_PIO_SEL2, pin & 31);
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}
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static inline void pnx833x_gpio_select_function_alt(unsigned int pin)
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{
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if (pin < 32)
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SET_REG_BIT(PNX833X_PIO_SEL, pin);
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else
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SET_REG_BIT(PNX833X_PIO_SEL2, pin & 31);
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}
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/* Read GPIO pin */
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static inline int pnx833x_gpio_read(unsigned int pin)
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{
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if (pin < 32)
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return (PNX833X_PIO_IN >> pin) & 1;
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else
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return (PNX833X_PIO_IN2 >> (pin & 31)) & 1;
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}
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/* Write GPIO pin */
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static inline void pnx833x_gpio_write(unsigned int val, unsigned int pin)
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{
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if (pin < 32) {
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if (val)
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SET_REG_BIT(PNX833X_PIO_OUT, pin);
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else
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CLEAR_REG_BIT(PNX833X_PIO_OUT, pin);
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} else {
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if (val)
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SET_REG_BIT(PNX833X_PIO_OUT2, pin & 31);
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else
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CLEAR_REG_BIT(PNX833X_PIO_OUT2, pin & 31);
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}
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}
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/* Configure GPIO interrupt */
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#define GPIO_INT_NONE 0
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#define GPIO_INT_LEVEL_LOW 1
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#define GPIO_INT_LEVEL_HIGH 2
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#define GPIO_INT_EDGE_RISING 3
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#define GPIO_INT_EDGE_FALLING 4
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#define GPIO_INT_EDGE_BOTH 5
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static inline void pnx833x_gpio_setup_irq(int when, unsigned int pin)
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{
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switch (when) {
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case GPIO_INT_LEVEL_LOW:
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CLEAR_REG_BIT(PNX833X_PIO_INT_EDGE, pin);
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CLEAR_REG_BIT(PNX833X_PIO_INT_HI, pin);
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SET_REG_BIT(PNX833X_PIO_INT_LO, pin);
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break;
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case GPIO_INT_LEVEL_HIGH:
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CLEAR_REG_BIT(PNX833X_PIO_INT_EDGE, pin);
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SET_REG_BIT(PNX833X_PIO_INT_HI, pin);
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CLEAR_REG_BIT(PNX833X_PIO_INT_LO, pin);
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break;
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case GPIO_INT_EDGE_RISING:
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SET_REG_BIT(PNX833X_PIO_INT_EDGE, pin);
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SET_REG_BIT(PNX833X_PIO_INT_HI, pin);
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CLEAR_REG_BIT(PNX833X_PIO_INT_LO, pin);
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break;
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case GPIO_INT_EDGE_FALLING:
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SET_REG_BIT(PNX833X_PIO_INT_EDGE, pin);
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CLEAR_REG_BIT(PNX833X_PIO_INT_HI, pin);
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SET_REG_BIT(PNX833X_PIO_INT_LO, pin);
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break;
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case GPIO_INT_EDGE_BOTH:
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SET_REG_BIT(PNX833X_PIO_INT_EDGE, pin);
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SET_REG_BIT(PNX833X_PIO_INT_HI, pin);
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SET_REG_BIT(PNX833X_PIO_INT_LO, pin);
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break;
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default:
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CLEAR_REG_BIT(PNX833X_PIO_INT_EDGE, pin);
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CLEAR_REG_BIT(PNX833X_PIO_INT_HI, pin);
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CLEAR_REG_BIT(PNX833X_PIO_INT_LO, pin);
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break;
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}
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}
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/* Enable/disable GPIO interrupt */
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static inline void pnx833x_gpio_enable_irq(unsigned int pin)
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{
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SET_REG_BIT(PNX833X_PIO_INT_ENABLE, pin);
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}
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static inline void pnx833x_gpio_disable_irq(unsigned int pin)
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{
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CLEAR_REG_BIT(PNX833X_PIO_INT_ENABLE, pin);
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}
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/* Clear GPIO interrupt request */
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static inline void pnx833x_gpio_clear_irq(unsigned int pin)
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{
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SET_REG_BIT(PNX833X_PIO_INT_CLEAR, pin);
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CLEAR_REG_BIT(PNX833X_PIO_INT_CLEAR, pin);
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}
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#endif
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126
arch/mips/include/asm/mach-pnx833x/irq-mapping.h
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126
arch/mips/include/asm/mach-pnx833x/irq-mapping.h
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@@ -0,0 +1,126 @@
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/*
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* irq.h: IRQ mappings for PNX833X.
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*
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* Copyright 2008 NXP Semiconductors
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* Chris Steel <chris.steel@nxp.com>
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* Daniel Laird <daniel.j.laird@nxp.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#ifndef __ASM_MIPS_MACH_PNX833X_IRQ_MAPPING_H
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#define __ASM_MIPS_MACH_PNX833X_IRQ_MAPPING_H
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/*
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* The "IRQ numbers" are completely virtual.
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*
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* In PNX8330/1, we have 48 interrupt lines, numbered from 1 to 48.
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* Let's use numbers 1..48 for PIC interrupts, number 0 for timer interrupt,
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* numbers 49..64 for (virtual) GPIO interrupts.
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*
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* In PNX8335, we have 57 interrupt lines, numbered from 1 to 57,
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* connected to PIC, which uses core hardware interrupt 2, and also
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* a timer interrupt through hardware interrupt 5.
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* Let's use numbers 1..64 for PIC interrupts, number 0 for timer interrupt,
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* numbers 65..80 for (virtual) GPIO interrupts.
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*
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*/
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#include <irq.h>
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#define PNX833X_TIMER_IRQ (MIPS_CPU_IRQ_BASE + 7)
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/* Interrupts supported by PIC */
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#define PNX833X_PIC_I2C0_INT (PNX833X_PIC_IRQ_BASE + 1)
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#define PNX833X_PIC_I2C1_INT (PNX833X_PIC_IRQ_BASE + 2)
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#define PNX833X_PIC_UART0_INT (PNX833X_PIC_IRQ_BASE + 3)
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#define PNX833X_PIC_UART1_INT (PNX833X_PIC_IRQ_BASE + 4)
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#define PNX833X_PIC_TS_IN0_DV_INT (PNX833X_PIC_IRQ_BASE + 5)
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#define PNX833X_PIC_TS_IN0_DMA_INT (PNX833X_PIC_IRQ_BASE + 6)
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#define PNX833X_PIC_GPIO_INT (PNX833X_PIC_IRQ_BASE + 7)
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#define PNX833X_PIC_AUDIO_DEC_INT (PNX833X_PIC_IRQ_BASE + 8)
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#define PNX833X_PIC_VIDEO_DEC_INT (PNX833X_PIC_IRQ_BASE + 9)
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#define PNX833X_PIC_CONFIG_INT (PNX833X_PIC_IRQ_BASE + 10)
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#define PNX833X_PIC_AOI_INT (PNX833X_PIC_IRQ_BASE + 11)
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#define PNX833X_PIC_SYNC_INT (PNX833X_PIC_IRQ_BASE + 12)
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#define PNX8330_PIC_SPU_INT (PNX833X_PIC_IRQ_BASE + 13)
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#define PNX8335_PIC_SATA_INT (PNX833X_PIC_IRQ_BASE + 13)
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#define PNX833X_PIC_OSD_INT (PNX833X_PIC_IRQ_BASE + 14)
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#define PNX833X_PIC_DISP1_INT (PNX833X_PIC_IRQ_BASE + 15)
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#define PNX833X_PIC_DEINTERLACER_INT (PNX833X_PIC_IRQ_BASE + 16)
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#define PNX833X_PIC_DISPLAY2_INT (PNX833X_PIC_IRQ_BASE + 17)
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#define PNX833X_PIC_VC_INT (PNX833X_PIC_IRQ_BASE + 18)
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#define PNX833X_PIC_SC_INT (PNX833X_PIC_IRQ_BASE + 19)
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#define PNX833X_PIC_IDE_INT (PNX833X_PIC_IRQ_BASE + 20)
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#define PNX833X_PIC_IDE_DMA_INT (PNX833X_PIC_IRQ_BASE + 21)
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#define PNX833X_PIC_TS_IN1_DV_INT (PNX833X_PIC_IRQ_BASE + 22)
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#define PNX833X_PIC_TS_IN1_DMA_INT (PNX833X_PIC_IRQ_BASE + 23)
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#define PNX833X_PIC_SGDX_DMA_INT (PNX833X_PIC_IRQ_BASE + 24)
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#define PNX833X_PIC_TS_OUT_INT (PNX833X_PIC_IRQ_BASE + 25)
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#define PNX833X_PIC_IR_INT (PNX833X_PIC_IRQ_BASE + 26)
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#define PNX833X_PIC_VMSP1_INT (PNX833X_PIC_IRQ_BASE + 27)
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#define PNX833X_PIC_VMSP2_INT (PNX833X_PIC_IRQ_BASE + 28)
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#define PNX833X_PIC_PIBC_INT (PNX833X_PIC_IRQ_BASE + 29)
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#define PNX833X_PIC_TS_IN0_TRD_INT (PNX833X_PIC_IRQ_BASE + 30)
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#define PNX833X_PIC_SGDX_TPD_INT (PNX833X_PIC_IRQ_BASE + 31)
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#define PNX833X_PIC_USB_INT (PNX833X_PIC_IRQ_BASE + 32)
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#define PNX833X_PIC_TS_IN1_TRD_INT (PNX833X_PIC_IRQ_BASE + 33)
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#define PNX833X_PIC_CLOCK_INT (PNX833X_PIC_IRQ_BASE + 34)
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#define PNX833X_PIC_SGDX_PARSER_INT (PNX833X_PIC_IRQ_BASE + 35)
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#define PNX833X_PIC_VMSP_DMA_INT (PNX833X_PIC_IRQ_BASE + 36)
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#if defined(CONFIG_SOC_PNX8335)
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#define PNX8335_PIC_MIU_INT (PNX833X_PIC_IRQ_BASE + 37)
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#define PNX8335_PIC_AVCHIP_IRQ_INT (PNX833X_PIC_IRQ_BASE + 38)
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#define PNX8335_PIC_SYNC_HD_INT (PNX833X_PIC_IRQ_BASE + 39)
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#define PNX8335_PIC_DISP_HD_INT (PNX833X_PIC_IRQ_BASE + 40)
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#define PNX8335_PIC_DISP_SCALER_INT (PNX833X_PIC_IRQ_BASE + 41)
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#define PNX8335_PIC_OSD_HD1_INT (PNX833X_PIC_IRQ_BASE + 42)
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#define PNX8335_PIC_DTL_WRITER_Y_INT (PNX833X_PIC_IRQ_BASE + 43)
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#define PNX8335_PIC_DTL_WRITER_C_INT (PNX833X_PIC_IRQ_BASE + 44)
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#define PNX8335_PIC_DTL_EMULATOR_Y_IR_INT (PNX833X_PIC_IRQ_BASE + 45)
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#define PNX8335_PIC_DTL_EMULATOR_C_IR_INT (PNX833X_PIC_IRQ_BASE + 46)
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#define PNX8335_PIC_DENC_TTX_INT (PNX833X_PIC_IRQ_BASE + 47)
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#define PNX8335_PIC_MMI_SIF0_INT (PNX833X_PIC_IRQ_BASE + 48)
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#define PNX8335_PIC_MMI_SIF1_INT (PNX833X_PIC_IRQ_BASE + 49)
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#define PNX8335_PIC_MMI_CDMMU_INT (PNX833X_PIC_IRQ_BASE + 50)
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#define PNX8335_PIC_PIBCS_INT (PNX833X_PIC_IRQ_BASE + 51)
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#define PNX8335_PIC_ETHERNET_INT (PNX833X_PIC_IRQ_BASE + 52)
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#define PNX8335_PIC_VMSP1_0_INT (PNX833X_PIC_IRQ_BASE + 53)
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#define PNX8335_PIC_VMSP1_1_INT (PNX833X_PIC_IRQ_BASE + 54)
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#define PNX8335_PIC_VMSP1_DMA_INT (PNX833X_PIC_IRQ_BASE + 55)
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#define PNX8335_PIC_TDGR_DE_INT (PNX833X_PIC_IRQ_BASE + 56)
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#define PNX8335_PIC_IR1_IRQ_INT (PNX833X_PIC_IRQ_BASE + 57)
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#endif
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/* GPIO interrupts */
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#define PNX833X_GPIO_0_INT (PNX833X_GPIO_IRQ_BASE + 0)
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#define PNX833X_GPIO_1_INT (PNX833X_GPIO_IRQ_BASE + 1)
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#define PNX833X_GPIO_2_INT (PNX833X_GPIO_IRQ_BASE + 2)
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#define PNX833X_GPIO_3_INT (PNX833X_GPIO_IRQ_BASE + 3)
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#define PNX833X_GPIO_4_INT (PNX833X_GPIO_IRQ_BASE + 4)
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#define PNX833X_GPIO_5_INT (PNX833X_GPIO_IRQ_BASE + 5)
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#define PNX833X_GPIO_6_INT (PNX833X_GPIO_IRQ_BASE + 6)
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#define PNX833X_GPIO_7_INT (PNX833X_GPIO_IRQ_BASE + 7)
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#define PNX833X_GPIO_8_INT (PNX833X_GPIO_IRQ_BASE + 8)
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#define PNX833X_GPIO_9_INT (PNX833X_GPIO_IRQ_BASE + 9)
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#define PNX833X_GPIO_10_INT (PNX833X_GPIO_IRQ_BASE + 10)
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#define PNX833X_GPIO_11_INT (PNX833X_GPIO_IRQ_BASE + 11)
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#define PNX833X_GPIO_12_INT (PNX833X_GPIO_IRQ_BASE + 12)
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#define PNX833X_GPIO_13_INT (PNX833X_GPIO_IRQ_BASE + 13)
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#define PNX833X_GPIO_14_INT (PNX833X_GPIO_IRQ_BASE + 14)
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#define PNX833X_GPIO_15_INT (PNX833X_GPIO_IRQ_BASE + 15)
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#endif
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53
arch/mips/include/asm/mach-pnx833x/irq.h
Normal file
53
arch/mips/include/asm/mach-pnx833x/irq.h
Normal file
@@ -0,0 +1,53 @@
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/*
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* irq.h: IRQ mappings for PNX833X.
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*
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* Copyright 2008 NXP Semiconductors
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* Chris Steel <chris.steel@nxp.com>
|
||||
* Daniel Laird <daniel.j.laird@nxp.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*/
|
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#ifndef __ASM_MIPS_MACH_PNX833X_IRQ_H
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#define __ASM_MIPS_MACH_PNX833X_IRQ_H
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/*
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* The "IRQ numbers" are completely virtual.
|
||||
*
|
||||
* In PNX8330/1, we have 48 interrupt lines, numbered from 1 to 48.
|
||||
* Let's use numbers 1..48 for PIC interrupts, number 0 for timer interrupt,
|
||||
* numbers 49..64 for (virtual) GPIO interrupts.
|
||||
*
|
||||
* In PNX8335, we have 57 interrupt lines, numbered from 1 to 57,
|
||||
* connected to PIC, which uses core hardware interrupt 2, and also
|
||||
* a timer interrupt through hardware interrupt 5.
|
||||
* Let's use numbers 1..64 for PIC interrupts, number 0 for timer interrupt,
|
||||
* numbers 65..80 for (virtual) GPIO interrupts.
|
||||
*
|
||||
*/
|
||||
#if defined(CONFIG_SOC_PNX8335)
|
||||
#define PNX833X_PIC_NUM_IRQ 58
|
||||
#else
|
||||
#define PNX833X_PIC_NUM_IRQ 37
|
||||
#endif
|
||||
|
||||
#define MIPS_CPU_NUM_IRQ 8
|
||||
#define PNX833X_GPIO_NUM_IRQ 16
|
||||
|
||||
#define MIPS_CPU_IRQ_BASE 0
|
||||
#define PNX833X_PIC_IRQ_BASE (MIPS_CPU_IRQ_BASE + MIPS_CPU_NUM_IRQ)
|
||||
#define PNX833X_GPIO_IRQ_BASE (PNX833X_PIC_IRQ_BASE + PNX833X_PIC_NUM_IRQ)
|
||||
#define NR_IRQS (MIPS_CPU_NUM_IRQ + PNX833X_PIC_NUM_IRQ + PNX833X_GPIO_NUM_IRQ)
|
||||
|
||||
#endif
|
||||
202
arch/mips/include/asm/mach-pnx833x/pnx833x.h
Normal file
202
arch/mips/include/asm/mach-pnx833x/pnx833x.h
Normal file
@@ -0,0 +1,202 @@
|
||||
/*
|
||||
* pnx833x.h: Register mappings for PNX833X.
|
||||
*
|
||||
* Copyright 2008 NXP Semiconductors
|
||||
* Chris Steel <chris.steel@nxp.com>
|
||||
* Daniel Laird <daniel.j.laird@nxp.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*/
|
||||
#ifndef __ASM_MIPS_MACH_PNX833X_PNX833X_H
|
||||
#define __ASM_MIPS_MACH_PNX833X_PNX833X_H
|
||||
|
||||
/* All regs are accessed in KSEG1 */
|
||||
#define PNX833X_BASE (0xa0000000ul + 0x17E00000ul)
|
||||
|
||||
#define PNX833X_REG(offs) (*((volatile unsigned long *)(PNX833X_BASE + offs)))
|
||||
|
||||
/* Registers are named exactly as in PNX833X docs, just with PNX833X_ prefix */
|
||||
|
||||
/* Read access to multibit fields */
|
||||
#define PNX833X_BIT(val, reg, field) ((val) & PNX833X_##reg##_##field)
|
||||
#define PNX833X_REGBIT(reg, field) PNX833X_BIT(PNX833X_##reg, reg, field)
|
||||
|
||||
/* Use PNX833X_FIELD to extract a field from val */
|
||||
#define PNX_FIELD(cpu, val, reg, field) \
|
||||
(((val) & PNX##cpu##_##reg##_##field##_MASK) >> \
|
||||
PNX##cpu##_##reg##_##field##_SHIFT)
|
||||
#define PNX833X_FIELD(val, reg, field) PNX_FIELD(833X, val, reg, field)
|
||||
#define PNX8330_FIELD(val, reg, field) PNX_FIELD(8330, val, reg, field)
|
||||
#define PNX8335_FIELD(val, reg, field) PNX_FIELD(8335, val, reg, field)
|
||||
|
||||
/* Use PNX833X_REGFIELD to extract a field from a register */
|
||||
#define PNX833X_REGFIELD(reg, field) PNX833X_FIELD(PNX833X_##reg, reg, field)
|
||||
#define PNX8330_REGFIELD(reg, field) PNX8330_FIELD(PNX8330_##reg, reg, field)
|
||||
#define PNX8335_REGFIELD(reg, field) PNX8335_FIELD(PNX8335_##reg, reg, field)
|
||||
|
||||
|
||||
#define PNX_WRITEFIELD(cpu, val, reg, field) \
|
||||
(PNX##cpu##_##reg = (PNX##cpu##_##reg & ~(PNX##cpu##_##reg##_##field##_MASK)) | \
|
||||
((val) << PNX##cpu##_##reg##_##field##_SHIFT))
|
||||
#define PNX833X_WRITEFIELD(val, reg, field) \
|
||||
PNX_WRITEFIELD(833X, val, reg, field)
|
||||
#define PNX8330_WRITEFIELD(val, reg, field) \
|
||||
PNX_WRITEFIELD(8330, val, reg, field)
|
||||
#define PNX8335_WRITEFIELD(val, reg, field) \
|
||||
PNX_WRITEFIELD(8335, val, reg, field)
|
||||
|
||||
|
||||
/* Macros to detect CPU type */
|
||||
|
||||
#define PNX833X_CONFIG_MODULE_ID PNX833X_REG(0x7FFC)
|
||||
#define PNX833X_CONFIG_MODULE_ID_MAJREV_MASK 0x0000f000
|
||||
#define PNX833X_CONFIG_MODULE_ID_MAJREV_SHIFT 12
|
||||
#define PNX8330_CONFIG_MODULE_MAJREV 4
|
||||
#define PNX8335_CONFIG_MODULE_MAJREV 5
|
||||
#define CPU_IS_PNX8330 (PNX833X_REGFIELD(CONFIG_MODULE_ID, MAJREV) == \
|
||||
PNX8330_CONFIG_MODULE_MAJREV)
|
||||
#define CPU_IS_PNX8335 (PNX833X_REGFIELD(CONFIG_MODULE_ID, MAJREV) == \
|
||||
PNX8335_CONFIG_MODULE_MAJREV)
|
||||
|
||||
|
||||
|
||||
#define PNX833X_RESET_CONTROL PNX833X_REG(0x8004)
|
||||
#define PNX833X_RESET_CONTROL_2 PNX833X_REG(0x8014)
|
||||
|
||||
#define PNX833X_PIC_REG(offs) PNX833X_REG(0x01000 + (offs))
|
||||
#define PNX833X_PIC_INT_PRIORITY PNX833X_PIC_REG(0x0)
|
||||
#define PNX833X_PIC_INT_SRC PNX833X_PIC_REG(0x4)
|
||||
#define PNX833X_PIC_INT_SRC_INT_SRC_MASK 0x00000FF8ul /* bits 11:3 */
|
||||
#define PNX833X_PIC_INT_SRC_INT_SRC_SHIFT 3
|
||||
#define PNX833X_PIC_INT_REG(irq) PNX833X_PIC_REG(0x10 + 4*(irq))
|
||||
|
||||
#define PNX833X_CLOCK_CPUCP_CTL PNX833X_REG(0x9228)
|
||||
#define PNX833X_CLOCK_CPUCP_CTL_EXIT_RESET 0x00000002ul /* bit 1 */
|
||||
#define PNX833X_CLOCK_CPUCP_CTL_DIV_CLOCK_MASK 0x00000018ul /* bits 4:3 */
|
||||
#define PNX833X_CLOCK_CPUCP_CTL_DIV_CLOCK_SHIFT 3
|
||||
|
||||
#define PNX8335_CLOCK_PLL_CPU_CTL PNX833X_REG(0x9020)
|
||||
#define PNX8335_CLOCK_PLL_CPU_CTL_FREQ_MASK 0x1f
|
||||
#define PNX8335_CLOCK_PLL_CPU_CTL_FREQ_SHIFT 0
|
||||
|
||||
#define PNX833X_CONFIG_MUX PNX833X_REG(0x7004)
|
||||
#define PNX833X_CONFIG_MUX_IDE_MUX 0x00000080 /* bit 7 */
|
||||
|
||||
#define PNX8330_CONFIG_POLYFUSE_7 PNX833X_REG(0x7040)
|
||||
#define PNX8330_CONFIG_POLYFUSE_7_BOOT_MODE_MASK 0x00180000
|
||||
#define PNX8330_CONFIG_POLYFUSE_7_BOOT_MODE_SHIFT 19
|
||||
|
||||
#define PNX833X_PIO_IN PNX833X_REG(0xF000)
|
||||
#define PNX833X_PIO_OUT PNX833X_REG(0xF004)
|
||||
#define PNX833X_PIO_DIR PNX833X_REG(0xF008)
|
||||
#define PNX833X_PIO_SEL PNX833X_REG(0xF014)
|
||||
#define PNX833X_PIO_INT_EDGE PNX833X_REG(0xF020)
|
||||
#define PNX833X_PIO_INT_HI PNX833X_REG(0xF024)
|
||||
#define PNX833X_PIO_INT_LO PNX833X_REG(0xF028)
|
||||
#define PNX833X_PIO_INT_STATUS PNX833X_REG(0xFFE0)
|
||||
#define PNX833X_PIO_INT_ENABLE PNX833X_REG(0xFFE4)
|
||||
#define PNX833X_PIO_INT_CLEAR PNX833X_REG(0xFFE8)
|
||||
#define PNX833X_PIO_IN2 PNX833X_REG(0xF05C)
|
||||
#define PNX833X_PIO_OUT2 PNX833X_REG(0xF060)
|
||||
#define PNX833X_PIO_DIR2 PNX833X_REG(0xF064)
|
||||
#define PNX833X_PIO_SEL2 PNX833X_REG(0xF068)
|
||||
|
||||
#define PNX833X_UART0_PORTS_START (PNX833X_BASE + 0xB000)
|
||||
#define PNX833X_UART0_PORTS_END (PNX833X_BASE + 0xBFFF)
|
||||
#define PNX833X_UART1_PORTS_START (PNX833X_BASE + 0xC000)
|
||||
#define PNX833X_UART1_PORTS_END (PNX833X_BASE + 0xCFFF)
|
||||
|
||||
#define PNX833X_USB_PORTS_START (PNX833X_BASE + 0x19000)
|
||||
#define PNX833X_USB_PORTS_END (PNX833X_BASE + 0x19FFF)
|
||||
|
||||
#define PNX833X_CONFIG_USB PNX833X_REG(0x7008)
|
||||
|
||||
#define PNX833X_I2C0_PORTS_START (PNX833X_BASE + 0xD000)
|
||||
#define PNX833X_I2C0_PORTS_END (PNX833X_BASE + 0xDFFF)
|
||||
#define PNX833X_I2C1_PORTS_START (PNX833X_BASE + 0xE000)
|
||||
#define PNX833X_I2C1_PORTS_END (PNX833X_BASE + 0xEFFF)
|
||||
|
||||
#define PNX833X_IDE_PORTS_START (PNX833X_BASE + 0x1A000)
|
||||
#define PNX833X_IDE_PORTS_END (PNX833X_BASE + 0x1AFFF)
|
||||
#define PNX833X_IDE_MODULE_ID PNX833X_REG(0x1AFFC)
|
||||
|
||||
#define PNX833X_IDE_MODULE_ID_MODULE_ID_MASK 0xFFFF0000
|
||||
#define PNX833X_IDE_MODULE_ID_MODULE_ID_SHIFT 16
|
||||
#define PNX833X_IDE_MODULE_ID_VALUE 0xA009
|
||||
|
||||
|
||||
#define PNX833X_MIU_SEL0 PNX833X_REG(0x2004)
|
||||
#define PNX833X_MIU_SEL0_TIMING PNX833X_REG(0x2008)
|
||||
#define PNX833X_MIU_SEL1 PNX833X_REG(0x200C)
|
||||
#define PNX833X_MIU_SEL1_TIMING PNX833X_REG(0x2010)
|
||||
#define PNX833X_MIU_SEL2 PNX833X_REG(0x2014)
|
||||
#define PNX833X_MIU_SEL2_TIMING PNX833X_REG(0x2018)
|
||||
#define PNX833X_MIU_SEL3 PNX833X_REG(0x201C)
|
||||
#define PNX833X_MIU_SEL3_TIMING PNX833X_REG(0x2020)
|
||||
|
||||
#define PNX833X_MIU_SEL0_SPI_MODE_ENABLE_MASK (1 << 14)
|
||||
#define PNX833X_MIU_SEL0_SPI_MODE_ENABLE_SHIFT 14
|
||||
|
||||
#define PNX833X_MIU_SEL0_BURST_MODE_ENABLE_MASK (1 << 7)
|
||||
#define PNX833X_MIU_SEL0_BURST_MODE_ENABLE_SHIFT 7
|
||||
|
||||
#define PNX833X_MIU_SEL0_BURST_PAGE_LEN_MASK (0xF << 9)
|
||||
#define PNX833X_MIU_SEL0_BURST_PAGE_LEN_SHIFT 9
|
||||
|
||||
#define PNX833X_MIU_CONFIG_SPI PNX833X_REG(0x2000)
|
||||
|
||||
#define PNX833X_MIU_CONFIG_SPI_OPCODE_MASK (0xFF << 3)
|
||||
#define PNX833X_MIU_CONFIG_SPI_OPCODE_SHIFT 3
|
||||
|
||||
#define PNX833X_MIU_CONFIG_SPI_DATA_ENABLE_MASK (1 << 2)
|
||||
#define PNX833X_MIU_CONFIG_SPI_DATA_ENABLE_SHIFT 2
|
||||
|
||||
#define PNX833X_MIU_CONFIG_SPI_ADDR_ENABLE_MASK (1 << 1)
|
||||
#define PNX833X_MIU_CONFIG_SPI_ADDR_ENABLE_SHIFT 1
|
||||
|
||||
#define PNX833X_MIU_CONFIG_SPI_SYNC_MASK (1 << 0)
|
||||
#define PNX833X_MIU_CONFIG_SPI_SYNC_SHIFT 0
|
||||
|
||||
#define PNX833X_WRITE_CONFIG_SPI(opcode, data_enable, addr_enable, sync) \
|
||||
(PNX833X_MIU_CONFIG_SPI = \
|
||||
((opcode) << PNX833X_MIU_CONFIG_SPI_OPCODE_SHIFT) | \
|
||||
((data_enable) << PNX833X_MIU_CONFIG_SPI_DATA_ENABLE_SHIFT) | \
|
||||
((addr_enable) << PNX833X_MIU_CONFIG_SPI_ADDR_ENABLE_SHIFT) | \
|
||||
((sync) << PNX833X_MIU_CONFIG_SPI_SYNC_SHIFT))
|
||||
|
||||
#define PNX8335_IP3902_PORTS_START (PNX833X_BASE + 0x2F000)
|
||||
#define PNX8335_IP3902_PORTS_END (PNX833X_BASE + 0x2FFFF)
|
||||
#define PNX8335_IP3902_MODULE_ID PNX833X_REG(0x2FFFC)
|
||||
|
||||
#define PNX8335_IP3902_MODULE_ID_MODULE_ID_MASK 0xFFFF0000
|
||||
#define PNX8335_IP3902_MODULE_ID_MODULE_ID_SHIFT 16
|
||||
#define PNX8335_IP3902_MODULE_ID_VALUE 0x3902
|
||||
|
||||
/* I/O location(gets remapped)*/
|
||||
#define PNX8335_NAND_BASE 0x18000000
|
||||
/* I/O location with CLE high */
|
||||
#define PNX8335_NAND_CLE_MASK 0x00100000
|
||||
/* I/O location with ALE high */
|
||||
#define PNX8335_NAND_ALE_MASK 0x00010000
|
||||
|
||||
#define PNX8335_SATA_PORTS_START (PNX833X_BASE + 0x2E000)
|
||||
#define PNX8335_SATA_PORTS_END (PNX833X_BASE + 0x2EFFF)
|
||||
#define PNX8335_SATA_MODULE_ID PNX833X_REG(0x2EFFC)
|
||||
|
||||
#define PNX8335_SATA_MODULE_ID_MODULE_ID_MASK 0xFFFF0000
|
||||
#define PNX8335_SATA_MODULE_ID_MODULE_ID_SHIFT 16
|
||||
#define PNX8335_SATA_MODULE_ID_VALUE 0xA099
|
||||
|
||||
#endif
|
||||
25
arch/mips/include/asm/mach-pnx833x/war.h
Normal file
25
arch/mips/include/asm/mach-pnx833x/war.h
Normal file
@@ -0,0 +1,25 @@
|
||||
/*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
|
||||
*/
|
||||
#ifndef __ASM_MIPS_MACH_PNX833X_WAR_H
|
||||
#define __ASM_MIPS_MACH_PNX833X_WAR_H
|
||||
|
||||
#define R4600_V1_INDEX_ICACHEOP_WAR 0
|
||||
#define R4600_V1_HIT_CACHEOP_WAR 0
|
||||
#define R4600_V2_HIT_CACHEOP_WAR 0
|
||||
#define R5432_CP0_INTERRUPT_WAR 0
|
||||
#define BCM1250_M3_WAR 0
|
||||
#define SIBYTE_1956_WAR 0
|
||||
#define MIPS4K_ICACHE_REFILL_WAR 0
|
||||
#define MIPS_CACHE_SYNC_WAR 0
|
||||
#define TX49XX_ICACHE_INDEX_INV_WAR 0
|
||||
#define RM9000_CDEX_SMP_WAR 0
|
||||
#define ICACHE_REFILLS_WORKAROUND_WAR 0
|
||||
#define R10000_LLSC_WAR 0
|
||||
#define MIPS34K_MISSED_ITLB_WAR 0
|
||||
|
||||
#endif /* __ASM_MIPS_MACH_PNX8550_WAR_H */
|
||||
Reference in New Issue
Block a user