MIPS: HTW: Prevent accidental HTW start due to nested htw_{start, stop}
activate_mm() and switch_mm() call get_new_mmu_context() which in turn can enable the HTW before the entryhi is changed with the new ASID. Since the latter will enable the HTW in local_flush_tlb_all(), then there is a small timing window where the HTW is running with the new ASID but with an old pgd since the TLBMISS_HANDLER_SETUP_PGD hasn't assigned a new one yet. In order to prevent that, we introduce a simple htw counter to avoid starting HTW accidentally due to nested htw_{start,stop}() sequences. Moreover, since various IPI calls can enforce TLB flushing operations on a different core, such an operation may interrupt another htw_{stop,start} in progress leading inconsistent updates of the htw_seq variable. In order to avoid that, we disable the interrupts whenever we update that variable. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: <stable@vger.kernel.org> # 3.17+ Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9118/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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committed by
Ralf Baechle

parent
fde3538a8a
commit
ed4cbc81ad
@@ -99,19 +99,31 @@ extern void paging_init(void);
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#define htw_stop() \
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do { \
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unsigned long flags; \
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\
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if (cpu_has_htw) { \
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write_c0_pwctl(read_c0_pwctl() & \
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~(1 << MIPS_PWCTL_PWEN_SHIFT)); \
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back_to_back_c0_hazard(); \
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local_irq_save(flags); \
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if(!raw_current_cpu_data.htw_seq++) { \
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write_c0_pwctl(read_c0_pwctl() & \
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~(1 << MIPS_PWCTL_PWEN_SHIFT)); \
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back_to_back_c0_hazard(); \
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} \
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local_irq_restore(flags); \
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} \
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} while(0)
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#define htw_start() \
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do { \
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unsigned long flags; \
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\
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if (cpu_has_htw) { \
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write_c0_pwctl(read_c0_pwctl() | \
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(1 << MIPS_PWCTL_PWEN_SHIFT)); \
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back_to_back_c0_hazard(); \
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local_irq_save(flags); \
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if (!--raw_current_cpu_data.htw_seq) { \
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write_c0_pwctl(read_c0_pwctl() | \
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(1 << MIPS_PWCTL_PWEN_SHIFT)); \
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back_to_back_c0_hazard(); \
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} \
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local_irq_restore(flags); \
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} \
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} while(0)
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