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Merge tag 'clk-for-linus-4.5' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Browse Source 
Pull clk framework updates from Michael Turquette:
 "The clk framework and driver changes for 4.5 look pretty typical.  The
  bulk of the changes are to clk controller drivers, though some
  improvements to the core and some re-usable blocks/templates also
  received some love.

  In this past cycle the clk maintainers developed a good workflow for
  handling the common case of patch submissions containing a new
  drivers, new shared Device Tree header and a new Device Tree binding
  description.  This requires coordination with the Device Tree
  maintainers and with the architecture maintainers (typically the
  arm-soc tree in our case).

  This explains the increase in changes to include/dt-bindings/... and
  to Documentation/devicetree/bindings/clock/... coming from the clk
  tree.  The same commits can be expected to come through those trees on
  occasion, through the use of shared, immutable branches"

* tag 'clk-for-linus-4.5' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (125 commits)
  clk: remove duplicated COMMON_CLK_NXP record from clk/Kconfig
  clk: fix clk-gpio.c with optional clock= DT property
  clk: rockchip: fix section mismatches with new child-clocks
  clk: gpio: handle error codes for of_clk_get_parent_count()
  clk: gpio: fix memory leak
  clk: shmobile: r8a7795: Add SATA0 clock
  clk: bcm2835: Add PWM clock support
  clk: bcm2835: Support for clock parent selection
  clk: bcm2835: add a round up ability to the clock divisor
  clk: lpc32xx: add common clock framework driver
  clk: lpc18xx: add NXP specific COMMON_CLK_NXP configuration symbol
  dt-bindings: clock: add NXP LPC32xx clock list for consumers
  dt-bindings: clock: add description of LPC32xx USB clock controller
  dt-bindings: clock: add description of LPC32xx clock controller
  clk: rockchip: rk3036: include downstream muxes into fractional dividers
  clk: add flag for clocks that need to be enabled on rate changes
  clk: rockchip: Allow the RK3288 SPDIF clocks to change their parent
  clk: rockchip: include downstream muxes into fractional dividers
  clk: rockchip: handle mux dependency of fractional dividers
  clk: bcm2835: Add a driver for the auxiliary peripheral clock gates.
  ...
This commit is contained in:
Linus Torvalds
2016-01-15 18:21:28 -08:00
parent d45187aaf0 3da834e3e5
commit ece6267878
119 changed files with 20639 additions and 1353 deletions
Download Patch File Download Diff File Expand all files Collapse all files

17
include/dt-bindings/clock/bcm2835-aux.h Normal file
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@@ -0,0 +1,17 @@
/*
* Copyright (C) 2015 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#define BCM2835_AUX_CLOCK_UART 0
#define BCM2835_AUX_CLOCK_SPI1 1
#define BCM2835_AUX_CLOCK_SPI2 2
#define BCM2835_AUX_CLOCK_COUNT 3

3
include/dt-bindings/clock/bcm2835.h
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@@ -43,5 +43,6 @@
#define BCM2835_CLOCK_TSENS 27
#define BCM2835_CLOCK_EMMC 28
#define BCM2835_CLOCK_PERI_IMAGE 29
#define BCM2835_CLOCK_PWM 30
#define BCM2835_CLOCK_COUNT 30
#define BCM2835_CLOCK_COUNT 31

4
include/dt-bindings/clock/exynos5420.h
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@@ -25,6 +25,8 @@
#define CLK_FOUT_MPLL 10
#define CLK_FOUT_BPLL 11
#define CLK_FOUT_KPLL 12
#define CLK_ARM_CLK 13
#define CLK_KFC_CLK 14
/* gate for special clocks (sclk) */
#define CLK_SCLK_UART0 128
@@ -210,6 +212,8 @@
#define CLK_MOUT_SW_ACLK300 649
#define CLK_MOUT_USER_ACLK400_DISP1 650
#define CLK_MOUT_SW_ACLK400 651
#define CLK_MOUT_USER_ACLK300_GSCL 652
#define CLK_MOUT_SW_ACLK300_GSCL 653
/* divider clocks */
#define CLK_DOUT_PIXEL 768

3
include/dt-bindings/clock/imx7d-clock.h
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@@ -447,5 +447,6 @@
#define IMX7D_SEMA4_HS_ROOT_CLK 434
#define IMX7D_PLL_DRAM_TEST_DIV 435
#define IMX7D_ADC_ROOT_CLK 436
#define IMX7D_CLK_END 437
#define IMX7D_CLK_ARM 437
#define IMX7D_CLK_END 438
#endif /* __DT_BINDINGS_CLOCK_IMX7D_H */

56
include/dt-bindings/clock/lpc32xx-clock.h Normal file
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@@ -0,0 +1,56 @@
/*
* Copyright (c) 2015 Vladimir Zapolskiy <vz@mleia.com>
*
* This code is released using a dual license strategy: BSD/GPL
* You can choose the licence that better fits your requirements.
*
* Released under the terms of 3-clause BSD License
* Released under the terms of GNU General Public License Version 2.0
*
*/
#ifndef __DT_BINDINGS_LPC32XX_CLOCK_H
#define __DT_BINDINGS_LPC32XX_CLOCK_H
/* LPC32XX System Control Block clocks */
#define LPC32XX_CLK_RTC 1
#define LPC32XX_CLK_DMA 2
#define LPC32XX_CLK_MLC 3
#define LPC32XX_CLK_SLC 4
#define LPC32XX_CLK_LCD 5
#define LPC32XX_CLK_MAC 6
#define LPC32XX_CLK_SD 7
#define LPC32XX_CLK_DDRAM 8
#define LPC32XX_CLK_SSP0 9
#define LPC32XX_CLK_SSP1 10
#define LPC32XX_CLK_UART3 11
#define LPC32XX_CLK_UART4 12
#define LPC32XX_CLK_UART5 13
#define LPC32XX_CLK_UART6 14
#define LPC32XX_CLK_IRDA 15
#define LPC32XX_CLK_I2C1 16
#define LPC32XX_CLK_I2C2 17
#define LPC32XX_CLK_TIMER0 18
#define LPC32XX_CLK_TIMER1 19
#define LPC32XX_CLK_TIMER2 20
#define LPC32XX_CLK_TIMER3 21
#define LPC32XX_CLK_TIMER4 22
#define LPC32XX_CLK_TIMER5 23
#define LPC32XX_CLK_WDOG 24
#define LPC32XX_CLK_I2S0 25
#define LPC32XX_CLK_I2S1 26
#define LPC32XX_CLK_SPI1 27
#define LPC32XX_CLK_SPI2 28
#define LPC32XX_CLK_MCPWM 29
#define LPC32XX_CLK_HSTIMER 30
#define LPC32XX_CLK_KEY 31
#define LPC32XX_CLK_PWM1 32
#define LPC32XX_CLK_PWM2 33
#define LPC32XX_CLK_ADC 34
/* LPC32XX USB clocks */
#define LPC32XX_USB_CLK_I2C 1
#define LPC32XX_USB_CLK_DEVICE 2
#define LPC32XX_USB_CLK_HOST 3
#endif /* __DT_BINDINGS_LPC32XX_CLOCK_H */

339
include/dt-bindings/clock/qcom,gcc-msm8996.h Normal file
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@@ -0,0 +1,339 @@
/*
* Copyright (c) 2015, The Linux Foundation. All rights reserved.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _DT_BINDINGS_CLK_MSM_GCC_8996_H
#define _DT_BINDINGS_CLK_MSM_GCC_8996_H
#define GPLL0_EARLY 0
#define GPLL0 1
#define GPLL1_EARLY 2
#define GPLL1 3
#define GPLL2_EARLY 4
#define GPLL2 5
#define GPLL3_EARLY 6
#define GPLL3 7
#define GPLL4_EARLY 8
#define GPLL4 9
#define SYSTEM_NOC_CLK_SRC 10
#define CONFIG_NOC_CLK_SRC 11
#define PERIPH_NOC_CLK_SRC 12
#define MMSS_BIMC_GFX_CLK_SRC 13
#define USB30_MASTER_CLK_SRC 14
#define USB30_MOCK_UTMI_CLK_SRC 15
#define USB3_PHY_AUX_CLK_SRC 16
#define USB20_MASTER_CLK_SRC 17
#define USB20_MOCK_UTMI_CLK_SRC 18
#define SDCC1_APPS_CLK_SRC 19
#define SDCC1_ICE_CORE_CLK_SRC 20
#define SDCC2_APPS_CLK_SRC 21
#define SDCC3_APPS_CLK_SRC 22
#define SDCC4_APPS_CLK_SRC 23
#define BLSP1_QUP1_SPI_APPS_CLK_SRC 24
#define BLSP1_QUP1_I2C_APPS_CLK_SRC 25
#define BLSP1_UART1_APPS_CLK_SRC 26
#define BLSP1_QUP2_SPI_APPS_CLK_SRC 27
#define BLSP1_QUP2_I2C_APPS_CLK_SRC 28
#define BLSP1_UART2_APPS_CLK_SRC 29
#define BLSP1_QUP3_SPI_APPS_CLK_SRC 30
#define BLSP1_QUP3_I2C_APPS_CLK_SRC 31
#define BLSP1_UART3_APPS_CLK_SRC 32
#define BLSP1_QUP4_SPI_APPS_CLK_SRC 33
#define BLSP1_QUP4_I2C_APPS_CLK_SRC 34
#define BLSP1_UART4_APPS_CLK_SRC 35
#define BLSP1_QUP5_SPI_APPS_CLK_SRC 36
#define BLSP1_QUP5_I2C_APPS_CLK_SRC 37
#define BLSP1_UART5_APPS_CLK_SRC 38
#define BLSP1_QUP6_SPI_APPS_CLK_SRC 39
#define BLSP1_QUP6_I2C_APPS_CLK_SRC 40
#define BLSP1_UART6_APPS_CLK_SRC 41
#define BLSP2_QUP1_SPI_APPS_CLK_SRC 42
#define BLSP2_QUP1_I2C_APPS_CLK_SRC 43
#define BLSP2_UART1_APPS_CLK_SRC 44
#define BLSP2_QUP2_SPI_APPS_CLK_SRC 45
#define BLSP2_QUP2_I2C_APPS_CLK_SRC 46
#define BLSP2_UART2_APPS_CLK_SRC 47
#define BLSP2_QUP3_SPI_APPS_CLK_SRC 48
#define BLSP2_QUP3_I2C_APPS_CLK_SRC 49
#define BLSP2_UART3_APPS_CLK_SRC 50
#define BLSP2_QUP4_SPI_APPS_CLK_SRC 51
#define BLSP2_QUP4_I2C_APPS_CLK_SRC 52
#define BLSP2_UART4_APPS_CLK_SRC 53
#define BLSP2_QUP5_SPI_APPS_CLK_SRC 54
#define BLSP2_QUP5_I2C_APPS_CLK_SRC 55
#define BLSP2_UART5_APPS_CLK_SRC 56
#define BLSP2_QUP6_SPI_APPS_CLK_SRC 57
#define BLSP2_QUP6_I2C_APPS_CLK_SRC 58
#define BLSP2_UART6_APPS_CLK_SRC 59
#define PDM2_CLK_SRC 60
#define TSIF_REF_CLK_SRC 61
#define CE1_CLK_SRC 62
#define GCC_SLEEP_CLK_SRC 63
#define BIMC_CLK_SRC 64
#define HMSS_AHB_CLK_SRC 65
#define BIMC_HMSS_AXI_CLK_SRC 66
#define HMSS_RBCPR_CLK_SRC 67
#define HMSS_GPLL0_CLK_SRC 68
#define GP1_CLK_SRC 69
#define GP2_CLK_SRC 70
#define GP3_CLK_SRC 71
#define PCIE_AUX_CLK_SRC 72
#define UFS_AXI_CLK_SRC 73
#define UFS_ICE_CORE_CLK_SRC 74
#define QSPI_SER_CLK_SRC 75
#define GCC_SYS_NOC_AXI_CLK 76
#define GCC_SYS_NOC_HMSS_AHB_CLK 77
#define GCC_SNOC_CNOC_AHB_CLK 78
#define GCC_SNOC_PNOC_AHB_CLK 79
#define GCC_SYS_NOC_AT_CLK 80
#define GCC_SYS_NOC_USB3_AXI_CLK 81
#define GCC_SYS_NOC_UFS_AXI_CLK 82
#define GCC_CFG_NOC_AHB_CLK 83
#define GCC_PERIPH_NOC_AHB_CLK 84
#define GCC_PERIPH_NOC_USB20_AHB_CLK 85
#define GCC_TIC_CLK 86
#define GCC_IMEM_AXI_CLK 87
#define GCC_MMSS_SYS_NOC_AXI_CLK 88
#define GCC_MMSS_NOC_CFG_AHB_CLK 89
#define GCC_MMSS_BIMC_GFX_CLK 90
#define GCC_USB30_MASTER_CLK 91
#define GCC_USB30_SLEEP_CLK 92
#define GCC_USB30_MOCK_UTMI_CLK 93
#define GCC_USB3_PHY_AUX_CLK 94
#define GCC_USB3_PHY_PIPE_CLK 95
#define GCC_USB20_MASTER_CLK 96
#define GCC_USB20_SLEEP_CLK 97
#define GCC_USB20_MOCK_UTMI_CLK 98
#define GCC_USB_PHY_CFG_AHB2PHY_CLK 99
#define GCC_SDCC1_APPS_CLK 100
#define GCC_SDCC1_AHB_CLK 101
#define GCC_SDCC1_ICE_CORE_CLK 102
#define GCC_SDCC2_APPS_CLK 103
#define GCC_SDCC2_AHB_CLK 104
#define GCC_SDCC3_APPS_CLK 105
#define GCC_SDCC3_AHB_CLK 106
#define GCC_SDCC4_APPS_CLK 107
#define GCC_SDCC4_AHB_CLK 108
#define GCC_BLSP1_AHB_CLK 109
#define GCC_BLSP1_SLEEP_CLK 110
#define GCC_BLSP1_QUP1_SPI_APPS_CLK 111
#define GCC_BLSP1_QUP1_I2C_APPS_CLK 112
#define GCC_BLSP1_UART1_APPS_CLK 113
#define GCC_BLSP1_QUP2_SPI_APPS_CLK 114
#define GCC_BLSP1_QUP2_I2C_APPS_CLK 115
#define GCC_BLSP1_UART2_APPS_CLK 116
#define GCC_BLSP1_QUP3_SPI_APPS_CLK 117
#define GCC_BLSP1_QUP3_I2C_APPS_CLK 118
#define GCC_BLSP1_UART3_APPS_CLK 119
#define GCC_BLSP1_QUP4_SPI_APPS_CLK 120
#define GCC_BLSP1_QUP4_I2C_APPS_CLK 121
#define GCC_BLSP1_UART4_APPS_CLK 122
#define GCC_BLSP1_QUP5_SPI_APPS_CLK 123
#define GCC_BLSP1_QUP5_I2C_APPS_CLK 124
#define GCC_BLSP1_UART5_APPS_CLK 125
#define GCC_BLSP1_QUP6_SPI_APPS_CLK 126
#define GCC_BLSP1_QUP6_I2C_APPS_CLK 127
#define GCC_BLSP1_UART6_APPS_CLK 128
#define GCC_BLSP2_AHB_CLK 129
#define GCC_BLSP2_SLEEP_CLK 130
#define GCC_BLSP2_QUP1_SPI_APPS_CLK 131
#define GCC_BLSP2_QUP1_I2C_APPS_CLK 132
#define GCC_BLSP2_UART1_APPS_CLK 133
#define GCC_BLSP2_QUP2_SPI_APPS_CLK 134
#define GCC_BLSP2_QUP2_I2C_APPS_CLK 135
#define GCC_BLSP2_UART2_APPS_CLK 136
#define GCC_BLSP2_QUP3_SPI_APPS_CLK 137
#define GCC_BLSP2_QUP3_I2C_APPS_CLK 138
#define GCC_BLSP2_UART3_APPS_CLK 139
#define GCC_BLSP2_QUP4_SPI_APPS_CLK 140
#define GCC_BLSP2_QUP4_I2C_APPS_CLK 141
#define GCC_BLSP2_UART4_APPS_CLK 142
#define GCC_BLSP2_QUP5_SPI_APPS_CLK 143
#define GCC_BLSP2_QUP5_I2C_APPS_CLK 144
#define GCC_BLSP2_UART5_APPS_CLK 145
#define GCC_BLSP2_QUP6_SPI_APPS_CLK 146
#define GCC_BLSP2_QUP6_I2C_APPS_CLK 147
#define GCC_BLSP2_UART6_APPS_CLK 148
#define GCC_PDM_AHB_CLK 149
#define GCC_PDM_XO4_CLK 150
#define GCC_PDM2_CLK 151
#define GCC_PRNG_AHB_CLK 152
#define GCC_TSIF_AHB_CLK 153
#define GCC_TSIF_REF_CLK 154
#define GCC_TSIF_INACTIVITY_TIMERS_CLK 155
#define GCC_TCSR_AHB_CLK 156
#define GCC_BOOT_ROM_AHB_CLK 157
#define GCC_MSG_RAM_AHB_CLK 158
#define GCC_TLMM_AHB_CLK 159
#define GCC_TLMM_CLK 160
#define GCC_MPM_AHB_CLK 161
#define GCC_SPMI_SER_CLK 162
#define GCC_SPMI_CNOC_AHB_CLK 163
#define GCC_CE1_CLK 164
#define GCC_CE1_AXI_CLK 165
#define GCC_CE1_AHB_CLK 166
#define GCC_BIMC_HMSS_AXI_CLK 167
#define GCC_BIMC_GFX_CLK 168
#define GCC_HMSS_AHB_CLK 169
#define GCC_HMSS_SLV_AXI_CLK 170
#define GCC_HMSS_MSTR_AXI_CLK 171
#define GCC_HMSS_RBCPR_CLK 172
#define GCC_GP1_CLK 173
#define GCC_GP2_CLK 174
#define GCC_GP3_CLK 175
#define GCC_PCIE_0_SLV_AXI_CLK 176
#define GCC_PCIE_0_MSTR_AXI_CLK 177
#define GCC_PCIE_0_CFG_AHB_CLK 178
#define GCC_PCIE_0_AUX_CLK 179
#define GCC_PCIE_0_PIPE_CLK 180
#define GCC_PCIE_1_SLV_AXI_CLK 181
#define GCC_PCIE_1_MSTR_AXI_CLK 182
#define GCC_PCIE_1_CFG_AHB_CLK 183
#define GCC_PCIE_1_AUX_CLK 184
#define GCC_PCIE_1_PIPE_CLK 185
#define GCC_PCIE_2_SLV_AXI_CLK 186
#define GCC_PCIE_2_MSTR_AXI_CLK 187
#define GCC_PCIE_2_CFG_AHB_CLK 188
#define GCC_PCIE_2_AUX_CLK 189
#define GCC_PCIE_2_PIPE_CLK 190
#define GCC_PCIE_PHY_CFG_AHB_CLK 191
#define GCC_PCIE_PHY_AUX_CLK 192
#define GCC_UFS_AXI_CLK 193
#define GCC_UFS_AHB_CLK 194
#define GCC_UFS_TX_CFG_CLK 195
#define GCC_UFS_RX_CFG_CLK 196
#define GCC_UFS_TX_SYMBOL_0_CLK 197
#define GCC_UFS_RX_SYMBOL_0_CLK 198
#define GCC_UFS_RX_SYMBOL_1_CLK 199
#define GCC_UFS_UNIPRO_CORE_CLK 200
#define GCC_UFS_ICE_CORE_CLK 201
#define GCC_UFS_SYS_CLK_CORE_CLK 202
#define GCC_UFS_TX_SYMBOL_CLK_CORE_CLK 203
#define GCC_AGGRE0_SNOC_AXI_CLK 204
#define GCC_AGGRE0_CNOC_AHB_CLK 205
#define GCC_SMMU_AGGRE0_AXI_CLK 206
#define GCC_SMMU_AGGRE0_AHB_CLK 207
#define GCC_AGGRE1_PNOC_AHB_CLK 208
#define GCC_AGGRE2_UFS_AXI_CLK 209
#define GCC_AGGRE2_USB3_AXI_CLK 210
#define GCC_QSPI_AHB_CLK 211
#define GCC_QSPI_SER_CLK 212
#define GCC_USB3_CLKREF_CLK 213
#define GCC_HDMI_CLKREF_CLK 214
#define GCC_UFS_CLKREF_CLK 215
#define GCC_PCIE_CLKREF_CLK 216
#define GCC_RX2_USB2_CLKREF_CLK 217
#define GCC_RX1_USB2_CLKREF_CLK 218
#define GCC_SYSTEM_NOC_BCR 0
#define GCC_CONFIG_NOC_BCR 1
#define GCC_PERIPH_NOC_BCR 2
#define GCC_IMEM_BCR 3
#define GCC_MMSS_BCR 4
#define GCC_PIMEM_BCR 5
#define GCC_QDSS_BCR 6
#define GCC_USB_30_BCR 7
#define GCC_USB_20_BCR 8
#define GCC_QUSB2PHY_PRIM_BCR 9
#define GCC_QUSB2PHY_SEC_BCR 10
#define GCC_USB_PHY_CFG_AHB2PHY_BCR 11
#define GCC_SDCC1_BCR 12
#define GCC_SDCC2_BCR 13
#define GCC_SDCC3_BCR 14
#define GCC_SDCC4_BCR 15
#define GCC_BLSP1_BCR 16
#define GCC_BLSP1_QUP1_BCR 17
#define GCC_BLSP1_UART1_BCR 18
#define GCC_BLSP1_QUP2_BCR 19
#define GCC_BLSP1_UART2_BCR 20
#define GCC_BLSP1_QUP3_BCR 21
#define GCC_BLSP1_UART3_BCR 22
#define GCC_BLSP1_QUP4_BCR 23
#define GCC_BLSP1_UART4_BCR 24
#define GCC_BLSP1_QUP5_BCR 25
#define GCC_BLSP1_UART5_BCR 26
#define GCC_BLSP1_QUP6_BCR 27
#define GCC_BLSP1_UART6_BCR 28
#define GCC_BLSP2_BCR 29
#define GCC_BLSP2_QUP1_BCR 30
#define GCC_BLSP2_UART1_BCR 31
#define GCC_BLSP2_QUP2_BCR 32
#define GCC_BLSP2_UART2_BCR 33
#define GCC_BLSP2_QUP3_BCR 34
#define GCC_BLSP2_UART3_BCR 35
#define GCC_BLSP2_QUP4_BCR 36
#define GCC_BLSP2_UART4_BCR 37
#define GCC_BLSP2_QUP5_BCR 38
#define GCC_BLSP2_UART5_BCR 39
#define GCC_BLSP2_QUP6_BCR 40
#define GCC_BLSP2_UART6_BCR 41
#define GCC_PDM_BCR 42
#define GCC_PRNG_BCR 43
#define GCC_TSIF_BCR 44
#define GCC_TCSR_BCR 45
#define GCC_BOOT_ROM_BCR 46
#define GCC_MSG_RAM_BCR 47
#define GCC_TLMM_BCR 48
#define GCC_MPM_BCR 49
#define GCC_SEC_CTRL_BCR 50
#define GCC_SPMI_BCR 51
#define GCC_SPDM_BCR 52
#define GCC_CE1_BCR 53
#define GCC_BIMC_BCR 54
#define GCC_SNOC_BUS_TIMEOUT0_BCR 55
#define GCC_SNOC_BUS_TIMEOUT2_BCR 56
#define GCC_SNOC_BUS_TIMEOUT1_BCR 57
#define GCC_SNOC_BUS_TIMEOUT3_BCR 58
#define GCC_SNOC_BUS_TIMEOUT_EXTREF_BCR 59
#define GCC_PNOC_BUS_TIMEOUT0_BCR 60
#define GCC_PNOC_BUS_TIMEOUT1_BCR 61
#define GCC_PNOC_BUS_TIMEOUT2_BCR 62
#define GCC_PNOC_BUS_TIMEOUT3_BCR 63
#define GCC_PNOC_BUS_TIMEOUT4_BCR 64
#define GCC_CNOC_BUS_TIMEOUT0_BCR 65
#define GCC_CNOC_BUS_TIMEOUT1_BCR 66
#define GCC_CNOC_BUS_TIMEOUT2_BCR 67
#define GCC_CNOC_BUS_TIMEOUT3_BCR 68
#define GCC_CNOC_BUS_TIMEOUT4_BCR 69
#define GCC_CNOC_BUS_TIMEOUT5_BCR 70
#define GCC_CNOC_BUS_TIMEOUT6_BCR 71
#define GCC_CNOC_BUS_TIMEOUT7_BCR 72
#define GCC_CNOC_BUS_TIMEOUT8_BCR 73
#define GCC_CNOC_BUS_TIMEOUT9_BCR 74
#define GCC_CNOC_BUS_TIMEOUT_EXTREF_BCR 75
#define GCC_APB2JTAG_BCR 76
#define GCC_RBCPR_CX_BCR 77
#define GCC_RBCPR_MX_BCR 78
#define GCC_PCIE_0_BCR 79
#define GCC_PCIE_0_PHY_BCR 80
#define GCC_PCIE_1_BCR 81
#define GCC_PCIE_1_PHY_BCR 82
#define GCC_PCIE_2_BCR 83
#define GCC_PCIE_2_PHY_BCR 84
#define GCC_PCIE_PHY_BCR 85
#define GCC_DCD_BCR 86
#define GCC_OBT_ODT_BCR 87
#define GCC_UFS_BCR 88
#define GCC_SSC_BCR 89
#define GCC_VS_BCR 90
#define GCC_AGGRE0_NOC_BCR 91
#define GCC_AGGRE1_NOC_BCR 92
#define GCC_AGGRE2_NOC_BCR 93
#define GCC_DCC_BCR 94
#define GCC_IPA_BCR 95
#define GCC_QSPI_BCR 96
#define GCC_SKL_BCR 97
#define GCC_MSMPU_BCR 98
#define GCC_MSS_Q6_BCR 99
#define GCC_QREFS_VBG_CAL_BCR 100
#endif

285
include/dt-bindings/clock/qcom,mmcc-msm8996.h Normal file
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@@ -0,0 +1,285 @@
/*
* Copyright (c) 2015, The Linux Foundation. All rights reserved.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _DT_BINDINGS_CLK_MSM_MMCC_8996_H
#define _DT_BINDINGS_CLK_MSM_MMCC_8996_H
#define MMPLL0_EARLY 0
#define MMPLL0_PLL 1
#define MMPLL1_EARLY 2
#define MMPLL1_PLL 3
#define MMPLL2_EARLY 4
#define MMPLL2_PLL 5
#define MMPLL3_EARLY 6
#define MMPLL3_PLL 7
#define MMPLL4_EARLY 8
#define MMPLL4_PLL 9
#define MMPLL5_EARLY 10
#define MMPLL5_PLL 11
#define MMPLL8_EARLY 12
#define MMPLL8_PLL 13
#define MMPLL9_EARLY 14
#define MMPLL9_PLL 15
#define AHB_CLK_SRC 16
#define AXI_CLK_SRC 17
#define MAXI_CLK_SRC 18
#define DSA_CORE_CLK_SRC 19
#define GFX3D_CLK_SRC 20
#define RBBMTIMER_CLK_SRC 21
#define ISENSE_CLK_SRC 22
#define RBCPR_CLK_SRC 23
#define VIDEO_CORE_CLK_SRC 24
#define VIDEO_SUBCORE0_CLK_SRC 25
#define VIDEO_SUBCORE1_CLK_SRC 26
#define PCLK0_CLK_SRC 27
#define PCLK1_CLK_SRC 28
#define MDP_CLK_SRC 29
#define EXTPCLK_CLK_SRC 30
#define VSYNC_CLK_SRC 31
#define HDMI_CLK_SRC 32
#define BYTE0_CLK_SRC 33
#define BYTE1_CLK_SRC 34
#define ESC0_CLK_SRC 35
#define ESC1_CLK_SRC 36
#define CAMSS_GP0_CLK_SRC 37
#define CAMSS_GP1_CLK_SRC 38
#define MCLK0_CLK_SRC 39
#define MCLK1_CLK_SRC 40
#define MCLK2_CLK_SRC 41
#define MCLK3_CLK_SRC 42
#define CCI_CLK_SRC 43
#define CSI0PHYTIMER_CLK_SRC 44
#define CSI1PHYTIMER_CLK_SRC 45
#define CSI2PHYTIMER_CLK_SRC 46
#define CSIPHY0_3P_CLK_SRC 47
#define CSIPHY1_3P_CLK_SRC 48
#define CSIPHY2_3P_CLK_SRC 49
#define JPEG0_CLK_SRC 50
#define JPEG2_CLK_SRC 51
#define JPEG_DMA_CLK_SRC 52
#define VFE0_CLK_SRC 53
#define VFE1_CLK_SRC 54
#define CPP_CLK_SRC 55
#define CSI0_CLK_SRC 56
#define CSI1_CLK_SRC 57
#define CSI2_CLK_SRC 58
#define CSI3_CLK_SRC 59
#define FD_CORE_CLK_SRC 60
#define MMSS_CXO_CLK 61
#define MMSS_SLEEPCLK_CLK 62
#define MMSS_MMAGIC_AHB_CLK 63
#define MMSS_MMAGIC_CFG_AHB_CLK 64
#define MMSS_MISC_AHB_CLK 65
#define MMSS_MISC_CXO_CLK 66
#define MMSS_BTO_AHB_CLK 67
#define MMSS_MMAGIC_AXI_CLK 68
#define MMSS_S0_AXI_CLK 69
#define MMSS_MMAGIC_MAXI_CLK 70
#define DSA_CORE_CLK 71
#define DSA_NOC_CFG_AHB_CLK 72
#define MMAGIC_CAMSS_AXI_CLK 73
#define MMAGIC_CAMSS_NOC_CFG_AHB_CLK 74
#define THROTTLE_CAMSS_CXO_CLK 75
#define THROTTLE_CAMSS_AHB_CLK 76
#define THROTTLE_CAMSS_AXI_CLK 77
#define SMMU_VFE_AHB_CLK 78
#define SMMU_VFE_AXI_CLK 79
#define SMMU_CPP_AHB_CLK 80
#define SMMU_CPP_AXI_CLK 81
#define SMMU_JPEG_AHB_CLK 82
#define SMMU_JPEG_AXI_CLK 83
#define MMAGIC_MDSS_AXI_CLK 84
#define MMAGIC_MDSS_NOC_CFG_AHB_CLK 85
#define THROTTLE_MDSS_CXO_CLK 86
#define THROTTLE_MDSS_AHB_CLK 87
#define THROTTLE_MDSS_AXI_CLK 88
#define SMMU_ROT_AHB_CLK 89
#define SMMU_ROT_AXI_CLK 90
#define SMMU_MDP_AHB_CLK 91
#define SMMU_MDP_AXI_CLK 92
#define MMAGIC_VIDEO_AXI_CLK 93
#define MMAGIC_VIDEO_NOC_CFG_AHB_CLK 94
#define THROTTLE_VIDEO_CXO_CLK 95
#define THROTTLE_VIDEO_AHB_CLK 96
#define THROTTLE_VIDEO_AXI_CLK 97
#define SMMU_VIDEO_AHB_CLK 98
#define SMMU_VIDEO_AXI_CLK 99
#define MMAGIC_BIMC_AXI_CLK 100
#define MMAGIC_BIMC_NOC_CFG_AHB_CLK 101
#define GPU_GX_GFX3D_CLK 102
#define GPU_GX_RBBMTIMER_CLK 103
#define GPU_AHB_CLK 104
#define GPU_AON_ISENSE_CLK 105
#define VMEM_MAXI_CLK 106
#define VMEM_AHB_CLK 107
#define MMSS_RBCPR_CLK 108
#define MMSS_RBCPR_AHB_CLK 109
#define VIDEO_CORE_CLK 110
#define VIDEO_AXI_CLK 111
#define VIDEO_MAXI_CLK 112
#define VIDEO_AHB_CLK 113
#define VIDEO_SUBCORE0_CLK 114
#define VIDEO_SUBCORE1_CLK 115
#define MDSS_AHB_CLK 116
#define MDSS_HDMI_AHB_CLK 117
#define MDSS_AXI_CLK 118
#define MDSS_PCLK0_CLK 119
#define MDSS_PCLK1_CLK 120
#define MDSS_MDP_CLK 121
#define MDSS_EXTPCLK_CLK 122
#define MDSS_VSYNC_CLK 123
#define MDSS_HDMI_CLK 124
#define MDSS_BYTE0_CLK 125
#define MDSS_BYTE1_CLK 126
#define MDSS_ESC0_CLK 127
#define MDSS_ESC1_CLK 128
#define CAMSS_TOP_AHB_CLK 129
#define CAMSS_AHB_CLK 130
#define CAMSS_MICRO_AHB_CLK 131
#define CAMSS_GP0_CLK 132
#define CAMSS_GP1_CLK 133
#define CAMSS_MCLK0_CLK 134
#define CAMSS_MCLK1_CLK 135
#define CAMSS_MCLK2_CLK 136
#define CAMSS_MCLK3_CLK 137
#define CAMSS_CCI_CLK 138
#define CAMSS_CCI_AHB_CLK 139
#define CAMSS_CSI0PHYTIMER_CLK 140
#define CAMSS_CSI1PHYTIMER_CLK 141
#define CAMSS_CSI2PHYTIMER_CLK 142
#define CAMSS_CSIPHY0_3P_CLK 143
#define CAMSS_CSIPHY1_3P_CLK 144
#define CAMSS_CSIPHY2_3P_CLK 145
#define CAMSS_JPEG0_CLK 146
#define CAMSS_JPEG2_CLK 147
#define CAMSS_JPEG_DMA_CLK 148
#define CAMSS_JPEG_AHB_CLK 149
#define CAMSS_JPEG_AXI_CLK 150
#define CAMSS_VFE_AHB_CLK 151
#define CAMSS_VFE_AXI_CLK 152
#define CAMSS_VFE0_CLK 153
#define CAMSS_VFE0_STREAM_CLK 154
#define CAMSS_VFE0_AHB_CLK 155
#define CAMSS_VFE1_CLK 156
#define CAMSS_VFE1_STREAM_CLK 157
#define CAMSS_VFE1_AHB_CLK 158
#define CAMSS_CSI_VFE0_CLK 159
#define CAMSS_CSI_VFE1_CLK 160
#define CAMSS_CPP_VBIF_AHB_CLK 161
#define CAMSS_CPP_AXI_CLK 162
#define CAMSS_CPP_CLK 163
#define CAMSS_CPP_AHB_CLK 164
#define CAMSS_CSI0_CLK 165
#define CAMSS_CSI0_AHB_CLK 166
#define CAMSS_CSI0PHY_CLK 167
#define CAMSS_CSI0RDI_CLK 168
#define CAMSS_CSI0PIX_CLK 169
#define CAMSS_CSI1_CLK 170
#define CAMSS_CSI1_AHB_CLK 171
#define CAMSS_CSI1PHY_CLK 172
#define CAMSS_CSI1RDI_CLK 173
#define CAMSS_CSI1PIX_CLK 174
#define CAMSS_CSI2_CLK 175
#define CAMSS_CSI2_AHB_CLK 176
#define CAMSS_CSI2PHY_CLK 177
#define CAMSS_CSI2RDI_CLK 178
#define CAMSS_CSI2PIX_CLK 179
#define CAMSS_CSI3_CLK 180
#define CAMSS_CSI3_AHB_CLK 181
#define CAMSS_CSI3PHY_CLK 182
#define CAMSS_CSI3RDI_CLK 183
#define CAMSS_CSI3PIX_CLK 184
#define CAMSS_ISPIF_AHB_CLK 185
#define FD_CORE_CLK 186
#define FD_CORE_UAR_CLK 187
#define FD_AHB_CLK 188
#define MMSS_SPDM_CSI0_CLK 189
#define MMSS_SPDM_JPEG_DMA_CLK 190
#define MMSS_SPDM_CPP_CLK 191
#define MMSS_SPDM_PCLK0_CLK 192
#define MMSS_SPDM_AHB_CLK 193
#define MMSS_SPDM_GFX3D_CLK 194
#define MMSS_SPDM_PCLK1_CLK 195
#define MMSS_SPDM_JPEG2_CLK 196
#define MMSS_SPDM_DEBUG_CLK 197
#define MMSS_SPDM_VFE1_CLK 198
#define MMSS_SPDM_VFE0_CLK 199
#define MMSS_SPDM_VIDEO_CORE_CLK 200
#define MMSS_SPDM_AXI_CLK 201
#define MMSS_SPDM_MDP_CLK 202
#define MMSS_SPDM_JPEG0_CLK 203
#define MMSS_SPDM_RM_AXI_CLK 204
#define MMSS_SPDM_RM_MAXI_CLK 205
#define MMAGICAHB_BCR 0
#define MMAGIC_CFG_BCR 1
#define MISC_BCR 2
#define BTO_BCR 3
#define MMAGICAXI_BCR 4
#define MMAGICMAXI_BCR 5
#define DSA_BCR 6
#define MMAGIC_CAMSS_BCR 7
#define THROTTLE_CAMSS_BCR 8
#define SMMU_VFE_BCR 9
#define SMMU_CPP_BCR 10
#define SMMU_JPEG_BCR 11
#define MMAGIC_MDSS_BCR 12
#define THROTTLE_MDSS_BCR 13
#define SMMU_ROT_BCR 14
#define SMMU_MDP_BCR 15
#define MMAGIC_VIDEO_BCR 16
#define THROTTLE_VIDEO_BCR 17
#define SMMU_VIDEO_BCR 18
#define MMAGIC_BIMC_BCR 19
#define GPU_GX_BCR 20
#define GPU_BCR 21
#define GPU_AON_BCR 22
#define VMEM_BCR 23
#define MMSS_RBCPR_BCR 24
#define VIDEO_BCR 25
#define MDSS_BCR 26
#define CAMSS_TOP_BCR 27
#define CAMSS_AHB_BCR 28
#define CAMSS_MICRO_BCR 29
#define CAMSS_CCI_BCR 30
#define CAMSS_PHY0_BCR 31
#define CAMSS_PHY1_BCR 32
#define CAMSS_PHY2_BCR 33
#define CAMSS_CSIPHY0_3P_BCR 34
#define CAMSS_CSIPHY1_3P_BCR 35
#define CAMSS_CSIPHY2_3P_BCR 36
#define CAMSS_JPEG_BCR 37
#define CAMSS_VFE_BCR 38
#define CAMSS_VFE0_BCR 39
#define CAMSS_VFE1_BCR 40
#define CAMSS_CSI_VFE0_BCR 41
#define CAMSS_CSI_VFE1_BCR 42
#define CAMSS_CPP_TOP_BCR 43
#define CAMSS_CPP_BCR 44
#define CAMSS_CSI0_BCR 45
#define CAMSS_CSI0RDI_BCR 46
#define CAMSS_CSI0PIX_BCR 47
#define CAMSS_CSI1_BCR 48
#define CAMSS_CSI1RDI_BCR 49
#define CAMSS_CSI1PIX_BCR 50
#define CAMSS_CSI2_BCR 51
#define CAMSS_CSI2RDI_BCR 52
#define CAMSS_CSI2PIX_BCR 53
#define CAMSS_CSI3_BCR 54
#define CAMSS_CSI3RDI_BCR 55
#define CAMSS_CSI3PIX_BCR 56
#define CAMSS_ISPIF_BCR 57
#define FD_BCR 58
#define MMSS_SPDM_RM_BCR 59
#endif

193
include/dt-bindings/clock/rk3036-cru.h Normal file
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@@ -0,0 +1,193 @@
/*
* Copyright (c) 2015 Rockchip Electronics Co. Ltd.
* Author: Xing Zheng <zhengxing@rock-chips.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H
#define _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H
/* core clocks */
#define PLL_APLL 1
#define PLL_DPLL 2
#define PLL_GPLL 3
#define ARMCLK 4
/* sclk gates (special clocks) */
#define SCLK_GPU 64
#define SCLK_SPI 65
#define SCLK_SDMMC 68
#define SCLK_SDIO 69
#define SCLK_EMMC 71
#define SCLK_NANDC 76
#define SCLK_UART0 77
#define SCLK_UART1 78
#define SCLK_UART2 79
#define SCLK_I2S 82
#define SCLK_SPDIF 83
#define SCLK_TIMER0 85
#define SCLK_TIMER1 86
#define SCLK_TIMER2 87
#define SCLK_TIMER3 88
#define SCLK_OTGPHY0 93
#define SCLK_LCDC 100
#define SCLK_HDMI 109
#define SCLK_HEVC 111
#define SCLK_I2S_OUT 113
#define SCLK_SDMMC_DRV 114
#define SCLK_SDIO_DRV 115
#define SCLK_EMMC_DRV 117
#define SCLK_SDMMC_SAMPLE 118
#define SCLK_SDIO_SAMPLE 119
#define SCLK_EMMC_SAMPLE 121
#define SCLK_PVTM_CORE 123
#define SCLK_PVTM_GPU 124
#define SCLK_PVTM_VIDEO 125
#define SCLK_MAC 151
#define SCLK_MACREF 152
#define SCLK_SFC 160
/* aclk gates */
#define ACLK_DMAC2 194
#define ACLK_LCDC 197
#define ACLK_VIO 203
#define ACLK_VCODEC 208
#define ACLK_CPU 209
#define ACLK_PERI 210
/* pclk gates */
#define PCLK_GPIO0 320
#define PCLK_GPIO1 321
#define PCLK_GPIO2 322
#define PCLK_GRF 329
#define PCLK_I2C0 332
#define PCLK_I2C1 333
#define PCLK_I2C2 334
#define PCLK_SPI 338
#define PCLK_UART0 341
#define PCLK_UART1 342
#define PCLK_UART2 343
#define PCLK_PWM 350
#define PCLK_TIMER 353
#define PCLK_HDMI 360
#define PCLK_CPU 362
#define PCLK_PERI 363
#define PCLK_DDRUPCTL 364
#define PCLK_WDT 368
#define PCLK_ACODEC 369
/* hclk gates */
#define HCLK_OTG0 449
#define HCLK_OTG1 450
#define HCLK_NANDC 453
#define HCLK_SDMMC 456
#define HCLK_SDIO 457
#define HCLK_EMMC 459
#define HCLK_I2S 462
#define HCLK_LCDC 465
#define HCLK_ROM 467
#define HCLK_VIO_BUS 472
#define HCLK_VCODEC 476
#define HCLK_CPU 477
#define HCLK_PERI 478
#define CLK_NR_CLKS (HCLK_PERI + 1)
/* soft-reset indices */
#define SRST_CORE0 0
#define SRST_CORE1 1
#define SRST_CORE0_DBG 4
#define SRST_CORE1_DBG 5
#define SRST_CORE0_POR 8
#define SRST_CORE1_POR 9
#define SRST_L2C 12
#define SRST_TOPDBG 13
#define SRST_STRC_SYS_A 14
#define SRST_PD_CORE_NIU 15
#define SRST_TIMER2 16
#define SRST_CPUSYS_H 17
#define SRST_AHB2APB_H 19
#define SRST_TIMER3 20
#define SRST_INTMEM 21
#define SRST_ROM 22
#define SRST_PERI_NIU 23
#define SRST_I2S 24
#define SRST_DDR_PLL 25
#define SRST_GPU_DLL 26
#define SRST_TIMER0 27
#define SRST_TIMER1 28
#define SRST_CORE_DLL 29
#define SRST_EFUSE_P 30
#define SRST_ACODEC_P 31
#define SRST_GPIO0 32
#define SRST_GPIO1 33
#define SRST_GPIO2 34
#define SRST_UART0 39
#define SRST_UART1 40
#define SRST_UART2 41
#define SRST_I2C0 43
#define SRST_I2C1 44
#define SRST_I2C2 45
#define SRST_SFC 47
#define SRST_PWM0 48
#define SRST_DAP 51
#define SRST_DAP_SYS 52
#define SRST_GRF 55
#define SRST_PERIPHSYS_A 57
#define SRST_PERIPHSYS_H 58
#define SRST_PERIPHSYS_P 59
#define SRST_CPU_PERI 61
#define SRST_EMEM_PERI 62
#define SRST_USB_PERI 63
#define SRST_DMA2 64
#define SRST_MAC 66
#define SRST_NANDC 68
#define SRST_USBOTG0 69
#define SRST_OTGC0 71
#define SRST_USBOTG1 72
#define SRST_OTGC1 74
#define SRST_DDRMSCH 79
#define SRST_MMC0 81
#define SRST_SDIO 82
#define SRST_EMMC 83
#define SRST_SPI0 84
#define SRST_WDT 86
#define SRST_DDRPHY 88
#define SRST_DDRPHY_P 89
#define SRST_DDRCTRL 90
#define SRST_DDRCTRL_P 91
#define SRST_HDMI_P 96
#define SRST_VIO_BUS_H 99
#define SRST_UTMI0 103
#define SRST_UTMI1 104
#define SRST_USBPOR 105
#define SRST_VCODEC_A 112
#define SRST_VCODEC_H 113
#define SRST_VIO1_A 114
#define SRST_HEVC 115
#define SRST_VCODEC_NIU_A 116
#define SRST_LCDC1_A 117
#define SRST_LCDC1_H 118
#define SRST_LCDC1_D 119
#define SRST_GPU 120
#define SRST_GPU_NIU_A 122
#define SRST_DBG_P 131
#endif

220
include/dt-bindings/clock/rk3228-cru.h Normal file
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@@ -0,0 +1,220 @@
/*
* Copyright (c) 2015 Rockchip Electronics Co. Ltd.
* Author: Jeffy Chen <jeffy.chen@rock-chips.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H
#define _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H
/* core clocks */
#define PLL_APLL 1
#define PLL_DPLL 2
#define PLL_CPLL 3
#define PLL_GPLL 4
#define ARMCLK 5
/* sclk gates (special clocks) */
#define SCLK_SPI0 65
#define SCLK_NANDC 67
#define SCLK_SDMMC 68
#define SCLK_SDIO 69
#define SCLK_EMMC 71
#define SCLK_UART0 77
#define SCLK_UART1 78
#define SCLK_UART2 79
#define SCLK_I2S0 80
#define SCLK_I2S1 81
#define SCLK_I2S2 82
#define SCLK_SPDIF 83
#define SCLK_TIMER0 85
#define SCLK_TIMER1 86
#define SCLK_TIMER2 87
#define SCLK_TIMER3 88
#define SCLK_TIMER4 89
#define SCLK_TIMER5 90
#define SCLK_I2S_OUT 113
#define SCLK_SDMMC_DRV 114
#define SCLK_SDIO_DRV 115
#define SCLK_EMMC_DRV 117
#define SCLK_SDMMC_SAMPLE 118
#define SCLK_SDIO_SAMPLE 119
#define SCLK_EMMC_SAMPLE 121
/* aclk gates */
#define ACLK_DMAC 194
#define ACLK_PERI 210
/* pclk gates */
#define PCLK_GPIO0 320
#define PCLK_GPIO1 321
#define PCLK_GPIO2 322
#define PCLK_GPIO3 323
#define PCLK_GRF 329
#define PCLK_I2C0 332
#define PCLK_I2C1 333
#define PCLK_I2C2 334
#define PCLK_I2C3 335
#define PCLK_SPI0 338
#define PCLK_UART0 341
#define PCLK_UART1 342
#define PCLK_UART2 343
#define PCLK_PWM 350
#define PCLK_TIMER 353
#define PCLK_PERI 363
/* hclk gates */
#define HCLK_NANDC 453
#define HCLK_SDMMC 456
#define HCLK_SDIO 457
#define HCLK_EMMC 459
#define HCLK_PERI 478
#define CLK_NR_CLKS (HCLK_PERI + 1)
/* soft-reset indices */
#define SRST_CORE0_PO 0
#define SRST_CORE1_PO 1
#define SRST_CORE2_PO 2
#define SRST_CORE3_PO 3
#define SRST_CORE0 4
#define SRST_CORE1 5
#define SRST_CORE2 6
#define SRST_CORE3 7
#define SRST_CORE0_DBG 8
#define SRST_CORE1_DBG 9
#define SRST_CORE2_DBG 10
#define SRST_CORE3_DBG 11
#define SRST_TOPDBG 12
#define SRST_ACLK_CORE 13
#define SRST_NOC 14
#define SRST_L2C 15
#define SRST_CPUSYS_H 18
#define SRST_BUSSYS_H 19
#define SRST_SPDIF 20
#define SRST_INTMEM 21
#define SRST_ROM 22
#define SRST_OTG_ADP 23
#define SRST_I2S0 24
#define SRST_I2S1 25
#define SRST_I2S2 26
#define SRST_ACODEC_P 27
#define SRST_DFIMON 28
#define SRST_MSCH 29
#define SRST_EFUSE1024 30
#define SRST_EFUSE256 31
#define SRST_GPIO0 32
#define SRST_GPIO1 33
#define SRST_GPIO2 34
#define SRST_GPIO3 35
#define SRST_PERIPH_NOC_A 36
#define SRST_PERIPH_NOC_BUS_H 37
#define SRST_PERIPH_NOC_P 38
#define SRST_UART0 39
#define SRST_UART1 40
#define SRST_UART2 41
#define SRST_PHYNOC 42
#define SRST_I2C0 43
#define SRST_I2C1 44
#define SRST_I2C2 45
#define SRST_I2C3 46
#define SRST_PWM 48
#define SRST_A53_GIC 49
#define SRST_DAP 51
#define SRST_DAP_NOC 52
#define SRST_CRYPTO 53
#define SRST_SGRF 54
#define SRST_GRF 55
#define SRST_GMAC 56
#define SRST_PERIPH_NOC_H 58
#define SRST_MACPHY 63
#define SRST_DMA 64
#define SRST_NANDC 68
#define SRST_USBOTG 69
#define SRST_OTGC 70
#define SRST_USBHOST0 71
#define SRST_HOST_CTRL0 72
#define SRST_USBHOST1 73
#define SRST_HOST_CTRL1 74
#define SRST_USBHOST2 75
#define SRST_HOST_CTRL2 76
#define SRST_USBPOR0 77
#define SRST_USBPOR1 78
#define SRST_DDRMSCH 79
#define SRST_SMART_CARD 80
#define SRST_SDMMC 81
#define SRST_SDIO 82
#define SRST_EMMC 83
#define SRST_SPI 84
#define SRST_TSP_H 85
#define SRST_TSP 86
#define SRST_TSADC 87
#define SRST_DDRPHY 88
#define SRST_DDRPHY_P 89
#define SRST_DDRCTRL 90
#define SRST_DDRCTRL_P 91
#define SRST_HOST0_ECHI 92
#define SRST_HOST1_ECHI 93
#define SRST_HOST2_ECHI 94
#define SRST_VOP_NOC_A 95
#define SRST_HDMI_P 96
#define SRST_VIO_ARBI_H 97
#define SRST_IEP_NOC_A 98
#define SRST_VIO_NOC_H 99
#define SRST_VOP_A 100
#define SRST_VOP_H 101
#define SRST_VOP_D 102
#define SRST_UTMI0 103
#define SRST_UTMI1 104
#define SRST_UTMI2 105
#define SRST_UTMI3 106
#define SRST_RGA 107
#define SRST_RGA_NOC_A 108
#define SRST_RGA_A 109
#define SRST_RGA_H 110
#define SRST_HDCP_A 111
#define SRST_VPU_A 112
#define SRST_VPU_H 113
#define SRST_VPU_NOC_A 116
#define SRST_VPU_NOC_H 117
#define SRST_RKVDEC_A 118
#define SRST_RKVDEC_NOC_A 119
#define SRST_RKVDEC_H 120
#define SRST_RKVDEC_NOC_H 121
#define SRST_RKVDEC_CORE 122
#define SRST_RKVDEC_CABAC 123
#define SRST_IEP_A 124
#define SRST_IEP_H 125
#define SRST_GPU_A 126
#define SRST_GPU_NOC_A 127
#define SRST_CORE_DBG 128
#define SRST_DBG_P 129
#define SRST_TIMER0 130
#define SRST_TIMER1 131
#define SRST_TIMER2 132
#define SRST_TIMER3 133
#define SRST_TIMER4 134
#define SRST_TIMER5 135
#define SRST_VIO_H2P 136
#define SRST_HDMIPHY 139
#define SRST_VDAC 140
#define SRST_TIMER_6CH_P 141
#endif

4
include/dt-bindings/clock/rk3288-cru.h
View File

@@ -86,6 +86,8 @@
#define SCLK_USBPHY480M_SRC 122
#define SCLK_PVTM_CORE 123
#define SCLK_PVTM_GPU 124
#define SCLK_CRYPTO 125
#define SCLK_MIPIDSI_24M 126
#define SCLK_MAC 151
#define SCLK_MACREF_OUT 152
@@ -164,6 +166,8 @@
#define PCLK_DDRUPCTL1 366
#define PCLK_PUBL1 367
#define PCLK_WDT 368
#define PCLK_EFUSE256 369
#define PCLK_EFUSE1024 370
/* hclk gates */
#define HCLK_GPS 448

401
include/dt-bindings/clock/tegra210-car.h Normal file
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/*
* This header provides constants for binding nvidia,tegra210-car.
*
* The first 224 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
* registers. These IDs often match those in the CAR's RST_DEVICES registers,
* but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
* this case, those clocks are assigned IDs above 224 in order to highlight
* this issue. Implementations that interpret these clock IDs as bit values
* within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
* explicitly handle these special cases.
*
* The balance of the clocks controlled by the CAR are assigned IDs of 224 and
* above.
*/
#ifndef _DT_BINDINGS_CLOCK_TEGRA210_CAR_H
#define _DT_BINDINGS_CLOCK_TEGRA210_CAR_H
/* 0 */
/* 1 */
/* 2 */
#define TEGRA210_CLK_ISPB 3
#define TEGRA210_CLK_RTC 4
#define TEGRA210_CLK_TIMER 5
#define TEGRA210_CLK_UARTA 6
/* 7 (register bit affects uartb and vfir) */
#define TEGRA210_CLK_GPIO 8
#define TEGRA210_CLK_SDMMC2 9
/* 10 (register bit affects spdif_in and spdif_out) */
#define TEGRA210_CLK_I2S1 11
#define TEGRA210_CLK_I2C1 12
/* 13 */
#define TEGRA210_CLK_SDMMC1 14
#define TEGRA210_CLK_SDMMC4 15
/* 16 */
#define TEGRA210_CLK_PWM 17
#define TEGRA210_CLK_I2S2 18
/* 19 */
/* 20 (register bit affects vi and vi_sensor) */
/* 21 */
#define TEGRA210_CLK_USBD 22
#define TEGRA210_CLK_ISP 23
/* 24 */
/* 25 */
#define TEGRA210_CLK_DISP2 26
#define TEGRA210_CLK_DISP1 27
#define TEGRA210_CLK_HOST1X 28
/* 29 */
#define TEGRA210_CLK_I2S0 30
/* 31 */
#define TEGRA210_CLK_MC 32
#define TEGRA210_CLK_AHBDMA 33
#define TEGRA210_CLK_APBDMA 34
/* 35 */
/* 36 */
/* 37 */
#define TEGRA210_CLK_PMC 38
/* 39 (register bit affects fuse and fuse_burn) */
#define TEGRA210_CLK_KFUSE 40
#define TEGRA210_CLK_SBC1 41
/* 42 */
/* 43 */
#define TEGRA210_CLK_SBC2 44
/* 45 */
#define TEGRA210_CLK_SBC3 46
#define TEGRA210_CLK_I2C5 47
#define TEGRA210_CLK_DSIA 48
/* 49 */
/* 50 */
/* 51 */
#define TEGRA210_CLK_CSI 52
/* 53 */
#define TEGRA210_CLK_I2C2 54
#define TEGRA210_CLK_UARTC 55
#define TEGRA210_CLK_MIPI_CAL 56
#define TEGRA210_CLK_EMC 57
#define TEGRA210_CLK_USB2 58
/* 59 */
/* 60 */
/* 61 */
/* 62 */
#define TEGRA210_CLK_BSEV 63
/* 64 */
#define TEGRA210_CLK_UARTD 65
/* 66 */
#define TEGRA210_CLK_I2C3 67
#define TEGRA210_CLK_SBC4 68
#define TEGRA210_CLK_SDMMC3 69
#define TEGRA210_CLK_PCIE 70
#define TEGRA210_CLK_OWR 71
#define TEGRA210_CLK_AFI 72
#define TEGRA210_CLK_CSITE 73
/* 74 */
/* 75 */
/* 76 */
/* 77 */
#define TEGRA210_CLK_SOC_THERM 78
#define TEGRA210_CLK_DTV 79
/* 80 */
#define TEGRA210_CLK_I2CSLOW 81
#define TEGRA210_CLK_DSIB 82
#define TEGRA210_CLK_TSEC 83
/* 84 */
/* 85 */
/* 86 */
/* 87 */
/* 88 */
#define TEGRA210_CLK_XUSB_HOST 89
/* 90 */
/* 91 */
#define TEGRA210_CLK_CSUS 92
/* 93 */
/* 94 */
/* 95 (bit affects xusb_dev and xusb_dev_src) */
/* 96 */
/* 97 */
/* 98 */
#define TEGRA210_CLK_MSELECT 99
#define TEGRA210_CLK_TSENSOR 100
#define TEGRA210_CLK_I2S3 101
#define TEGRA210_CLK_I2S4 102
#define TEGRA210_CLK_I2C4 103
/* 104 */
/* 105 */
#define TEGRA210_CLK_D_AUDIO 106
/* 107 ( affects abp -> ape) */
/* 108 */
/* 109 */
/* 110 */
#define TEGRA210_CLK_HDA2CODEC_2X 111
/* 112 */
/* 113 */
/* 114 */
/* 115 */
/* 116 */
/* 117 */
#define TEGRA210_CLK_SPDIF_2X 118
#define TEGRA210_CLK_ACTMON 119
#define TEGRA210_CLK_EXTERN1 120
#define TEGRA210_CLK_EXTERN2 121
#define TEGRA210_CLK_EXTERN3 122
#define TEGRA210_CLK_SATA_OOB 123
#define TEGRA210_CLK_SATA 124
#define TEGRA210_CLK_HDA 125
/* 126 */
/* 127 */
#define TEGRA210_CLK_HDA2HDMI 128
/* 129 */
/* 130 */
/* 131 */
/* 132 */
/* 133 */
/* 134 */
/* 135 */
/* 136 */
/* 137 */
/* 138 */
/* 139 */
/* 140 */
/* 141 */
/* 142 */
/* (bit affects xusb_falcon_src, xusb_fs_src, xusb_host_src and xusb_ss_src) */
#define TEGRA210_CLK_XUSB_GATE 143
#define TEGRA210_CLK_CILAB 144
#define TEGRA210_CLK_CILCD 145
#define TEGRA210_CLK_CILE 146
#define TEGRA210_CLK_DSIALP 147
#define TEGRA210_CLK_DSIBLP 148
#define TEGRA210_CLK_ENTROPY 149
/* 150 */
/* 151 */
/* 152 */
/* 153 */
/* 154 */
/* 155 (bit affects dfll_ref and dfll_soc) */
#define TEGRA210_CLK_XUSB_SS 156
/* 157 */
/* 158 */
/* 159 */
/* 160 */
#define TEGRA210_CLK_DMIC1 161
#define TEGRA210_CLK_DMIC2 162
/* 163 */
/* 164 */
/* 165 */
#define TEGRA210_CLK_I2C6 166
/* 167 */
/* 168 */
/* 169 */
/* 170 */
#define TEGRA210_CLK_VIM2_CLK 171
/* 172 */
#define TEGRA210_CLK_MIPIBIF 173
/* 174 */
/* 175 */
/* 176 */
#define TEGRA210_CLK_CLK72MHZ 177
#define TEGRA210_CLK_VIC03 178
/* 179 */
/* 180 */
#define TEGRA210_CLK_DPAUX 181
#define TEGRA210_CLK_SOR0 182
#define TEGRA210_CLK_SOR1 183
#define TEGRA210_CLK_GPU 184
#define TEGRA210_CLK_DBGAPB 185
/* 186 */
#define TEGRA210_CLK_PLL_P_OUT_ADSP 187
/* 188 */
#define TEGRA210_CLK_PLL_G_REF 189
/* 190 */
/* 191 */
/* 192 */
#define TEGRA210_CLK_SDMMC_LEGACY 193
#define TEGRA210_CLK_NVDEC 194
#define TEGRA210_CLK_NVJPG 195
/* 196 */
#define TEGRA210_CLK_DMIC3 197
#define TEGRA210_CLK_APE 198
/* 199 */
/* 200 */
/* 201 */
#define TEGRA210_CLK_MAUD 202
/* 203 */
/* 204 */
/* 205 */
#define TEGRA210_CLK_TSECB 206
#define TEGRA210_CLK_DPAUX1 207
#define TEGRA210_CLK_VI_I2C 208
#define TEGRA210_CLK_HSIC_TRK 209
#define TEGRA210_CLK_USB2_TRK 210
#define TEGRA210_CLK_QSPI 211
#define TEGRA210_CLK_UARTAPE 212
/* 213 */
/* 214 */
/* 215 */
/* 216 */
/* 217 */
/* 218 */
#define TEGRA210_CLK_NVENC 219
/* 220 */
/* 221 */
#define TEGRA210_CLK_SOR_SAFE 222
#define TEGRA210_CLK_PLL_P_OUT_CPU 223
#define TEGRA210_CLK_UARTB 224
#define TEGRA210_CLK_VFIR 225
#define TEGRA210_CLK_SPDIF_IN 226
#define TEGRA210_CLK_SPDIF_OUT 227
#define TEGRA210_CLK_VI 228
#define TEGRA210_CLK_VI_SENSOR 229
#define TEGRA210_CLK_FUSE 230
#define TEGRA210_CLK_FUSE_BURN 231
#define TEGRA210_CLK_CLK_32K 232
#define TEGRA210_CLK_CLK_M 233
#define TEGRA210_CLK_CLK_M_DIV2 234
#define TEGRA210_CLK_CLK_M_DIV4 235
#define TEGRA210_CLK_PLL_REF 236
#define TEGRA210_CLK_PLL_C 237
#define TEGRA210_CLK_PLL_C_OUT1 238
#define TEGRA210_CLK_PLL_C2 239
#define TEGRA210_CLK_PLL_C3 240
#define TEGRA210_CLK_PLL_M 241
#define TEGRA210_CLK_PLL_M_OUT1 242
#define TEGRA210_CLK_PLL_P 243
#define TEGRA210_CLK_PLL_P_OUT1 244
#define TEGRA210_CLK_PLL_P_OUT2 245
#define TEGRA210_CLK_PLL_P_OUT3 246
#define TEGRA210_CLK_PLL_P_OUT4 247
#define TEGRA210_CLK_PLL_A 248
#define TEGRA210_CLK_PLL_A_OUT0 249
#define TEGRA210_CLK_PLL_D 250
#define TEGRA210_CLK_PLL_D_OUT0 251
#define TEGRA210_CLK_PLL_D2 252
#define TEGRA210_CLK_PLL_D2_OUT0 253
#define TEGRA210_CLK_PLL_U 254
#define TEGRA210_CLK_PLL_U_480M 255
#define TEGRA210_CLK_PLL_U_60M 256
#define TEGRA210_CLK_PLL_U_48M 257
/* 258 */
#define TEGRA210_CLK_PLL_X 259
#define TEGRA210_CLK_PLL_X_OUT0 260
#define TEGRA210_CLK_PLL_RE_VCO 261
#define TEGRA210_CLK_PLL_RE_OUT 262
#define TEGRA210_CLK_PLL_E 263
#define TEGRA210_CLK_SPDIF_IN_SYNC 264
#define TEGRA210_CLK_I2S0_SYNC 265
#define TEGRA210_CLK_I2S1_SYNC 266
#define TEGRA210_CLK_I2S2_SYNC 267
#define TEGRA210_CLK_I2S3_SYNC 268
#define TEGRA210_CLK_I2S4_SYNC 269
#define TEGRA210_CLK_VIMCLK_SYNC 270
#define TEGRA210_CLK_AUDIO0 271
#define TEGRA210_CLK_AUDIO1 272
#define TEGRA210_CLK_AUDIO2 273
#define TEGRA210_CLK_AUDIO3 274
#define TEGRA210_CLK_AUDIO4 275
#define TEGRA210_CLK_SPDIF 276
#define TEGRA210_CLK_CLK_OUT_1 277
#define TEGRA210_CLK_CLK_OUT_2 278
#define TEGRA210_CLK_CLK_OUT_3 279
#define TEGRA210_CLK_BLINK 280
/* 281 */
/* 282 */
/* 283 */
#define TEGRA210_CLK_XUSB_HOST_SRC 284
#define TEGRA210_CLK_XUSB_FALCON_SRC 285
#define TEGRA210_CLK_XUSB_FS_SRC 286
#define TEGRA210_CLK_XUSB_SS_SRC 287
#define TEGRA210_CLK_XUSB_DEV_SRC 288
#define TEGRA210_CLK_XUSB_DEV 289
#define TEGRA210_CLK_XUSB_HS_SRC 290
#define TEGRA210_CLK_SCLK 291
#define TEGRA210_CLK_HCLK 292
#define TEGRA210_CLK_PCLK 293
#define TEGRA210_CLK_CCLK_G 294
#define TEGRA210_CLK_CCLK_LP 295
#define TEGRA210_CLK_DFLL_REF 296
#define TEGRA210_CLK_DFLL_SOC 297
#define TEGRA210_CLK_VI_SENSOR2 298
#define TEGRA210_CLK_PLL_P_OUT5 299
#define TEGRA210_CLK_CML0 300
#define TEGRA210_CLK_CML1 301
#define TEGRA210_CLK_PLL_C4 302
#define TEGRA210_CLK_PLL_DP 303
#define TEGRA210_CLK_PLL_E_MUX 304
#define TEGRA210_CLK_PLL_MB 305
#define TEGRA210_CLK_PLL_A1 306
#define TEGRA210_CLK_PLL_D_DSI_OUT 307
#define TEGRA210_CLK_PLL_C4_OUT0 308
#define TEGRA210_CLK_PLL_C4_OUT1 309
#define TEGRA210_CLK_PLL_C4_OUT2 310
#define TEGRA210_CLK_PLL_C4_OUT3 311
#define TEGRA210_CLK_PLL_U_OUT 312
#define TEGRA210_CLK_PLL_U_OUT1 313
#define TEGRA210_CLK_PLL_U_OUT2 314
#define TEGRA210_CLK_USB2_HSIC_TRK 315
#define TEGRA210_CLK_PLL_P_OUT_HSIO 316
#define TEGRA210_CLK_PLL_P_OUT_XUSB 317
#define TEGRA210_CLK_XUSB_SSP_SRC 318
/* 319 */
/* 320 */
/* 321 */
/* 322 */
/* 323 */
/* 324 */
/* 325 */
/* 326 */
/* 327 */
/* 328 */
/* 329 */
/* 330 */
/* 331 */
/* 332 */
/* 333 */
/* 334 */
/* 335 */
/* 336 */
/* 337 */
/* 338 */
/* 339 */
/* 340 */
/* 341 */
/* 342 */
/* 343 */
/* 344 */
/* 345 */
/* 346 */
/* 347 */
/* 348 */
/* 349 */
#define TEGRA210_CLK_AUDIO0_MUX 350
#define TEGRA210_CLK_AUDIO1_MUX 351
#define TEGRA210_CLK_AUDIO2_MUX 352
#define TEGRA210_CLK_AUDIO3_MUX 353
#define TEGRA210_CLK_AUDIO4_MUX 354
#define TEGRA210_CLK_SPDIF_MUX 355
#define TEGRA210_CLK_CLK_OUT_1_MUX 356
#define TEGRA210_CLK_CLK_OUT_2_MUX 357
#define TEGRA210_CLK_CLK_OUT_3_MUX 358
#define TEGRA210_CLK_DSIA_MUX 359
#define TEGRA210_CLK_DSIB_MUX 360
#define TEGRA210_CLK_SOR0_LVDS 361
#define TEGRA210_CLK_XUSB_SS_DIV2 362
#define TEGRA210_CLK_PLL_M_UD 363
#define TEGRA210_CLK_PLL_C_UD 364
#define TEGRA210_CLK_SCLK_MUX 365
#define TEGRA210_CLK_CLK_MAX 366
#endif /* _DT_BINDINGS_CLOCK_TEGRA210_CAR_H */