drm/amdgpu: enable VCE clockgating in Polaris-10/11
VCE clocks are set to be disabled, when not in use. Signed-off-by: Maruthi Bayyavarapu <maruthi.bayyavarapu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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committed by
Alex Deucher

parent
ddbc2594cc
commit
ecc2cf7cc8
@@ -134,7 +134,7 @@ static void vce_v3_0_set_vce_sw_clock_gating(struct amdgpu_device *adev,
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accessible but the firmware will throttle the clocks on the
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fly as necessary.
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*/
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if (gated) {
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if (!gated) {
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data = RREG32(mmVCE_CLOCK_GATING_B);
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data |= 0x1ff;
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data &= ~0xef0000;
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@@ -937,12 +937,14 @@ static int vi_common_early_init(void *handle)
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adev->external_rev_id = adev->rev_id + 0x14;
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break;
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case CHIP_POLARIS11:
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adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG;
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adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG |
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AMD_CG_SUPPORT_VCE_MGCG;
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adev->pg_flags = 0;
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adev->external_rev_id = adev->rev_id + 0x5A;
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break;
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case CHIP_POLARIS10:
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adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG;
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adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG |
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AMD_CG_SUPPORT_VCE_MGCG;
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adev->pg_flags = 0;
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adev->external_rev_id = adev->rev_id + 0x50;
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break;
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