Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM SoC driver updates from Olof Johansson: "Various driver updates for platforms: - A larger set of work on Tegra 2/3 around memory controller and regulator features, some fuse cleanups, etc.. - MMP platform drivers, in particular for USB PHY, and other smaller additions. - Samsung Exynos 5422 driver for DMC (dynamic memory configuration), and ASV (adaptive voltage), allowing the platform to run at more optimal operating points. - Misc refactorings and support for RZ/G2N and R8A774B1 from Renesas - Clock/reset control driver for TI/OMAP - Meson-A1 reset controller support - Qualcomm sdm845 and sda845 SoC IDs for socinfo" * tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (150 commits) firmware: arm_scmi: Fix doorbell ring logic for !CONFIG_64BIT soc: fsl: add RCPM driver dt-bindings: fsl: rcpm: Add 'little-endian' and update Chassis definition memory: tegra: Consolidate registers definition into common header memory: tegra: Ensure timing control debug features are disabled memory: tegra: Introduce Tegra30 EMC driver memory: tegra: Do not handle error from wait_for_completion_timeout() memory: tegra: Increase handshake timeout on Tegra20 memory: tegra: Print a brief info message about EMC timings memory: tegra: Pre-configure debug register on Tegra20 memory: tegra: Include io.h instead of iopoll.h memory: tegra: Adapt for Tegra20 clock driver changes memory: tegra: Don't set EMC rate to maximum on probe for Tegra20 memory: tegra: Add gr2d and gr3d to DRM IOMMU group memory: tegra: Set DMA mask based on supported address bits soc: at91: Add Atmel SFR SN (Serial Number) support memory: atmel-ebi: switch to SPDX license identifiers memory: atmel-ebi: move NUM_CS definition inside EBI driver soc: mediatek: Refactor bus protection control soc: mediatek: Refactor sram control ...
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@@ -16,11 +16,14 @@ enum {
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struct meson_sm_firmware;
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int meson_sm_call(unsigned int cmd_index, u32 *ret, u32 arg0, u32 arg1,
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u32 arg2, u32 arg3, u32 arg4);
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int meson_sm_call_write(void *buffer, unsigned int b_size, unsigned int cmd_index,
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u32 arg0, u32 arg1, u32 arg2, u32 arg3, u32 arg4);
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int meson_sm_call_read(void *buffer, unsigned int bsize, unsigned int cmd_index,
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u32 arg0, u32 arg1, u32 arg2, u32 arg3, u32 arg4);
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int meson_sm_call(struct meson_sm_firmware *fw, unsigned int cmd_index,
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u32 *ret, u32 arg0, u32 arg1, u32 arg2, u32 arg3, u32 arg4);
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int meson_sm_call_write(struct meson_sm_firmware *fw, void *buffer,
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unsigned int b_size, unsigned int cmd_index, u32 arg0,
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u32 arg1, u32 arg2, u32 arg3, u32 arg4);
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int meson_sm_call_read(struct meson_sm_firmware *fw, void *buffer,
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unsigned int bsize, unsigned int cmd_index, u32 arg0,
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u32 arg1, u32 arg2, u32 arg3, u32 arg4);
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struct meson_sm_firmware *meson_sm_get(struct device_node *firmware_node);
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#endif /* _MESON_SM_FW_H_ */
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@@ -2,7 +2,7 @@
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/*
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* Xilinx Zynq MPSoC Firmware layer
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*
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* Copyright (C) 2014-2018 Xilinx
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* Copyright (C) 2014-2019 Xilinx
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*
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* Michal Simek <michal.simek@xilinx.com>
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* Davorin Mista <davorin.mista@aggios.com>
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@@ -46,6 +46,7 @@
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#define ZYNQMP_PM_CAPABILITY_ACCESS 0x1U
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#define ZYNQMP_PM_CAPABILITY_CONTEXT 0x2U
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#define ZYNQMP_PM_CAPABILITY_WAKEUP 0x4U
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#define ZYNQMP_PM_CAPABILITY_UNUSABLE 0x8U
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/*
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* Firmware FPGA Manager flags
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