powerpc: Convert to new irq_* function names
Scripted with coccinelle. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
This commit is contained in:
@@ -104,7 +104,7 @@ static int cpm_pic_host_map(struct irq_host *h, unsigned int virq,
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pr_debug("cpm_pic_host_map(%d, 0x%lx)\n", virq, hw);
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irq_set_status_flags(virq, IRQ_LEVEL);
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set_irq_chip_and_handler(virq, &cpm_pic, handle_fasteoi_irq);
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irq_set_chip_and_handler(virq, &cpm_pic, handle_fasteoi_irq);
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return 0;
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}
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@@ -157,9 +157,9 @@ static int cpm2_set_irq_type(struct irq_data *d, unsigned int flow_type)
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irqd_set_trigger_type(d, flow_type);
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if (flow_type & IRQ_TYPE_LEVEL_LOW)
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__set_irq_handler_unlocked(d->irq, handle_level_irq);
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__irq_set_handler_locked(d->irq, handle_level_irq);
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else
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__set_irq_handler_unlocked(d->irq, handle_edge_irq);
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__irq_set_handler_locked(d->irq, handle_edge_irq);
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/* internal IRQ senses are LEVEL_LOW
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* EXT IRQ and Port C IRQ senses are programmable
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@@ -220,7 +220,7 @@ static int cpm2_pic_host_map(struct irq_host *h, unsigned int virq,
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pr_debug("cpm2_pic_host_map(%d, 0x%lx)\n", virq, hw);
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irq_set_status_flags(virq, IRQ_LEVEL);
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set_irq_chip_and_handler(virq, &cpm2_pic, handle_level_irq);
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irq_set_chip_and_handler(virq, &cpm2_pic, handle_level_irq);
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return 0;
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}
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@@ -66,8 +66,8 @@ static int fsl_msi_host_map(struct irq_host *h, unsigned int virq,
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irq_set_status_flags(virq, IRQ_TYPE_EDGE_FALLING);
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set_irq_chip_data(virq, msi_data);
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set_irq_chip_and_handler(virq, chip, handle_edge_irq);
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irq_set_chip_data(virq, msi_data);
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irq_set_chip_and_handler(virq, chip, handle_edge_irq);
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return 0;
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}
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@@ -110,8 +110,8 @@ static void fsl_teardown_msi_irqs(struct pci_dev *pdev)
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list_for_each_entry(entry, &pdev->msi_list, list) {
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if (entry->irq == NO_IRQ)
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continue;
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msi_data = get_irq_data(entry->irq);
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set_irq_msi(entry->irq, NULL);
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msi_data = irq_get_handler_data(entry->irq);
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irq_set_msi_desc(entry->irq, NULL);
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msi_bitmap_free_hwirqs(&msi_data->bitmap,
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virq_to_hw(entry->irq), 1);
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irq_dispose_mapping(entry->irq);
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@@ -168,8 +168,8 @@ static int fsl_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
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rc = -ENOSPC;
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goto out_free;
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}
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set_irq_data(virq, msi_data);
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set_irq_msi(virq, entry);
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irq_set_handler_data(virq, msi_data);
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irq_set_msi_desc(virq, entry);
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fsl_compose_msi_msg(pdev, hwirq, &msg, msi_data);
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write_msi_msg(virq, &msg);
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@@ -193,7 +193,7 @@ static void fsl_msi_cascade(unsigned int irq, struct irq_desc *desc)
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u32 have_shift = 0;
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struct fsl_msi_cascade_data *cascade_data;
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cascade_data = (struct fsl_msi_cascade_data *)get_irq_data(irq);
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cascade_data = (struct fsl_msi_cascade_data *)irq_get_handler_data(irq);
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msi_data = cascade_data->msi_data;
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raw_spin_lock(&desc->lock);
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@@ -262,7 +262,7 @@ static int fsl_of_msi_remove(struct platform_device *ofdev)
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for (i = 0; i < NR_MSI_REG; i++) {
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virq = msi->msi_virqs[i];
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if (virq != NO_IRQ) {
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cascade_data = get_irq_data(virq);
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cascade_data = irq_get_handler_data(virq);
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kfree(cascade_data);
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irq_dispose_mapping(virq);
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}
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@@ -298,8 +298,8 @@ static int __devinit fsl_msi_setup_hwirq(struct fsl_msi *msi,
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msi->msi_virqs[irq_index] = virt_msir;
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cascade_data->index = offset + irq_index;
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cascade_data->msi_data = msi;
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set_irq_data(virt_msir, cascade_data);
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set_irq_chained_handler(virt_msir, fsl_msi_cascade);
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irq_set_handler_data(virt_msir, cascade_data);
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irq_set_chained_handler(virt_msir, fsl_msi_cascade);
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return 0;
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}
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@@ -181,7 +181,7 @@ static int i8259_host_map(struct irq_host *h, unsigned int virq,
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* be more cautious here but that works for now
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*/
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irq_set_status_flags(virq, IRQ_LEVEL);
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set_irq_chip_and_handler(virq, &i8259_pic, handle_level_irq);
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irq_set_chip_and_handler(virq, &i8259_pic, handle_level_irq);
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return 0;
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}
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@@ -191,7 +191,7 @@ static void i8259_host_unmap(struct irq_host *h, unsigned int virq)
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i8259_mask_irq(irq_get_irq_data(virq));
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/* remove chip and handler */
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set_irq_chip_and_handler(virq, NULL, NULL);
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irq_set_chip_and_handler(virq, NULL, NULL);
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/* Make sure it's completed */
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synchronize_irq(virq);
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@@ -685,11 +685,11 @@ static int ipic_host_map(struct irq_host *h, unsigned int virq,
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{
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struct ipic *ipic = h->host_data;
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set_irq_chip_data(virq, ipic);
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set_irq_chip_and_handler(virq, &ipic_level_irq_chip, handle_level_irq);
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irq_set_chip_data(virq, ipic);
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irq_set_chip_and_handler(virq, &ipic_level_irq_chip, handle_level_irq);
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/* Set default irq type */
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set_irq_type(virq, IRQ_TYPE_NONE);
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irq_set_irq_type(virq, IRQ_TYPE_NONE);
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return 0;
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}
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@@ -80,7 +80,7 @@ static int mpc8xx_set_irq_type(struct irq_data *d, unsigned int flow_type)
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if ((hw & 1) == 0) {
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siel |= (0x80000000 >> hw);
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out_be32(&siu_reg->sc_siel, siel);
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__set_irq_handler_unlocked(irq, handle_edge_irq);
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__irq_set_handler_locked(irq, handle_edge_irq);
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}
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}
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return 0;
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@@ -117,7 +117,7 @@ static int mpc8xx_pic_host_map(struct irq_host *h, unsigned int virq,
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pr_debug("mpc8xx_pic_host_map(%d, 0x%lx)\n", virq, hw);
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/* Set default irq handle */
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set_irq_chip_and_handler(virq, &mpc8xx_pic, handle_level_irq);
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irq_set_chip_and_handler(virq, &mpc8xx_pic, handle_level_irq);
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return 0;
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}
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@@ -145,7 +145,7 @@ static int mpc8xxx_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
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static void mpc8xxx_gpio_irq_cascade(unsigned int irq, struct irq_desc *desc)
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{
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struct mpc8xxx_gpio_chip *mpc8xxx_gc = get_irq_desc_data(desc);
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struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_desc_get_handler_data(desc);
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struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
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unsigned int mask;
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@@ -278,9 +278,9 @@ static int mpc8xxx_gpio_irq_map(struct irq_host *h, unsigned int virq,
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if (mpc8xxx_gc->of_dev_id_data)
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mpc8xxx_irq_chip.irq_set_type = mpc8xxx_gc->of_dev_id_data;
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set_irq_chip_data(virq, h->host_data);
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set_irq_chip_and_handler(virq, &mpc8xxx_irq_chip, handle_level_irq);
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set_irq_type(virq, IRQ_TYPE_NONE);
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irq_set_chip_data(virq, h->host_data);
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irq_set_chip_and_handler(virq, &mpc8xxx_irq_chip, handle_level_irq);
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irq_set_irq_type(virq, IRQ_TYPE_NONE);
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return 0;
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}
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@@ -369,8 +369,8 @@ static void __init mpc8xxx_add_controller(struct device_node *np)
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out_be32(mm_gc->regs + GPIO_IER, 0xffffffff);
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out_be32(mm_gc->regs + GPIO_IMR, 0);
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set_irq_data(hwirq, mpc8xxx_gc);
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set_irq_chained_handler(hwirq, mpc8xxx_gpio_irq_cascade);
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irq_set_handler_data(hwirq, mpc8xxx_gc);
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irq_set_chained_handler(hwirq, mpc8xxx_gpio_irq_cascade);
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skip_irq:
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return;
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@@ -615,7 +615,7 @@ static struct mpic *mpic_find(unsigned int irq)
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if (irq < NUM_ISA_INTERRUPTS)
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return NULL;
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return get_irq_chip_data(irq);
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return irq_get_chip_data(irq);
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}
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/* Determine if the linux irq is an IPI */
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@@ -649,7 +649,7 @@ static inline struct mpic * mpic_from_ipi(struct irq_data *d)
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/* Get the mpic structure from the irq number */
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static inline struct mpic * mpic_from_irq(unsigned int irq)
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{
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return get_irq_chip_data(irq);
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return irq_get_chip_data(irq);
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}
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/* Get the mpic structure from the irq data */
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@@ -978,8 +978,8 @@ static int mpic_host_map(struct irq_host *h, unsigned int virq,
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WARN_ON(!(mpic->flags & MPIC_PRIMARY));
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DBG("mpic: mapping as IPI\n");
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set_irq_chip_data(virq, mpic);
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set_irq_chip_and_handler(virq, &mpic->hc_ipi,
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irq_set_chip_data(virq, mpic);
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irq_set_chip_and_handler(virq, &mpic->hc_ipi,
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handle_percpu_irq);
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return 0;
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}
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@@ -1001,11 +1001,11 @@ static int mpic_host_map(struct irq_host *h, unsigned int virq,
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DBG("mpic: mapping to irq chip @%p\n", chip);
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set_irq_chip_data(virq, mpic);
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set_irq_chip_and_handler(virq, chip, handle_fasteoi_irq);
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irq_set_chip_data(virq, mpic);
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irq_set_chip_and_handler(virq, chip, handle_fasteoi_irq);
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/* Set default irq type */
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set_irq_type(virq, IRQ_TYPE_NONE);
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irq_set_irq_type(virq, IRQ_TYPE_NONE);
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/* If the MPIC was reset, then all vectors have already been
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* initialized. Otherwise, a per source lazy initialization
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@@ -81,7 +81,7 @@ static void pasemi_msi_teardown_msi_irqs(struct pci_dev *pdev)
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if (entry->irq == NO_IRQ)
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continue;
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set_irq_msi(entry->irq, NULL);
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irq_set_msi_desc(entry->irq, NULL);
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msi_bitmap_free_hwirqs(&msi_mpic->msi_bitmap,
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virq_to_hw(entry->irq), ALLOC_CHUNK);
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irq_dispose_mapping(entry->irq);
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@@ -131,9 +131,9 @@ static int pasemi_msi_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
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*/
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mpic_set_vector(virq, 0);
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set_irq_msi(virq, entry);
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set_irq_chip(virq, &mpic_pasemi_msi_chip);
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set_irq_type(virq, IRQ_TYPE_EDGE_RISING);
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irq_set_msi_desc(virq, entry);
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irq_set_chip(virq, &mpic_pasemi_msi_chip);
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irq_set_irq_type(virq, IRQ_TYPE_EDGE_RISING);
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pr_debug("pasemi_msi: allocated virq 0x%x (hw 0x%x) " \
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"addr 0x%x\n", virq, hwirq, msg.address_lo);
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@@ -129,7 +129,7 @@ static void u3msi_teardown_msi_irqs(struct pci_dev *pdev)
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if (entry->irq == NO_IRQ)
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continue;
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set_irq_msi(entry->irq, NULL);
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irq_set_msi_desc(entry->irq, NULL);
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msi_bitmap_free_hwirqs(&msi_mpic->msi_bitmap,
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virq_to_hw(entry->irq), 1);
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irq_dispose_mapping(entry->irq);
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@@ -166,9 +166,9 @@ static int u3msi_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
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return -ENOSPC;
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}
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set_irq_msi(virq, entry);
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set_irq_chip(virq, &mpic_u3msi_chip);
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set_irq_type(virq, IRQ_TYPE_EDGE_RISING);
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irq_set_msi_desc(virq, entry);
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irq_set_chip(virq, &mpic_u3msi_chip);
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irq_set_irq_type(virq, IRQ_TYPE_EDGE_RISING);
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pr_debug("u3msi: allocated virq 0x%x (hw 0x%x) addr 0x%lx\n",
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virq, hwirq, (unsigned long)addr);
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@@ -217,7 +217,8 @@ static int mv64x60_host_map(struct irq_host *h, unsigned int virq,
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level1 = (hwirq & MV64x60_LEVEL1_MASK) >> MV64x60_LEVEL1_OFFSET;
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BUG_ON(level1 > MV64x60_LEVEL1_GPP);
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set_irq_chip_and_handler(virq, mv64x60_chips[level1], handle_level_irq);
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irq_set_chip_and_handler(virq, mv64x60_chips[level1],
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handle_level_irq);
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return 0;
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}
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@@ -189,7 +189,7 @@ static inline void qe_ic_write(volatile __be32 __iomem * base, unsigned int reg
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static inline struct qe_ic *qe_ic_from_irq(unsigned int virq)
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{
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return get_irq_chip_data(virq);
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return irq_get_chip_data(virq);
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}
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static inline struct qe_ic *qe_ic_from_irq_data(struct irq_data *d)
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@@ -267,10 +267,10 @@ static int qe_ic_host_map(struct irq_host *h, unsigned int virq,
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/* Default chip */
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chip = &qe_ic->hc_irq;
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set_irq_chip_data(virq, qe_ic);
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irq_set_chip_data(virq, qe_ic);
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irq_set_status_flags(virq, IRQ_LEVEL);
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set_irq_chip_and_handler(virq, chip, handle_level_irq);
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irq_set_chip_and_handler(virq, chip, handle_level_irq);
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return 0;
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}
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@@ -386,13 +386,13 @@ void __init qe_ic_init(struct device_node *node, unsigned int flags,
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qe_ic_write(qe_ic->regs, QEIC_CICR, temp);
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set_irq_data(qe_ic->virq_low, qe_ic);
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set_irq_chained_handler(qe_ic->virq_low, low_handler);
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irq_set_handler_data(qe_ic->virq_low, qe_ic);
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irq_set_chained_handler(qe_ic->virq_low, low_handler);
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if (qe_ic->virq_high != NO_IRQ &&
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qe_ic->virq_high != qe_ic->virq_low) {
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set_irq_data(qe_ic->virq_high, qe_ic);
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set_irq_chained_handler(qe_ic->virq_high, high_handler);
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irq_set_handler_data(qe_ic->virq_high, qe_ic);
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irq_set_chained_handler(qe_ic->virq_high, high_handler);
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}
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}
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@@ -392,7 +392,7 @@ static int pci_irq_host_map(struct irq_host *h, unsigned int virq,
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if ((virq >= 1) && (virq <= 4)){
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irq = virq + IRQ_PCI_INTAD_BASE - 1;
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irq_set_status_flags(irq, IRQ_LEVEL);
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set_irq_chip(irq, &tsi108_pci_irq);
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irq_set_chip(irq, &tsi108_pci_irq);
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}
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return 0;
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}
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@@ -431,7 +431,7 @@ void __init tsi108_pci_int_init(struct device_node *node)
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void tsi108_irq_cascade(unsigned int irq, struct irq_desc *desc)
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{
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struct irq_chip *chip = get_irq_desc_chip(desc);
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struct irq_chip *chip = irq_desc_get_chip(desc);
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unsigned int cascade_irq = get_pci_source();
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if (cascade_irq != NO_IRQ)
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@@ -182,13 +182,13 @@ static int uic_host_map(struct irq_host *h, unsigned int virq,
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{
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struct uic *uic = h->host_data;
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set_irq_chip_data(virq, uic);
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irq_set_chip_data(virq, uic);
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/* Despite the name, handle_level_irq() works for both level
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* and edge irqs on UIC. FIXME: check this is correct */
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set_irq_chip_and_handler(virq, &uic_irq_chip, handle_level_irq);
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irq_set_chip_and_handler(virq, &uic_irq_chip, handle_level_irq);
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/* Set default irq type */
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set_irq_type(virq, IRQ_TYPE_NONE);
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irq_set_irq_type(virq, IRQ_TYPE_NONE);
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return 0;
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}
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@@ -212,9 +212,9 @@ static struct irq_host_ops uic_host_ops = {
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void uic_irq_cascade(unsigned int virq, struct irq_desc *desc)
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{
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struct irq_chip *chip = get_irq_desc_chip(desc);
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struct irq_chip *chip = irq_desc_get_chip(desc);
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struct irq_data *idata = irq_desc_get_irq_data(desc);
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struct uic *uic = get_irq_data(virq);
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struct uic *uic = irq_get_handler_data(virq);
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u32 msr;
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int src;
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int subvirq;
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@@ -329,8 +329,8 @@ void __init uic_init_tree(void)
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cascade_virq = irq_of_parse_and_map(np, 0);
|
||||
|
||||
set_irq_data(cascade_virq, uic);
|
||||
set_irq_chained_handler(cascade_virq, uic_irq_cascade);
|
||||
irq_set_handler_data(cascade_virq, uic);
|
||||
irq_set_chained_handler(cascade_virq, uic_irq_cascade);
|
||||
|
||||
/* FIXME: setup critical cascade?? */
|
||||
}
|
||||
|
@@ -164,15 +164,15 @@ static int xilinx_intc_xlate(struct irq_host *h, struct device_node *ct,
|
||||
static int xilinx_intc_map(struct irq_host *h, unsigned int virq,
|
||||
irq_hw_number_t irq)
|
||||
{
|
||||
set_irq_chip_data(virq, h->host_data);
|
||||
irq_set_chip_data(virq, h->host_data);
|
||||
|
||||
if (xilinx_intc_typetable[irq] == IRQ_TYPE_LEVEL_HIGH ||
|
||||
xilinx_intc_typetable[irq] == IRQ_TYPE_LEVEL_LOW) {
|
||||
set_irq_chip_and_handler(virq, &xilinx_intc_level_irqchip,
|
||||
handle_level_irq);
|
||||
irq_set_chip_and_handler(virq, &xilinx_intc_level_irqchip,
|
||||
handle_level_irq);
|
||||
} else {
|
||||
set_irq_chip_and_handler(virq, &xilinx_intc_edge_irqchip,
|
||||
handle_edge_irq);
|
||||
irq_set_chip_and_handler(virq, &xilinx_intc_edge_irqchip,
|
||||
handle_edge_irq);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
@@ -223,7 +223,7 @@ int xilinx_intc_get_irq(void)
|
||||
*/
|
||||
static void xilinx_i8259_cascade(unsigned int irq, struct irq_desc *desc)
|
||||
{
|
||||
struct irq_chip *chip = get_irq_desc_chip(desc);
|
||||
struct irq_chip *chip = irq_desc_get_chip(desc);
|
||||
unsigned int cascade_irq = i8259_irq();
|
||||
|
||||
if (cascade_irq)
|
||||
@@ -250,7 +250,7 @@ static void __init xilinx_i8259_setup_cascade(void)
|
||||
}
|
||||
|
||||
i8259_init(cascade_node, 0);
|
||||
set_irq_chained_handler(cascade_irq, xilinx_i8259_cascade);
|
||||
irq_set_chained_handler(cascade_irq, xilinx_i8259_cascade);
|
||||
|
||||
/* Program irq 7 (usb/audio), 14/15 (ide) to level sensitive */
|
||||
/* This looks like a dirty hack to me --gcl */
|
||||
|
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