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clk: tegra: move fields to tegra_clk_pll_params

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Move some fields related to the PLL HW description to the tegra_clk_pll_params.
This allows some PLL code to be moved to common files later.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
This commit is contained in:
Peter De Schrijver
2013-10-04 17:28:34 +03:00
parent 8e9cc80aa3
commit ebe142b2ad
5 changed files with 175 additions and 177 deletions
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44
drivers/clk/tegra/clk-tegra20.c
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@@ -360,6 +360,8 @@ static struct tegra_clk_pll_params pll_c_params = {
.lock_mask = PLL_BASE_LOCK,
.lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
.lock_delay = 300,
.freq_table = pll_c_freq_table,
.flags = TEGRA_PLL_HAS_CPCON,
};
static struct tegra_clk_pll_params pll_m_params = {
@@ -374,6 +376,8 @@ static struct tegra_clk_pll_params pll_m_params = {
.lock_mask = PLL_BASE_LOCK,
.lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
.lock_delay = 300,
.freq_table = pll_m_freq_table,
.flags = TEGRA_PLL_HAS_CPCON,
};
static struct tegra_clk_pll_params pll_p_params = {
@@ -388,6 +392,9 @@ static struct tegra_clk_pll_params pll_p_params = {
.lock_mask = PLL_BASE_LOCK,
.lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
.lock_delay = 300,
.freq_table = pll_p_freq_table,
.flags = TEGRA_PLL_FIXED | TEGRA_PLL_HAS_CPCON,
.fixed_rate = 216000000,
};
static struct tegra_clk_pll_params pll_a_params = {
@@ -402,6 +409,8 @@ static struct tegra_clk_pll_params pll_a_params = {
.lock_mask = PLL_BASE_LOCK,
.lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
.lock_delay = 300,
.freq_table = pll_a_freq_table,
.flags = TEGRA_PLL_HAS_CPCON,
};
static struct tegra_clk_pll_params pll_d_params = {
@@ -416,6 +425,8 @@ static struct tegra_clk_pll_params pll_d_params = {
.lock_mask = PLL_BASE_LOCK,
.lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
.lock_delay = 1000,
.freq_table = pll_d_freq_table,
.flags = TEGRA_PLL_HAS_CPCON,
};
static struct pdiv_map pllu_p[] = {
@@ -437,6 +448,8 @@ static struct tegra_clk_pll_params pll_u_params = {
.lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
.lock_delay = 1000,
.pdiv_tohw = pllu_p,
.freq_table = pll_u_freq_table,
.flags = TEGRA_PLLU | TEGRA_PLL_HAS_CPCON,
};
static struct tegra_clk_pll_params pll_x_params = {
@@ -451,6 +464,8 @@ static struct tegra_clk_pll_params pll_x_params = {
.lock_mask = PLL_BASE_LOCK,
.lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
.lock_delay = 300,
.freq_table = pll_x_freq_table,
.flags = TEGRA_PLL_HAS_CPCON,
};
static struct tegra_clk_pll_params pll_e_params = {
@@ -465,6 +480,9 @@ static struct tegra_clk_pll_params pll_e_params = {
.lock_mask = PLLE_MISC_LOCK,
.lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
.lock_delay = 0,
.freq_table = pll_e_freq_table,
.flags = TEGRA_PLL_FIXED,
.fixed_rate = 100000000,
};
static unsigned long tegra20_clk_measure_input_freq(void)
@@ -526,8 +544,7 @@ static void tegra20_pll_init(void)
/* PLLC */
clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, NULL, 0,
0, &pll_c_params, TEGRA_PLL_HAS_CPCON,
pll_c_freq_table, NULL);
&pll_c_params, NULL);
clk_register_clkdev(clk, "pll_c", NULL);
clks[pll_c] = clk;
@@ -543,8 +560,7 @@ static void tegra20_pll_init(void)
/* PLLP */
clk = tegra_clk_register_pll("pll_p", "pll_ref", clk_base, NULL, 0,
216000000, &pll_p_params, TEGRA_PLL_FIXED |
TEGRA_PLL_HAS_CPCON, pll_p_freq_table, NULL);
&pll_p_params, NULL);
clk_register_clkdev(clk, "pll_p", NULL);
clks[pll_p] = clk;
@@ -598,9 +614,8 @@ static void tegra20_pll_init(void)
/* PLLM */
clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, NULL,
CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE, 0,
&pll_m_params, TEGRA_PLL_HAS_CPCON,
pll_m_freq_table, NULL);
CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE,
&pll_m_params, NULL);
clk_register_clkdev(clk, "pll_m", NULL);
clks[pll_m] = clk;
@@ -616,22 +631,19 @@ static void tegra20_pll_init(void)
/* PLLX */
clk = tegra_clk_register_pll("pll_x", "pll_ref", clk_base, NULL, 0,
0, &pll_x_params, TEGRA_PLL_HAS_CPCON,
pll_x_freq_table, NULL);
&pll_x_params, NULL);
clk_register_clkdev(clk, "pll_x", NULL);
clks[pll_x] = clk;
/* PLLU */
clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, NULL, 0,
0, &pll_u_params, TEGRA_PLLU | TEGRA_PLL_HAS_CPCON,
pll_u_freq_table, NULL);
&pll_u_params, NULL);
clk_register_clkdev(clk, "pll_u", NULL);
clks[pll_u] = clk;
/* PLLD */
clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, NULL, 0,
0, &pll_d_params, TEGRA_PLL_HAS_CPCON,
pll_d_freq_table, NULL);
&pll_d_params, NULL);
clk_register_clkdev(clk, "pll_d", NULL);
clks[pll_d] = clk;
@@ -643,8 +655,7 @@ static void tegra20_pll_init(void)
/* PLLA */
clk = tegra_clk_register_pll("pll_a", "pll_p_out1", clk_base, NULL, 0,
0, &pll_a_params, TEGRA_PLL_HAS_CPCON,
pll_a_freq_table, NULL);
&pll_a_params, NULL);
clk_register_clkdev(clk, "pll_a", NULL);
clks[pll_a] = clk;
@@ -660,8 +671,7 @@ static void tegra20_pll_init(void)
/* PLLE */
clk = tegra_clk_register_plle("pll_e", "pll_ref", clk_base, pmc_base,
0, 100000000, &pll_e_params,
0, pll_e_freq_table, NULL);
0, &pll_e_params, NULL);
clk_register_clkdev(clk, "pll_e", NULL);
clks[pll_e] = clk;
}