drm/nouveau: port all engines to new engine module format
This is a HUGE commit, but it's not nearly as bad as it looks - any problems can be isolated to a particular chipset and engine combination. It was simply too difficult to port each one at a time, the compat layers are *already* ridiculous. Most of the changes here are simply to the glue, the process for each of the engine modules was to start with a standard skeleton and copy+paste the old code into the appropriate places, fixing up variable names etc as needed. v2: Marcin Slusarz <marcin.slusarz@gmail.com> - fix find/replace bug in license header v3: Ben Skeggs <bskeggs@redhat.com> - bump indirect pushbuf size to 8KiB, 4KiB barely enough for userspace and left no space for kernel's requirements during GEM pushbuf submission. - fix duplicate assignments noticed by clang v4: Marcin Slusarz <marcin.slusarz@gmail.com> - add sparse annotations to nv04_fifo_pause/nv04_fifo_start - use ioread32_native/iowrite32_native for fifo control registers v5: Ben Skeggs <bskeggs@redhat.com> - rebase on v3.6-rc4, modified to keep copy engine fix intact - nv10/fence: unmap fence bo before destroying - fixed fermi regression when using nvidia gr fuc - fixed typo in supported dma_mask checking Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
@@ -22,13 +22,15 @@
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* Authors: Ben Skeggs
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*/
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#include "drmP.h"
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#include "nouveau_drv.h"
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#include "nouveau_dma.h"
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#include <core/object.h>
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#include <core/client.h>
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#include <core/class.h>
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#include <engine/fifo.h>
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#include <core/ramht.h>
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#include "nouveau_drm.h"
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#include "nouveau_dma.h"
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#include "nouveau_fence.h"
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#include "nv50_display.h"
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struct nvc0_fence_priv {
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struct nouveau_fence_priv base;
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@@ -54,7 +56,8 @@ nvc0_fence_emit(struct nouveau_fence *fence)
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{
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struct nouveau_channel *chan = fence->channel;
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struct nvc0_fence_chan *fctx = chan->fence;
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u64 addr = fctx->vma.offset + chan->id * 16;
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struct nouveau_fifo_chan *fifo = (void *)chan->object;
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u64 addr = fctx->vma.offset + fifo->chid * 16;
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int ret;
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ret = RING_SPACE(chan, 5);
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@@ -75,7 +78,8 @@ nvc0_fence_sync(struct nouveau_fence *fence,
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struct nouveau_channel *prev, struct nouveau_channel *chan)
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{
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struct nvc0_fence_chan *fctx = chan->fence;
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u64 addr = fctx->vma.offset + prev->id * 16;
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struct nouveau_fifo_chan *fifo = (void *)prev->object;
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u64 addr = fctx->vma.offset + fifo->chid * 16;
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int ret;
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ret = RING_SPACE(chan, 5);
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@@ -95,31 +99,29 @@ nvc0_fence_sync(struct nouveau_fence *fence,
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static u32
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nvc0_fence_read(struct nouveau_channel *chan)
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{
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struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
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struct nvc0_fence_priv *priv = dev_priv->fence.func;
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return nouveau_bo_rd32(priv->bo, chan->id * 16/4);
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struct nouveau_fifo_chan *fifo = (void *)chan->object;
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struct nvc0_fence_priv *priv = chan->drm->fence;
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return nouveau_bo_rd32(priv->bo, fifo->chid * 16/4);
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}
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static void
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nvc0_fence_context_del(struct nouveau_channel *chan)
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{
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struct drm_device *dev = chan->dev;
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nvc0_fence_priv *priv = dev_priv->fence.func;
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struct drm_device *dev = chan->drm->dev;
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struct nvc0_fence_priv *priv = chan->drm->fence;
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struct nvc0_fence_chan *fctx = chan->fence;
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int i;
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if (dev_priv->card_type >= NV_D0) {
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if (nv_device(chan->drm->device)->card_type >= NV_D0) {
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for (i = 0; i < dev->mode_config.num_crtc; i++) {
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struct nouveau_bo *bo = nvd0_display_crtc_sema(dev, i);
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struct nouveau_bo *bo = nvd0sema(dev, i);
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nouveau_bo_vma_del(bo, &fctx->dispc_vma[i]);
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}
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} else
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if (dev_priv->card_type >= NV_50) {
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struct nv50_display *disp = nv50_display(dev);
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if (nv_device(chan->drm->device)->card_type >= NV_50) {
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for (i = 0; i < dev->mode_config.num_crtc; i++) {
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struct nv50_display_crtc *dispc = &disp->crtc[i];
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nouveau_bo_vma_del(dispc->sem.bo, &fctx->dispc_vma[i]);
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struct nouveau_bo *bo = nv50sema(dev, i);
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nouveau_bo_vma_del(bo, &fctx->dispc_vma[i]);
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}
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}
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@@ -132,9 +134,9 @@ nvc0_fence_context_del(struct nouveau_channel *chan)
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static int
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nvc0_fence_context_new(struct nouveau_channel *chan)
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{
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struct drm_device *dev = chan->dev;
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nvc0_fence_priv *priv = dev_priv->fence.func;
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struct nouveau_fifo_chan *fifo = (void *)chan->object;
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struct nouveau_client *client = nouveau_client(fifo);
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struct nvc0_fence_priv *priv = chan->drm->fence;
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struct nvc0_fence_chan *fctx;
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int ret, i;
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@@ -144,36 +146,35 @@ nvc0_fence_context_new(struct nouveau_channel *chan)
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nouveau_fence_context_new(&fctx->base);
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ret = nouveau_bo_vma_add(priv->bo, chan->vm, &fctx->vma);
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ret = nouveau_bo_vma_add(priv->bo, client->vm, &fctx->vma);
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if (ret)
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nvc0_fence_context_del(chan);
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/* map display semaphore buffers into channel's vm */
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for (i = 0; !ret && i < dev->mode_config.num_crtc; i++) {
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for (i = 0; !ret && i < chan->drm->dev->mode_config.num_crtc; i++) {
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struct nouveau_bo *bo;
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if (dev_priv->card_type >= NV_D0)
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bo = nvd0_display_crtc_sema(dev, i);
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if (nv_device(chan->drm->device)->card_type >= NV_D0)
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bo = nvd0sema(chan->drm->dev, i);
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else
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bo = nv50_display(dev)->crtc[i].sem.bo;
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bo = nv50sema(chan->drm->dev, i);
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ret = nouveau_bo_vma_add(bo, chan->vm, &fctx->dispc_vma[i]);
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ret = nouveau_bo_vma_add(bo, client->vm, &fctx->dispc_vma[i]);
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}
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nouveau_bo_wr32(priv->bo, chan->id * 16/4, 0x00000000);
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nouveau_bo_wr32(priv->bo, fifo->chid * 16/4, 0x00000000);
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return ret;
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}
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static bool
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nvc0_fence_suspend(struct drm_device *dev)
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nvc0_fence_suspend(struct nouveau_drm *drm)
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{
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struct nouveau_fifo_priv *pfifo = nv_engine(dev, NVOBJ_ENGINE_FIFO);
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nvc0_fence_priv *priv = dev_priv->fence.func;
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struct nouveau_fifo *pfifo = nouveau_fifo(drm->device);
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struct nvc0_fence_priv *priv = drm->fence;
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int i;
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priv->suspend = vmalloc(pfifo->channels * sizeof(u32));
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priv->suspend = vmalloc((pfifo->max + 1) * sizeof(u32));
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if (priv->suspend) {
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for (i = 0; i < pfifo->channels; i++)
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for (i = 0; i <= pfifo->max; i++)
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priv->suspend[i] = nouveau_bo_rd32(priv->bo, i);
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}
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@@ -181,15 +182,14 @@ nvc0_fence_suspend(struct drm_device *dev)
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}
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static void
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nvc0_fence_resume(struct drm_device *dev)
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nvc0_fence_resume(struct nouveau_drm *drm)
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{
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struct nouveau_fifo_priv *pfifo = nv_engine(dev, NVOBJ_ENGINE_FIFO);
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nvc0_fence_priv *priv = dev_priv->fence.func;
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struct nouveau_fifo *pfifo = nouveau_fifo(drm->device);
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struct nvc0_fence_priv *priv = drm->fence;
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int i;
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if (priv->suspend) {
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for (i = 0; i < pfifo->channels; i++)
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for (i = 0; i <= pfifo->max; i++)
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nouveau_bo_wr32(priv->bo, i, priv->suspend[i]);
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vfree(priv->suspend);
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priv->suspend = NULL;
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@@ -197,26 +197,23 @@ nvc0_fence_resume(struct drm_device *dev)
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}
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static void
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nvc0_fence_destroy(struct drm_device *dev)
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nvc0_fence_destroy(struct nouveau_drm *drm)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nvc0_fence_priv *priv = dev_priv->fence.func;
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struct nvc0_fence_priv *priv = drm->fence;
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nouveau_bo_unmap(priv->bo);
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nouveau_bo_ref(NULL, &priv->bo);
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dev_priv->fence.func = NULL;
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drm->fence = NULL;
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kfree(priv);
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}
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int
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nvc0_fence_create(struct drm_device *dev)
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nvc0_fence_create(struct nouveau_drm *drm)
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{
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struct nouveau_fifo_priv *pfifo = nv_engine(dev, NVOBJ_ENGINE_FIFO);
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_fifo *pfifo = nouveau_fifo(drm->device);
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struct nvc0_fence_priv *priv;
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int ret;
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priv = kzalloc(sizeof(*priv), GFP_KERNEL);
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priv = drm->fence = kzalloc(sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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@@ -228,10 +225,9 @@ nvc0_fence_create(struct drm_device *dev)
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priv->base.emit = nvc0_fence_emit;
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priv->base.sync = nvc0_fence_sync;
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priv->base.read = nvc0_fence_read;
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dev_priv->fence.func = priv;
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ret = nouveau_bo_new(dev, 16 * pfifo->channels, 0, TTM_PL_FLAG_VRAM,
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0, 0, NULL, &priv->bo);
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ret = nouveau_bo_new(drm->dev, 16 * (pfifo->max + 1), 0,
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TTM_PL_FLAG_VRAM, 0, 0, NULL, &priv->bo);
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if (ret == 0) {
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ret = nouveau_bo_pin(priv->bo, TTM_PL_FLAG_VRAM);
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if (ret == 0)
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@@ -241,6 +237,6 @@ nvc0_fence_create(struct drm_device *dev)
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}
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if (ret)
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nvc0_fence_destroy(dev);
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nvc0_fence_destroy(drm);
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return ret;
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}
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