clk: prima2: enable dt-binding clkdev mapping
this patche deletes hard code that registers clkdev by things like: clk_register_clkdev(clk, NULL, "b0030000.nand"); clk_register_clkdev(clk, NULL, "b0040000.audio"); clk_register_clkdev(clk, NULL, "b0080000.usp"); prima2 clock controller becomes a clock provider and every dt node just declares its clock sources by dt prop. it also makes us easier to extend this driver to support both prima2 and marco as marco has different address mapping with prima2. Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
This commit is contained in:
Barry Song
کامیت شده توسط
Mike Turquette
Mike Turquette
والد
38a8b096f8
کامیت
eb8b8f2e71
@@ -1025,20 +1025,67 @@ static struct of_device_id rsc_ids[] = {
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{},
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};
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enum prima2_clk_index {
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/* 0 1 2 3 4 5 6 7 8 9 */
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rtc, osc, pll1, pll2, pll3, mem, sys, security, dsp, gps,
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mf, io, cpu, uart0, uart1, uart2, tsc, i2c0, i2c1, spi0,
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spi1, pwmc, efuse, pulse, dmac0, dmac1, nand, audio, usp0, usp1,
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usp2, vip, gfx, mm, lcd, vpp, mmc01, mmc23, mmc45, usbpll,
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usb0, usb1, maxclk,
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};
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static __initdata struct clk_hw* prima2_clk_hw_array[maxclk] = {
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NULL, /* dummy */
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NULL,
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&clk_pll1.hw,
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&clk_pll2.hw,
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&clk_pll3.hw,
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&clk_mem.hw,
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&clk_sys.hw,
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&clk_security.hw,
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&clk_dsp.hw,
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&clk_gps.hw,
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&clk_mf.hw,
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&clk_io.hw,
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&clk_cpu.hw,
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&clk_uart0.hw,
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&clk_uart1.hw,
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&clk_uart2.hw,
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&clk_tsc.hw,
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&clk_i2c0.hw,
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&clk_i2c1.hw,
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&clk_spi0.hw,
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&clk_spi1.hw,
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&clk_pwmc.hw,
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&clk_efuse.hw,
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&clk_pulse.hw,
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&clk_dmac0.hw,
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&clk_dmac1.hw,
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&clk_nand.hw,
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&clk_audio.hw,
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&clk_usp0.hw,
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&clk_usp1.hw,
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&clk_usp2.hw,
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&clk_vip.hw,
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&clk_gfx.hw,
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&clk_mm.hw,
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&clk_lcd.hw,
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&clk_vpp.hw,
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&clk_mmc01.hw,
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&clk_mmc23.hw,
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&clk_mmc45.hw,
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&usb_pll_clk_hw,
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&clk_usb0.hw,
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&clk_usb1.hw,
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};
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static struct clk *prima2_clks[maxclk];
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static struct clk_onecell_data clk_data;
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void __init sirfsoc_of_clk_init(void)
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{
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struct clk *clk;
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struct device_node *np;
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np = of_find_matching_node(NULL, clkc_ids);
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if (!np)
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panic("unable to find compatible clkc node in dtb\n");
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sirfsoc_clk_vbase = of_iomap(np, 0);
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if (!sirfsoc_clk_vbase)
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panic("unable to map clkc registers\n");
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of_node_put(np);
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int i;
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np = of_find_matching_node(NULL, rsc_ids);
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if (!np)
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@@ -1050,122 +1097,30 @@ void __init sirfsoc_of_clk_init(void)
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of_node_put(np);
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np = of_find_matching_node(NULL, clkc_ids);
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if (!np)
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return;
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sirfsoc_clk_vbase = of_iomap(np, 0);
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if (!sirfsoc_clk_vbase)
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panic("unable to map clkc registers\n");
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/* These are always available (RTC and 26MHz OSC)*/
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clk = clk_register_fixed_rate(NULL, "rtc", NULL,
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prima2_clks[rtc] = clk_register_fixed_rate(NULL, "rtc", NULL,
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CLK_IS_ROOT, 32768);
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BUG_ON(IS_ERR(clk));
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clk = clk_register_fixed_rate(NULL, "osc", NULL,
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prima2_clks[osc]= clk_register_fixed_rate(NULL, "osc", NULL,
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CLK_IS_ROOT, 26000000);
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BUG_ON(IS_ERR(clk));
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clk = clk_register(NULL, &clk_pll1.hw);
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BUG_ON(IS_ERR(clk));
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clk = clk_register(NULL, &clk_pll2.hw);
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BUG_ON(IS_ERR(clk));
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clk = clk_register(NULL, &clk_pll3.hw);
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BUG_ON(IS_ERR(clk));
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clk = clk_register(NULL, &clk_mem.hw);
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BUG_ON(IS_ERR(clk));
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clk = clk_register(NULL, &clk_sys.hw);
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BUG_ON(IS_ERR(clk));
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clk = clk_register(NULL, &clk_security.hw);
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BUG_ON(IS_ERR(clk));
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clk_register_clkdev(clk, NULL, "b8030000.security");
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clk = clk_register(NULL, &clk_dsp.hw);
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BUG_ON(IS_ERR(clk));
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clk = clk_register(NULL, &clk_gps.hw);
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BUG_ON(IS_ERR(clk));
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clk_register_clkdev(clk, NULL, "a8010000.gps");
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clk = clk_register(NULL, &clk_mf.hw);
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BUG_ON(IS_ERR(clk));
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clk = clk_register(NULL, &clk_io.hw);
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BUG_ON(IS_ERR(clk));
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clk_register_clkdev(clk, NULL, "io");
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clk = clk_register(NULL, &clk_cpu.hw);
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BUG_ON(IS_ERR(clk));
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clk_register_clkdev(clk, NULL, "cpu");
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clk = clk_register(NULL, &clk_uart0.hw);
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BUG_ON(IS_ERR(clk));
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clk_register_clkdev(clk, NULL, "b0050000.uart");
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clk = clk_register(NULL, &clk_uart1.hw);
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BUG_ON(IS_ERR(clk));
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clk_register_clkdev(clk, NULL, "b0060000.uart");
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clk = clk_register(NULL, &clk_uart2.hw);
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BUG_ON(IS_ERR(clk));
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clk_register_clkdev(clk, NULL, "b0070000.uart");
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clk = clk_register(NULL, &clk_tsc.hw);
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BUG_ON(IS_ERR(clk));
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clk_register_clkdev(clk, NULL, "b0110000.tsc");
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clk = clk_register(NULL, &clk_i2c0.hw);
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BUG_ON(IS_ERR(clk));
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clk_register_clkdev(clk, NULL, "b00e0000.i2c");
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clk = clk_register(NULL, &clk_i2c1.hw);
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BUG_ON(IS_ERR(clk));
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clk_register_clkdev(clk, NULL, "b00f0000.i2c");
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clk = clk_register(NULL, &clk_spi0.hw);
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BUG_ON(IS_ERR(clk));
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clk_register_clkdev(clk, NULL, "b00d0000.spi");
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clk = clk_register(NULL, &clk_spi1.hw);
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BUG_ON(IS_ERR(clk));
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clk_register_clkdev(clk, NULL, "b0170000.spi");
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clk = clk_register(NULL, &clk_pwmc.hw);
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BUG_ON(IS_ERR(clk));
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clk_register_clkdev(clk, NULL, "b0130000.pwm");
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clk = clk_register(NULL, &clk_efuse.hw);
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BUG_ON(IS_ERR(clk));
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clk_register_clkdev(clk, NULL, "b0140000.efusesys");
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clk = clk_register(NULL, &clk_pulse.hw);
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BUG_ON(IS_ERR(clk));
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clk_register_clkdev(clk, NULL, "b0150000.pulsec");
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clk = clk_register(NULL, &clk_dmac0.hw);
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BUG_ON(IS_ERR(clk));
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clk_register_clkdev(clk, NULL, "b00b0000.dma-controller");
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clk = clk_register(NULL, &clk_dmac1.hw);
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BUG_ON(IS_ERR(clk));
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clk_register_clkdev(clk, NULL, "b0160000.dma-controller");
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clk = clk_register(NULL, &clk_nand.hw);
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BUG_ON(IS_ERR(clk));
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clk_register_clkdev(clk, NULL, "b0030000.nand");
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clk = clk_register(NULL, &clk_audio.hw);
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BUG_ON(IS_ERR(clk));
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clk_register_clkdev(clk, NULL, "b0040000.audio");
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clk = clk_register(NULL, &clk_usp0.hw);
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BUG_ON(IS_ERR(clk));
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clk_register_clkdev(clk, NULL, "b0080000.usp");
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clk = clk_register(NULL, &clk_usp1.hw);
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BUG_ON(IS_ERR(clk));
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clk_register_clkdev(clk, NULL, "b0090000.usp");
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clk = clk_register(NULL, &clk_usp2.hw);
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BUG_ON(IS_ERR(clk));
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clk_register_clkdev(clk, NULL, "b00a0000.usp");
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clk = clk_register(NULL, &clk_vip.hw);
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BUG_ON(IS_ERR(clk));
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clk_register_clkdev(clk, NULL, "b00c0000.vip");
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clk = clk_register(NULL, &clk_gfx.hw);
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BUG_ON(IS_ERR(clk));
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clk_register_clkdev(clk, NULL, "98000000.graphics");
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clk = clk_register(NULL, &clk_mm.hw);
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BUG_ON(IS_ERR(clk));
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clk_register_clkdev(clk, NULL, "a0000000.multimedia");
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clk = clk_register(NULL, &clk_lcd.hw);
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BUG_ON(IS_ERR(clk));
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clk_register_clkdev(clk, NULL, "90010000.display");
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clk = clk_register(NULL, &clk_vpp.hw);
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BUG_ON(IS_ERR(clk));
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clk_register_clkdev(clk, NULL, "90020000.vpp");
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clk = clk_register(NULL, &clk_mmc01.hw);
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BUG_ON(IS_ERR(clk));
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clk = clk_register(NULL, &clk_mmc23.hw);
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BUG_ON(IS_ERR(clk));
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clk = clk_register(NULL, &clk_mmc45.hw);
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BUG_ON(IS_ERR(clk));
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clk = clk_register(NULL, &usb_pll_clk_hw);
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BUG_ON(IS_ERR(clk));
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clk = clk_register(NULL, &clk_usb0.hw);
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BUG_ON(IS_ERR(clk));
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clk_register_clkdev(clk, NULL, "b00e0000.usb");
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clk = clk_register(NULL, &clk_usb1.hw);
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BUG_ON(IS_ERR(clk));
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clk_register_clkdev(clk, NULL, "b00f0000.usb");
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for (i = pll1; i < maxclk; i++) {
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prima2_clks[i] = clk_register(NULL, prima2_clk_hw_array[i]);
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BUG_ON(!prima2_clks[i]);
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}
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clk_register_clkdev(prima2_clks[cpu], NULL, "cpu");
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clk_register_clkdev(prima2_clks[io], NULL, "io");
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clk_register_clkdev(prima2_clks[mem], NULL, "mem");
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clk_data.clks = prima2_clks;
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clk_data.clk_num = maxclk;
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of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
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}
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