Merge branch 'for-linus' of git://ftp.arm.linux.org.uk/~rmk/linux-arm into next
Pull ARM updates from Russell King: - Major clean-up of the L2 cache support code. The existing mess was becoming rather unmaintainable through all the additions that others have done over time. This turns it into a much nicer structure, and implements a few performance improvements as well. - Clean up some of the CP15 control register tweaks for alignment support, moving some code and data into alignment.c - DMA properties for ARM, from Santosh and reviewed by DT people. This adds DT properties to specify bus translations we can't discover automatically, and to indicate whether devices are coherent. - Hibernation support for ARM - Make ftrace work with read-only text in modules - add suspend support for PJ4B CPUs - rework interrupt masking for undefined instruction handling, which allows us to enable interrupts earlier in the handling of these exceptions. - support for big endian page tables - fix stacktrace support to exclude stacktrace functions from the trace, and add save_stack_trace_regs() implementation so that kprobes can record stack traces. - Add support for the Cortex-A17 CPU. - Remove last vestiges of ARM710 support. - Removal of ARM "meminfo" structure, finally converting us solely to memblock to handle the early memory initialisation. * 'for-linus' of git://ftp.arm.linux.org.uk/~rmk/linux-arm: (142 commits) ARM: ensure C page table setup code follows assembly code (part II) ARM: ensure C page table setup code follows assembly code ARM: consolidate last remaining open-coded alignment trap enable ARM: remove global cr_no_alignment ARM: remove CPU_CP15 conditional from alignment.c ARM: remove unused adjust_cr() function ARM: move "noalign" command line option to alignment.c ARM: provide common method to clear bits in CPU control register ARM: 8025/1: Get rid of meminfo ARM: 8060/1: mm: allow sub-architectures to override PCI I/O memory type ARM: 8066/1: correction for ARM patch 8031/2 ARM: 8049/1: ftrace/add save_stack_trace_regs() implementation ARM: 8065/1: remove last use of CONFIG_CPU_ARM710 ARM: 8062/1: Modify ldrt fixup handler to re-execute the userspace instruction ARM: 8047/1: rwsem: use asm-generic rwsem implementation ARM: l2c: trial at enabling some Cortex-A9 optimisations ARM: l2c: add warnings for stuff modifying aux_ctrl register values ARM: l2c: print a warning with L2C-310 caches if the cache size is modified ARM: l2c: remove old .set_debug method ARM: l2c: kill L2X0_AUX_CTRL_MASK before anyone else makes use of this ...
This commit is contained in:
Linus Torvalds
@@ -167,75 +167,57 @@ void __iomem *omap4_get_l2cache_base(void)
|
||||
return l2cache_base;
|
||||
}
|
||||
|
||||
static void omap4_l2x0_disable(void)
|
||||
static void omap4_l2c310_write_sec(unsigned long val, unsigned reg)
|
||||
{
|
||||
outer_flush_all();
|
||||
/* Disable PL310 L2 Cache controller */
|
||||
omap_smc1(0x102, 0x0);
|
||||
unsigned smc_op;
|
||||
|
||||
switch (reg) {
|
||||
case L2X0_CTRL:
|
||||
smc_op = OMAP4_MON_L2X0_CTRL_INDEX;
|
||||
break;
|
||||
|
||||
case L2X0_AUX_CTRL:
|
||||
smc_op = OMAP4_MON_L2X0_AUXCTRL_INDEX;
|
||||
break;
|
||||
|
||||
case L2X0_DEBUG_CTRL:
|
||||
smc_op = OMAP4_MON_L2X0_DBG_CTRL_INDEX;
|
||||
break;
|
||||
|
||||
case L310_PREFETCH_CTRL:
|
||||
smc_op = OMAP4_MON_L2X0_PREFETCH_INDEX;
|
||||
break;
|
||||
|
||||
default:
|
||||
WARN_ONCE(1, "OMAP L2C310: ignoring write to reg 0x%x\n", reg);
|
||||
return;
|
||||
}
|
||||
|
||||
omap_smc1(smc_op, val);
|
||||
}
|
||||
|
||||
static void omap4_l2x0_set_debug(unsigned long val)
|
||||
int __init omap_l2_cache_init(void)
|
||||
{
|
||||
/* Program PL310 L2 Cache controller debug register */
|
||||
omap_smc1(0x100, val);
|
||||
}
|
||||
|
||||
static int __init omap_l2_cache_init(void)
|
||||
{
|
||||
u32 aux_ctrl = 0;
|
||||
|
||||
/*
|
||||
* To avoid code running on other OMAPs in
|
||||
* multi-omap builds
|
||||
*/
|
||||
if (!cpu_is_omap44xx())
|
||||
return -ENODEV;
|
||||
u32 aux_ctrl;
|
||||
|
||||
/* Static mapping, never released */
|
||||
l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K);
|
||||
if (WARN_ON(!l2cache_base))
|
||||
return -ENOMEM;
|
||||
|
||||
/*
|
||||
* 16-way associativity, parity disabled
|
||||
* Way size - 32KB (es1.0)
|
||||
* Way size - 64KB (es2.0 +)
|
||||
*/
|
||||
aux_ctrl = ((1 << L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT) |
|
||||
(0x1 << 25) |
|
||||
(0x1 << L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT) |
|
||||
(0x1 << L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT));
|
||||
|
||||
if (omap_rev() == OMAP4430_REV_ES1_0) {
|
||||
aux_ctrl |= 0x2 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT;
|
||||
} else {
|
||||
aux_ctrl |= ((0x3 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT) |
|
||||
(1 << L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT) |
|
||||
(1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) |
|
||||
(1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) |
|
||||
(1 << L2X0_AUX_CTRL_EARLY_BRESP_SHIFT));
|
||||
}
|
||||
if (omap_rev() != OMAP4430_REV_ES1_0)
|
||||
omap_smc1(0x109, aux_ctrl);
|
||||
|
||||
/* Enable PL310 L2 Cache controller */
|
||||
omap_smc1(0x102, 0x1);
|
||||
/* 16-way associativity, parity disabled, way size - 64KB (es2.0 +) */
|
||||
aux_ctrl = L2C_AUX_CTRL_SHARED_OVERRIDE |
|
||||
L310_AUX_CTRL_DATA_PREFETCH |
|
||||
L310_AUX_CTRL_INSTR_PREFETCH;
|
||||
|
||||
outer_cache.write_sec = omap4_l2c310_write_sec;
|
||||
if (of_have_populated_dt())
|
||||
l2x0_of_init(aux_ctrl, L2X0_AUX_CTRL_MASK);
|
||||
l2x0_of_init(aux_ctrl, 0xcf9fffff);
|
||||
else
|
||||
l2x0_init(l2cache_base, aux_ctrl, L2X0_AUX_CTRL_MASK);
|
||||
|
||||
/*
|
||||
* Override default outer_cache.disable with a OMAP4
|
||||
* specific one
|
||||
*/
|
||||
outer_cache.disable = omap4_l2x0_disable;
|
||||
outer_cache.set_debug = omap4_l2x0_set_debug;
|
||||
l2x0_init(l2cache_base, aux_ctrl, 0xcf9fffff);
|
||||
|
||||
return 0;
|
||||
}
|
||||
omap_early_initcall(omap_l2_cache_init);
|
||||
#endif
|
||||
|
||||
void __iomem *omap4_get_sar_ram_base(void)
|
||||
|
||||
Reference in New Issue
Block a user