Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM Device-tree updates from Olof Johansson:
"As always, the bulk of updates. Some of the news this cycle:
New SoC descriptions:
- Broadcom BCM2711
- Amlogic Meson A1 and G12
- Freescale S32V234
- Marvell Armada AP807/AP807-quad and CP115
- Realtek RTD1293 and RTD1296
- Rockchip RK3308
New boards and platforms:
- Allwinner: NanoPi Duo2
- Amlogic: Ugoos am6
- Atmel at91: Overkiz Kizbox2/4
- Broadcom: RPi4, Luxul XWC-2000
- Marvell: New Espressobin flavor
- NXP: i.MX8MN LPDDR4 EVK, i.MX8QXP Colibri, S32V234 EVB, Netronix
E60K02 and Kobo Clara HD, Kontron N6311 and N6411, OPOS6UL and
OPOS6ULDev
- Renesas: Salvator-XS
- Rockchip: Beelink A1 (rk3308), rk3308 eval boards, rk3399-roc-pc"
* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (653 commits)
ARM: dts: logicpd-torpedo: Disable USB Host
arm: dts: mt6323: add keys, power-controller, rtc and codec
arm64: dts: mt8183: add systimer0 device node
dt-bindings: mediatek: update bindings for MT8183 systimer
arm64: dts: rockchip: fix sdmmc detection on boot on rk3328-roc-cc
arm64: dts: rockchip: Split rk3399-roc-pc for with and without mezzanine board.
arm64: dts: rockchip: Add Beelink A1
dt-bindings: ARM: rockchip: Add Beelink A1
arm64: dts: rockchip: Add RK3328 audio pipelines
arm64: dts: ti: k3-j721e-common-proc-board: Add USB ports
arm64: dts: ti: k3-j721e-main: add USB controller nodes
ARM: dts: aspeed-g6: Add timer description
ARM: dts: aspeed: ast2600evb: Enable i2c buses
ARM: dts: at91: add a dts and dtsi file for kizbox2 based boards
dt-bindings: arm: at91: Document Kizbox2-2 board binding
arm64: dts: meson-gx: fix i2c compatible
arm64: dts: meson-gx: cec node should be disabled by default
arm64: dts: meson-g12b-odroid-n2: add missing amlogic, s922x compatible
arm64: dts: meson-gxm: fix gpu irq order
arm64: dts: meson-g12a: fix gpu irq order
...
此提交包含在：
Linus Torvalds
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/* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) */
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/*
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* Realtek RTD1295 reset controllers
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*
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* Copyright (c) 2017 Andreas Färber
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*/
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#ifndef DT_BINDINGS_RESET_RTD1295_H
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#define DT_BINDINGS_RESET_RTD1295_H
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/* soft reset 1 */
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#define RTD1295_RSTN_MISC 0
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#define RTD1295_RSTN_NAT 1
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#define RTD1295_RSTN_USB3_PHY0_POW 2
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#define RTD1295_RSTN_GSPI 3
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#define RTD1295_RSTN_USB3_P0_MDIO 4
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#define RTD1295_RSTN_SATA_0 5
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#define RTD1295_RSTN_USB 6
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#define RTD1295_RSTN_SATA_PHY_0 7
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#define RTD1295_RSTN_USB_PHY0 8
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#define RTD1295_RSTN_USB_PHY1 9
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#define RTD1295_RSTN_SATA_PHY_POW_0 10
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#define RTD1295_RSTN_SATA_FUNC_EXIST_0 11
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#define RTD1295_RSTN_HDMI 12
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#define RTD1295_RSTN_VE1 13
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#define RTD1295_RSTN_VE2 14
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#define RTD1295_RSTN_VE3 15
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#define RTD1295_RSTN_ETN 16
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#define RTD1295_RSTN_AIO 17
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#define RTD1295_RSTN_GPU 18
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#define RTD1295_RSTN_TVE 19
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#define RTD1295_RSTN_VO 20
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#define RTD1295_RSTN_LVDS 21
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#define RTD1295_RSTN_SE 22
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#define RTD1295_RSTN_DCU 23
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#define RTD1295_RSTN_DC_PHY 24
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#define RTD1295_RSTN_CP 25
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#define RTD1295_RSTN_MD 26
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#define RTD1295_RSTN_TP 27
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#define RTD1295_RSTN_AE 28
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#define RTD1295_RSTN_NF 29
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#define RTD1295_RSTN_MIPI 30
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#define RTD1295_RSTN_RSA 31
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/* soft reset 2 */
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#define RTD1295_RSTN_ACPU 0
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#define RTD1295_RSTN_JPEG 1
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#define RTD1295_RSTN_USB_PHY3 2
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#define RTD1295_RSTN_USB_PHY2 3
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#define RTD1295_RSTN_USB3_PHY1_POW 4
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#define RTD1295_RSTN_USB3_P1_MDIO 5
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#define RTD1295_RSTN_PCIE0_STITCH 6
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#define RTD1295_RSTN_PCIE0_PHY 7
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#define RTD1295_RSTN_PCIE0 8
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#define RTD1295_RSTN_PCR_CNT 9
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#define RTD1295_RSTN_CR 10
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#define RTD1295_RSTN_EMMC 11
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#define RTD1295_RSTN_SDIO 12
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#define RTD1295_RSTN_PCIE0_CORE 13
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#define RTD1295_RSTN_PCIE0_POWER 14
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#define RTD1295_RSTN_PCIE0_NONSTICH 15
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#define RTD1295_RSTN_PCIE1_PHY 16
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#define RTD1295_RSTN_PCIE1 17
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#define RTD1295_RSTN_I2C_5 18
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#define RTD1295_RSTN_PCIE1_STITCH 19
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#define RTD1295_RSTN_PCIE1_CORE 20
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#define RTD1295_RSTN_PCIE1_POWER 21
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#define RTD1295_RSTN_PCIE1_NONSTICH 22
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#define RTD1295_RSTN_I2C_4 23
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#define RTD1295_RSTN_I2C_3 24
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#define RTD1295_RSTN_I2C_2 25
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#define RTD1295_RSTN_I2C_1 26
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#define RTD1295_RSTN_UR2 27
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#define RTD1295_RSTN_UR1 28
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#define RTD1295_RSTN_MISC_SC 29
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#define RTD1295_RSTN_CBUS_TX 30
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#define RTD1295_RSTN_SDS_PHY 31
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/* soft reset 4 */
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#define RTD1295_RSTN_DCPHY_CRT 0
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#define RTD1295_RSTN_DCPHY_ALERT_RX 1
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#define RTD1295_RSTN_DCPHY_PTR 2
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#define RTD1295_RSTN_DCPHY_LDO 3
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#define RTD1295_RSTN_DCPHY_SSC_DIG 4
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#define RTD1295_RSTN_HDMIRX 5
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#define RTD1295_RSTN_CBUSRX 6
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#define RTD1295_RSTN_SATA_PHY_POW_1 7
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#define RTD1295_RSTN_SATA_FUNC_EXIST_1 8
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#define RTD1295_RSTN_SATA_PHY_1 9
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#define RTD1295_RSTN_SATA_1 10
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#define RTD1295_RSTN_FAN 11
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#define RTD1295_RSTN_HDMIRX_WRAP 12
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#define RTD1295_RSTN_PCIE0_PHY_MDIO 13
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#define RTD1295_RSTN_PCIE1_PHY_MDIO 14
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#define RTD1295_RSTN_DISP 15
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/* iso reset */
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#define RTD1295_ISO_RSTN_IR 1
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#define RTD1295_ISO_RSTN_CEC0 2
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#define RTD1295_ISO_RSTN_CEC1 3
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#define RTD1295_ISO_RSTN_DP 4
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#define RTD1295_ISO_RSTN_CBUSTX 5
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#define RTD1295_ISO_RSTN_CBUSRX 6
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#define RTD1295_ISO_RSTN_EFUSE 7
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#define RTD1295_ISO_RSTN_UR0 8
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#define RTD1295_ISO_RSTN_GMAC 9
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#define RTD1295_ISO_RSTN_GPHY 10
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#define RTD1295_ISO_RSTN_I2C_0 11
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#define RTD1295_ISO_RSTN_I2C_1 12
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#define RTD1295_ISO_RSTN_CBUS 13
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#endif
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