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Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Browse Source 
Pull ARM Device-tree updates from Olof Johansson:
 "As always, the bulk of updates.  Some of the news this cycle:

  New SoC descriptions:
   - Broadcom BCM2711
   - Amlogic Meson A1 and G12
   - Freescale S32V234
   - Marvell Armada AP807/AP807-quad and CP115
   - Realtek RTD1293 and RTD1296
   - Rockchip RK3308

  New boards and platforms:
   - Allwinner: NanoPi Duo2
   - Amlogic: Ugoos am6
   - Atmel at91: Overkiz Kizbox2/4
   - Broadcom: RPi4, Luxul XWC-2000
   - Marvell: New Espressobin flavor
   - NXP: i.MX8MN LPDDR4 EVK, i.MX8QXP Colibri, S32V234 EVB, Netronix
     E60K02 and Kobo Clara HD, Kontron N6311 and N6411, OPOS6UL and
     OPOS6ULDev
   - Renesas: Salvator-XS
   - Rockchip: Beelink A1 (rk3308), rk3308 eval boards, rk3399-roc-pc"

* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (653 commits)
  ARM: dts: logicpd-torpedo: Disable USB Host
  arm: dts: mt6323: add keys, power-controller, rtc and codec
  arm64: dts: mt8183: add systimer0 device node
  dt-bindings: mediatek: update bindings for MT8183 systimer
  arm64: dts: rockchip: fix sdmmc detection on boot on rk3328-roc-cc
  arm64: dts: rockchip: Split rk3399-roc-pc for with and without mezzanine board.
  arm64: dts: rockchip: Add Beelink A1
  dt-bindings: ARM: rockchip: Add Beelink A1
  arm64: dts: rockchip: Add RK3328 audio pipelines
  arm64: dts: ti: k3-j721e-common-proc-board: Add USB ports
  arm64: dts: ti: k3-j721e-main: add USB controller nodes
  ARM: dts: aspeed-g6: Add timer description
  ARM: dts: aspeed: ast2600evb: Enable i2c buses
  ARM: dts: at91: add a dts and dtsi file for kizbox2 based boards
  dt-bindings: arm: at91: Document Kizbox2-2 board binding
  arm64: dts: meson-gx: fix i2c compatible
  arm64: dts: meson-gx: cec node should be disabled by default
  arm64: dts: meson-g12b-odroid-n2: add missing amlogic, s922x compatible
  arm64: dts: meson-gxm: fix gpu irq order
  arm64: dts: meson-g12a: fix gpu irq order
  ...
This commit is contained in:
Linus Torvalds
2019-12-05 12:09:47 -08:00
parent ec939e4c94 5f1f152834
commit eb275167d1
498 changed files with 37569 additions and 10479 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
Documentation/devicetree/bindings/arm/amlogic.yaml
View File

@@ -94,7 +94,7 @@ properties:
- amlogic,p212
- hwacom,amazetv
- khadas,vim
- libretech,cc
- libretech,aml-s905x-cc
- nexbox,a95x
- const: amlogic,s905x
- const: amlogic,meson-gxl
@@ -147,6 +147,7 @@ properties:
- enum:
- hardkernel,odroid-n2
- khadas,vim3
- ugoos,am6
- const: amlogic,s922x
- const: amlogic,g12b
@@ -156,4 +157,10 @@ properties:
- seirobotics,sei610
- khadas,vim3l
- const: amlogic,sm1
- description: Boards with the Amlogic Meson A1 A113L SoC
items:
- enum:
- amlogic,ad401
- const: amlogic,a1
...

14
Documentation/devicetree/bindings/arm/atmel-at91.yaml
View File

@@ -45,6 +45,13 @@ properties:
- const: atmel,at91sam9x5
- const: atmel,at91sam9
- description: Overkiz kizbox3 board
items:
- const: overkiz,kizbox3-hs
- const: atmel,sama5d27
- const: atmel,sama5d2
- const: atmel,sama5
- items:
- const: atmel,sama5d27
- const: atmel,sama5d2
@@ -73,6 +80,13 @@ properties:
- const: atmel,sama5d3
- const: atmel,sama5
- description: Overkiz kizbox2 board with two heads
items:
- const: overkiz,kizbox2-2
- const: atmel,sama5d31
- const: atmel,sama5d3
- const: atmel,sama5
- items:
- enum:
- atmel,sama5d31

54
Documentation/devicetree/bindings/arm/bcm/bcm2835.yaml Normal file
View File

@@ -0,0 +1,54 @@
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/bcm/bcm2835.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom BCM2711/BCM2835 Platforms Device Tree Bindings
maintainers:
- Eric Anholt <eric@anholt.net>
- Stefan Wahren <wahrenst@gmx.net>
properties:
$nodename:
const: '/'
compatible:
oneOf:
- description: BCM2711 based Boards
items:
- enum:
- raspberrypi,4-model-b
- const: brcm,bcm2711
- description: BCM2835 based Boards
items:
- enum:
- raspberrypi,model-a
- raspberrypi,model-a-plus
- raspberrypi,model-b
- raspberrypi,model-b-i2c0 # Raspberry Pi Model B (no P5)
- raspberrypi,model-b-rev2
- raspberrypi,model-b-plus
- raspberrypi,compute-module
- raspberrypi,model-zero
- raspberrypi,model-zero-w
- const: brcm,bcm2835
- description: BCM2836 based Boards
items:
- enum:
- raspberrypi,2-model-b
- const: brcm,bcm2836
- description: BCM2837 based Boards
items:
- enum:
- raspberrypi,3-model-a-plus
- raspberrypi,3-model-b
- raspberrypi,3-model-b-plus
- raspberrypi,3-compute-module
- raspberrypi,3-compute-module-lite
- const: brcm,bcm2837
...

67
Documentation/devicetree/bindings/arm/bcm/brcm,bcm2835.txt
View File

@@ -1,67 +0,0 @@
Broadcom BCM2835 device tree bindings
-------------------------------------------
Raspberry Pi Model A
Required root node properties:
compatible = "raspberrypi,model-a", "brcm,bcm2835";
Raspberry Pi Model A+
Required root node properties:
compatible = "raspberrypi,model-a-plus", "brcm,bcm2835";
Raspberry Pi Model B
Required root node properties:
compatible = "raspberrypi,model-b", "brcm,bcm2835";
Raspberry Pi Model B (no P5)
early model B with I2C0 rather than I2C1 routed to the expansion header
Required root node properties:
compatible = "raspberrypi,model-b-i2c0", "brcm,bcm2835";
Raspberry Pi Model B rev2
Required root node properties:
compatible = "raspberrypi,model-b-rev2", "brcm,bcm2835";
Raspberry Pi Model B+
Required root node properties:
compatible = "raspberrypi,model-b-plus", "brcm,bcm2835";
Raspberry Pi 2 Model B
Required root node properties:
compatible = "raspberrypi,2-model-b", "brcm,bcm2836";
Raspberry Pi 3 Model A+
Required root node properties:
compatible = "raspberrypi,3-model-a-plus", "brcm,bcm2837";
Raspberry Pi 3 Model B
Required root node properties:
compatible = "raspberrypi,3-model-b", "brcm,bcm2837";
Raspberry Pi 3 Model B+
Required root node properties:
compatible = "raspberrypi,3-model-b-plus", "brcm,bcm2837";
Raspberry Pi Compute Module
Required root node properties:
compatible = "raspberrypi,compute-module", "brcm,bcm2835";
Raspberry Pi Compute Module 3
Required root node properties:
compatible = "raspberrypi,3-compute-module", "brcm,bcm2837";
Raspberry Pi Compute Module 3 Lite
Required root node properties:
compatible = "raspberrypi,3-compute-module-lite", "brcm,bcm2837";
Raspberry Pi Zero
Required root node properties:
compatible = "raspberrypi,model-zero", "brcm,bcm2835";
Raspberry Pi Zero W
Required root node properties:
compatible = "raspberrypi,model-zero-w", "brcm,bcm2835";
Generic BCM2835 board
Required root node properties:
compatible = "brcm,bcm2835";

1
Documentation/devicetree/bindings/arm/cpus.yaml
View File

@@ -189,6 +189,7 @@ properties:
- marvell,armada-390-smp
- marvell,armada-xp-smp
- marvell,98dx3236-smp
- marvell,mmp3-smp
- mediatek,mt6589-smp
- mediatek,mt81xx-tz-smp
- qcom,gcc-msm8660

58
Documentation/devicetree/bindings/arm/fsl.yaml
View File

@@ -38,12 +38,16 @@ properties:
- description: i.MX27 Product Development Kit
items:
- enum:
- armadeus,imx27-apf27 # APF27 SoM
- armadeus,imx27-apf27dev # APF27 SoM on APF27Dev board
- fsl,imx27-pdk
- const: fsl,imx27
- description: i.MX28 based Boards
items:
- enum:
- armadeus,imx28-apf28 # APF28 SoM
- armadeus,imx28-apf28dev # APF28 SoM on APF28Dev board
- fsl,imx28-evk
- i2se,duckbill
- i2se,duckbill-2
@@ -87,7 +91,8 @@ properties:
- description: i.MX51 Babbage Board
items:
- enum:
- armadeus,imx51-apf51
- armadeus,imx51-apf51 # APF51 SoM
- armadeus,imx51-apf51dev # APF51 SoM on APF51Dev board
- fsl,imx51-babbage
- technologic,imx51-ts4800
- const: fsl,imx51
@@ -106,6 +111,8 @@ properties:
- description: i.MX6Q based Boards
items:
- enum:
- armadeus,imx6q-apf6 # APF6 (Quad/Dual) SoM
- armadeus,imx6q-apf6dev # APF6 (Quad/Dual) SoM on APF6Dev board
- emtrion,emcon-mx6 # emCON-MX6D or emCON-MX6Q SoM
- emtrion,emcon-mx6-avari # emCON-MX6D or emCON-MX6Q SoM on Avari Base
- fsl,imx6q-arm2
@@ -114,6 +121,11 @@ properties:
- fsl,imx6q-sabresd
- technologic,imx6q-ts4900
- technologic,imx6q-ts7970
- toradex,apalis_imx6q # Apalis iMX6 Module
- toradex,apalis_imx6q-eval # Apalis iMX6 Module on Apalis Evaluation Board
- toradex,apalis_imx6q-ixora # Apalis iMX6 Module on Ixora
- toradex,apalis_imx6q-ixora-v1.1 # Apalis iMX6 Module on Ixora V1.1
- variscite,dt6customboard
- const: fsl,imx6q
- description: i.MX6QP based Boards
@@ -126,6 +138,8 @@ properties:
- description: i.MX6DL based Boards
items:
- enum:
- armadeus,imx6dl-apf6 # APF6 (Solo) SoM
- armadeus,imx6dl-apf6dldev # APF6 (Solo) SoM on APF6Dev board
- eckelmann,imx6dl-ci4x10
- emtrion,emcon-mx6 # emCON-MX6S or emCON-MX6DL SoM
- emtrion,emcon-mx6-avari # emCON-MX6S or emCON-MX6DL SoM on Avari Base
@@ -133,6 +147,8 @@ properties:
- fsl,imx6dl-sabresd # i.MX6 DualLite SABRE Smart Device Board
- technologic,imx6dl-ts4900
- technologic,imx6dl-ts7970
- toradex,colibri_imx6dl # Colibri iMX6 Module
- toradex,colibri_imx6dl-eval-v3 # Colibri iMX6 Module on Colibri Evaluation Board V3
- ysoft,imx6dl-yapp4-draco # i.MX6 DualLite Y Soft IOTA Draco board
- ysoft,imx6dl-yapp4-hydra # i.MX6 DualLite Y Soft IOTA Hydra board
- ysoft,imx6dl-yapp4-ursa # i.MX6 Solo Y Soft IOTA Ursa board
@@ -148,6 +164,7 @@ properties:
items:
- enum:
- fsl,imx6sll-evk
- kobo,clarahd
- const: fsl,imx6sll
- description: i.MX6SX based Boards
@@ -160,8 +177,11 @@ properties:
- description: i.MX6UL based Boards
items:
- enum:
- armadeus,imx6ul-opos6ul # OPOS6UL (i.MX6UL) SoM
- armadeus,imx6ul-opos6uldev # OPOS6UL (i.MX6UL) SoM on OPOS6ULDev board
- fsl,imx6ul-14x14-evk # i.MX6 UltraLite 14x14 EVK Board
- kontron,imx6ul-n6310-som # Kontron N6310 SOM
- kontron,imx6ul-n6311-som # Kontron N6311 SOM
- const: fsl,imx6ul
- description: Kontron N6310 S Board
@@ -170,6 +190,12 @@ properties:
- const: kontron,imx6ul-n6310-som
- const: fsl,imx6ul
- description: Kontron N6311 S Board
items:
- const: kontron,imx6ul-n6311-s
- const: kontron,imx6ul-n6311-som
- const: fsl,imx6ul
- description: Kontron N6310 S 43 Board
items:
- const: kontron,imx6ul-n6310-s-43
@@ -180,7 +206,18 @@ properties:
- description: i.MX6ULL based Boards
items:
- enum:
- armadeus,imx6ull-opos6ul # OPOS6UL (i.MX6ULL) SoM
- armadeus,imx6ull-opos6uldev # OPOS6UL (i.MX6ULL) SoM on OPOS6ULDev board
- fsl,imx6ull-14x14-evk # i.MX6 UltraLiteLite 14x14 EVK Board
- kontron,imx6ull-n6411-som # Kontron N6411 SOM
- toradex,colibri-imx6ull-eval # Colibri iMX6ULL Module on Colibri Evaluation Board
- toradex,colibri-imx6ull-wifi-eval # Colibri iMX6ULL Wi-Fi / Bluetooth Module on Colibri Evaluation Board
- const: fsl,imx6ull
- description: Kontron N6411 S Board
items:
- const: kontron,imx6ull-n6411-s
- const: kontron,imx6ull-n6411-som
- const: fsl,imx6ull
- description: i.MX6ULZ based Boards
@@ -193,6 +230,8 @@ properties:
- description: i.MX7S based Boards
items:
- enum:
- toradex,colibri-imx7s # Colibri iMX7 Solo Module
- toradex,colibri-imx7s-eval-v3 # Colibri iMX7 Solo Module on Colibri Evaluation Board V3
- tq,imx7s-mba7 # i.MX7S TQ MBa7 with TQMa7S SoM
- const: fsl,imx7s
@@ -201,6 +240,10 @@ properties:
- enum:
- fsl,imx7d-sdb # i.MX7 SabreSD Board
- novtech,imx7d-meerkat96 # i.MX7 Meerkat96 Board
- toradex,colibri-imx7d # Colibri iMX7 Dual Module
- toradex,colibri-imx7d-emmc # Colibri iMX7 Dual 1GB (eMMC) Module
- toradex,colibri-imx7d-emmc-eval-v3 # Colibri iMX7 Dual 1GB (eMMC) Module on Colibri Evaluation Board V3
- toradex,colibri-imx7d-eval-v3 # Colibri iMX7 Dual Module on Colibri Evaluation Board V3
- tq,imx7d-mba7 # i.MX7D TQ MBa7 with TQMa7D SoM
- zii,imx7d-rmu2 # ZII RMU2 Board
- zii,imx7d-rpu2 # ZII RPU2 Board
@@ -233,6 +276,7 @@ properties:
items:
- enum:
- fsl,imx8mn-ddr4-evk # i.MX8MN DDR4 EVK Board
- fsl,imx8mn-evk # i.MX8MN LPDDR4 EVK Board
- const: fsl,imx8mn
- description: i.MX8MQ based Boards
@@ -250,6 +294,8 @@ properties:
- enum:
- einfochips,imx8qxp-ai_ml # i.MX8QXP AI_ML Board
- fsl,imx8qxp-mek # i.MX8QXP MEK Board
- toradex,colibri-imx8x # Colibri iMX8X Module
- toradex,colibri-imx8x-eval-v3 # Colibri iMX8X Module on Colibri Evaluation Board V3
- const: fsl,imx8qxp
- description:
@@ -267,6 +313,10 @@ properties:
- fsl,vf600
- fsl,vf610
- fsl,vf610m4
- toradex,vf500-colibri_vf50 # Colibri VF50 Module
- toradex,vf500-colibri_vf50-on-eval # Colibri VF50 Module on Colibri Evaluation Board
- toradex,vf610-colibri_vf61 # Colibri VF61 Module
- toradex,vf610-colibri_vf61-on-eval # Colibri VF61 Module on Colibri Evaluation Board
- description: ZII's VF610 based Boards
items:
@@ -335,4 +385,10 @@ properties:
- fsl,ls2088a-rdb
- const: fsl,ls2088a
- description: S32V234 based Boards
items:
- enum:
- fsl,s32v234-evb # S32V234-EVB2 Customer Evaluation Board
- const: fsl,s32v234
...

14
Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt → Documentation/devicetree/bindings/arm/marvell/ap80x-system-controller.txt
View File

@@ -1,15 +1,15 @@
Marvell Armada AP806 System Controller
Marvell Armada AP80x System Controller
======================================
The AP806 is one of the two core HW blocks of the Marvell Armada 7K/8K
SoCs. It contains system controllers, which provide several registers
giving access to numerous features: clocks, pin-muxing and many other
SoC configuration items. This DT binding allows to describe these
system controllers.
The AP806/AP807 is one of the two core HW blocks of the Marvell Armada
7K/8K/931x SoCs. It contains system controllers, which provide several
registers giving access to numerous features: clocks, pin-muxing and
many other SoC configuration items. This DT binding allows to describe
these system controllers.
For the top level node:
- compatible: must be: "syscon", "simple-mfd";
- reg: register area of the AP806 system controller
- reg: register area of the AP80x system controller
SYSTEM CONTROLLER 0
===================

24
Documentation/devicetree/bindings/arm/marvell/armada-7k-8k.txt
View File

@@ -1,24 +0,0 @@
Marvell Armada 7K/8K Platforms Device Tree Bindings
---------------------------------------------------
Boards using a SoC of the Marvell Armada 7K or 8K families must carry
the following root node property:
- compatible, with one of the following values:
- "marvell,armada7020", "marvell,armada-ap806-dual", "marvell,armada-ap806"
when the SoC being used is the Armada 7020
- "marvell,armada7040", "marvell,armada-ap806-quad", "marvell,armada-ap806"
when the SoC being used is the Armada 7040
- "marvell,armada8020", "marvell,armada-ap806-dual", "marvell,armada-ap806"
when the SoC being used is the Armada 8020
- "marvell,armada8040", "marvell,armada-ap806-quad", "marvell,armada-ap806"
when the SoC being used is the Armada 8040
Example:
compatible = "marvell,armada7040-db", "marvell,armada7040",
"marvell,armada-ap806-quad", "marvell,armada-ap806";

61
Documentation/devicetree/bindings/arm/marvell/armada-7k-8k.yaml Normal file
View File

@@ -0,0 +1,61 @@
# SPDX-License-Identifier: (GPL-2.0+ OR X11)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/marvell/armada-7k-8k.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Marvell Armada 7K/8K Platforms Device Tree Bindings
maintainers:
- Gregory CLEMENT <gregory.clement@bootlin.com>
properties:
$nodename:
const: '/'
compatible:
oneOf:
- description: Armada 7020 SoC
items:
- const: marvell,armada7020
- const: marvell,armada-ap806-dual
- const: marvell,armada-ap806
- description: Armada 7040 SoC
items:
- const: marvell,armada7040
- const: marvell,armada-ap806-quad
- const: marvell,armada-ap806
- description: Armada 8020 SoC
items:
- const: marvell,armada8020
- const: marvell,armada-ap806-dual
- const: marvell,armada-ap806
- description: Armada 8040 SoC
items:
- const: marvell,armada8040
- const: marvell,armada-ap806-quad
- const: marvell,armada-ap806
- description: Armada CN9130 SoC with no external CP
items:
- const: marvell,cn9130
- const: marvell,armada-ap807-quad
- const: marvell,armada-ap807
- description: Armada CN9131 SoC with one external CP
items:
- const: marvell,cn9131
- const: marvell,cn9130
- const: marvell,armada-ap807-quad
- const: marvell,armada-ap807
- description: Armada CN9132 SoC with two external CPs
items:
- const: marvell,cn9132
- const: marvell,cn9131
- const: marvell,cn9130
- const: marvell,armada-ap807-quad
- const: marvell,armada-ap807

14
Documentation/devicetree/bindings/arm/mrvl/mrvl.txt
View File

@@ -1,14 +0,0 @@
Marvell Platforms Device Tree Bindings
----------------------------------------------------
PXA168 Aspenite Board
Required root node properties:
- compatible = "mrvl,pxa168-aspenite", "mrvl,pxa168";
PXA910 DKB Board
Required root node properties:
- compatible = "mrvl,pxa910-dkb";
MMP2 Brownstone Board
Required root node properties:
- compatible = "mrvl,mmp2-brownstone", "mrvl,mmp2";

35
Documentation/devicetree/bindings/arm/mrvl/mrvl.yaml Normal file
View File

@@ -0,0 +1,35 @@
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/mrvl/mrvl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Marvell Platforms Device Tree Bindings
maintainers:
- Lubomir Rintel <lkundrak@v3.sk>
properties:
$nodename:
const: '/'
compatible:
oneOf:
- description: PXA168 Aspenite Board
items:
- enum:
- mrvl,pxa168-aspenite
- const: mrvl,pxa168
- description: PXA910 DKB Board
items:
- enum:
- mrvl,pxa910-dkb
- const: mrvl,pxa910
- description: MMP2 based boards
items:
- enum:
- mrvl,mmp2-brownstone
- const: mrvl,mmp2
- description: MMP3 based boards
items:
- const: mrvl,mmp3
...

27
Documentation/devicetree/bindings/arm/realtek.yaml
View File

@@ -13,11 +13,24 @@ properties:
$nodename:
const: '/'
compatible:
# RTD1295 SoC based boards
items:
- enum:
- mele,v9
- probox2,ava
- zidoo,x9s
- const: realtek,rtd1295
oneOf:
# RTD1293 SoC based boards
- items:
- enum:
- synology,ds418j # Synology DiskStation DS418j
- const: realtek,rtd1293
# RTD1295 SoC based boards
- items:
- enum:
- mele,v9 # MeLE V9
- probox2,ava # ProBox2 AVA
- zidoo,x9s # Zidoo X9S
- const: realtek,rtd1295
# RTD1296 SoC based boards
- items:
- enum:
- synology,ds418 # Synology DiskStation DS418
- const: realtek,rtd1296
...

20
Documentation/devicetree/bindings/arm/renesas,prr.txt
View File

@@ -1,20 +0,0 @@
Renesas Product Register
Most Renesas ARM SoCs have a Product Register or Boundary Scan ID Register that
allows to retrieve SoC product and revision information. If present, a device
node for this register should be added.
Required properties:
- compatible: Must be one of:
"renesas,prr"
"renesas,bsid"
- reg: Base address and length of the register block.
Examples
--------
prr: chipid@ff000044 {
compatible = "renesas,prr";
reg = <0 0xff000044 0 4>;
};

35
Documentation/devicetree/bindings/arm/renesas,prr.yaml Normal file
View File

@@ -0,0 +1,35 @@
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/renesas,prr.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Renesas Product Register
maintainers:
- Geert Uytterhoeven <geert+renesas@glider.be>
- Magnus Damm <magnus.damm@gmail.com>
description: |
Most Renesas ARM SoCs have a Product Register or Boundary Scan ID
Register that allows to retrieve SoC product and revision information.
If present, a device node for this register should be added.
properties:
compatible:
enum:
- renesas,prr
- renesas,bsid
reg:
maxItems: 1
required:
- compatible
- reg
examples:
- |
prr: chipid@ff000044 {
compatible = "renesas,prr";
reg = <0 0xff000044 0 4>;
};

20
Documentation/devicetree/bindings/arm/renesas.yaml
View File

@@ -116,6 +116,18 @@ properties:
- const: hoperun,hihope-rzg2m
- const: renesas,r8a774a1
- description: RZ/G2N (R8A774B1)
items:
- enum:
- hoperun,hihope-rzg2n # HopeRun HiHope RZ/G2N platform
- const: renesas,r8a774b1
- items:
- enum:
- hoperun,hihope-rzg2-ex # HopeRun expansion board for HiHope RZ/G2 platforms
- const: hoperun,hihope-rzg2n
- const: renesas,r8a774b1
- description: RZ/G2E (R8A774C0)
items:
- enum:
@@ -193,15 +205,23 @@ properties:
- renesas,salvator-xs # Salvator-XS (Salvator-X 2nd version, RTP0RC7796SIPB0012S)
- const: renesas,r8a7796
- description: R-Car M3-W+ (R8A77961)
items:
- enum:
- renesas,salvator-xs # Salvator-XS (Salvator-X 2nd version, RTP0RC7796SIPB0012SA5A)
- const: renesas,r8a77961
- description: Kingfisher (SBEV-RCAR-KF-M03)
items:
- const: shimafuji,kingfisher
- enum:
- renesas,h3ulcb
- renesas,m3ulcb
- renesas,m3nulcb
- enum:
- renesas,r8a7795
- renesas,r8a7796
- renesas,r8a77965
- description: R-Car M3-N (R8A77965)
items:

19
Documentation/devicetree/bindings/arm/rockchip.yaml
View File

@@ -40,6 +40,11 @@ properties:
- const: asus,rk3288-tinker-s
- const: rockchip,rk3288
- description: Beelink A1
items:
- const: azw,beelink-a1
- const: rockchip,rk3328
- description: bq Curie 2 tablet
items:
- const: mundoreader,bq-curie2
@@ -82,6 +87,11 @@ properties:
- const: firefly,firefly-rk3399
- const: rockchip,rk3399
- description: Firefly ROC-RK3308-CC
items:
- const: firefly,roc-rk3308-cc
- const: rockchip,rk3308
- description: Firefly roc-rk3328-cc
items:
- const: firefly,roc-rk3328-cc
@@ -89,7 +99,9 @@ properties:
- description: Firefly ROC-RK3399-PC
items:
- const: firefly,roc-rk3399-pc
- enum:
- firefly,roc-rk3399-pc
- firefly,roc-rk3399-pc-mezzanine
- const: rockchip,rk3399
- description: FriendlyElec NanoPi4 series boards
@@ -464,6 +476,11 @@ properties:
- rockchip,rk3288-evb-rk808
- const: rockchip,rk3288
- description: Rockchip RK3308 Evaluation board
items:
- const: rockchip,rk3308-evb
- const: rockchip,rk3308
- description: Rockchip RK3328 Evaluation board
items:
- const: rockchip,rk3328-evb

5
Documentation/devicetree/bindings/arm/sunxi.yaml
View File

@@ -211,6 +211,11 @@ properties:
- const: friendlyarm,nanopi-a64
- const: allwinner,sun50i-a64
- description: FriendlyARM NanoPi Duo2
items:
- const: friendlyarm,nanopi-duo2
- const: allwinner,sun8i-h3
- description: FriendlyARM NanoPi M1
items:
- const: friendlyarm,nanopi-m1

1
Documentation/devicetree/bindings/arm/sunxi/sunxi-mbus.txt
View File

@@ -8,6 +8,7 @@ bus.
Required properties:
- compatible: Must be one of:
- allwinner,sun5i-a13-mbus
- allwinner,sun8i-h3-mbus
- reg: Offset and length of the register set for the controller
- clocks: phandle to the clock driving the controller
- dma-ranges: See section 2.3.9 of the DeviceTree Specification

5
Documentation/devicetree/bindings/clock/rockchip,px30-cru.txt
View File

@@ -10,6 +10,11 @@ Required Properties:
- compatible: CRU should be "rockchip,px30-cru"
- reg: physical base address of the controller and length of memory mapped
region.
- clocks: A list of phandle + clock-specifier pairs for the clocks listed
in clock-names
- clock-names: Should contain the following:
- "xin24m" for both PMUCRU and CRU
- "gpll" for CRU (sourced from PMUCRU)
- #clock-cells: should be 1.
- #reset-cells: should be 1.

88
Documentation/devicetree/bindings/crypto/allwinner,sun8i-ce.yaml Normal file
View File

@@ -0,0 +1,88 @@
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/crypto/allwinner,sun8i-ce.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Allwinner Crypto Engine driver
maintainers:
- Corentin Labbe <clabbe.montjoie@gmail.com>
properties:
compatible:
enum:
- allwinner,sun8i-h3-crypto
- allwinner,sun8i-r40-crypto
- allwinner,sun50i-a64-crypto
- allwinner,sun50i-h5-crypto
- allwinner,sun50i-h6-crypto
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
items:
- description: Bus clock
- description: Module clock
- description: MBus clock
minItems: 2
maxItems: 3
clock-names:
items:
- const: bus
- const: mod
- const: ram
minItems: 2
maxItems: 3
resets:
maxItems: 1
if:
properties:
compatible:
items:
const: allwinner,sun50i-h6-crypto
then:
properties:
clocks:
minItems: 3
clock-names:
minItems: 3
else:
properties:
clocks:
maxItems: 2
clock-names:
maxItems: 2
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
- resets
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/sun50i-a64-ccu.h>
#include <dt-bindings/reset/sun50i-a64-ccu.h>
crypto: crypto@1c15000 {
compatible = "allwinner,sun8i-h3-crypto";
reg = <0x01c15000 0x1000>;
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
clock-names = "bus", "mod";
resets = <&ccu RST_BUS_CE>;
};

0
Documentation/devicetree/bindings/lpddr2/lpddr2-timings.txt → Documentation/devicetree/bindings/ddr/lpddr2-timings.txt
View File

2
Documentation/devicetree/bindings/lpddr2/lpddr2.txt → Documentation/devicetree/bindings/ddr/lpddr2.txt
View File

@@ -36,7 +36,7 @@ Child nodes:
"lpddr2-timings" provides AC timing parameters of the device for
a given speed-bin. The user may provide the timings for as many
speed-bins as is required. Please see Documentation/devicetree/
bindings/lpddr2/lpddr2-timings.txt for more information on "lpddr2-timings"
bindings/ddr/lpddr2-timings.txt for more information on "lpddr2-timings"
Example:

58
Documentation/devicetree/bindings/ddr/lpddr3-timings.txt Normal file
View File

@@ -0,0 +1,58 @@
* AC timing parameters of LPDDR3 memories for a given speed-bin.
The structures are based on LPDDR2 and extended where needed.
Required properties:
- compatible : Should be "jedec,lpddr3-timings"
- min-freq : minimum DDR clock frequency for the speed-bin. Type is <u32>
- reg : maximum DDR clock frequency for the speed-bin. Type is <u32>
Optional properties:
The following properties represent AC timing parameters from the memory
data-sheet of the device for a given speed-bin. All these properties are
of type <u32> and the default unit is ps (pico seconds).
- tRFC
- tRRD
- tRPab
- tRPpb
- tRCD
- tRC
- tRAS
- tWTR
- tWR
- tRTP
- tW2W-C2C
- tR2R-C2C
- tFAW
- tXSR
- tXP
- tCKE
- tCKESR
- tMRD
Example:
timings_samsung_K3QF2F20DB_800mhz: lpddr3-timings@800000000 {
compatible = "jedec,lpddr3-timings";
reg = <800000000>; /* workaround: it shows max-freq */
min-freq = <100000000>;
tRFC = <65000>;
tRRD = <6000>;
tRPab = <12000>;
tRPpb = <12000>;
tRCD = <10000>;
tRC = <33750>;
tRAS = <23000>;
tWTR = <3750>;
tWR = <7500>;
tRTP = <3750>;
tW2W-C2C = <0>;
tR2R-C2C = <0>;
tFAW = <25000>;
tXSR = <70000>;
tXP = <3750>;
tCKE = <3750>;
tCKESR = <3750>;
tMRD = <7000>;
};

101
Documentation/devicetree/bindings/ddr/lpddr3.txt Normal file
View File

@@ -0,0 +1,101 @@
* LPDDR3 SDRAM memories compliant to JEDEC JESD209-3C
Required properties:
- compatible : Should be "<vendor>,<type>", and generic value "jedec,lpddr3".
Example "<vendor>,<type>" values:
"samsung,K3QF2F20DB"
- density : <u32> representing density in Mb (Mega bits)
- io-width : <u32> representing bus width. Possible values are 8, 16, 32, 64
- #address-cells: Must be set to 1
- #size-cells: Must be set to 0
Optional properties:
The following optional properties represent the minimum value of some AC
timing parameters of the DDR device in terms of number of clock cycles.
These values shall be obtained from the device data-sheet.
- tRFC-min-tck
- tRRD-min-tck
- tRPab-min-tck
- tRPpb-min-tck
- tRCD-min-tck
- tRC-min-tck
- tRAS-min-tck
- tWTR-min-tck
- tWR-min-tck
- tRTP-min-tck
- tW2W-C2C-min-tck
- tR2R-C2C-min-tck
- tWL-min-tck
- tDQSCK-min-tck
- tRL-min-tck
- tFAW-min-tck
- tXSR-min-tck
- tXP-min-tck
- tCKE-min-tck
- tCKESR-min-tck
- tMRD-min-tck
Child nodes:
- The lpddr3 node may have one or more child nodes of type "lpddr3-timings".
"lpddr3-timings" provides AC timing parameters of the device for
a given speed-bin. Please see Documentation/devicetree/
bindings/ddr/lpddr3-timings.txt for more information on "lpddr3-timings"
Example:
samsung_K3QF2F20DB: lpddr3 {
compatible = "samsung,K3QF2F20DB", "jedec,lpddr3";
density = <16384>;
io-width = <32>;
#address-cells = <1>;
#size-cells = <0>;
tRFC-min-tck = <17>;
tRRD-min-tck = <2>;
tRPab-min-tck = <2>;
tRPpb-min-tck = <2>;
tRCD-min-tck = <3>;
tRC-min-tck = <6>;
tRAS-min-tck = <5>;
tWTR-min-tck = <2>;
tWR-min-tck = <7>;
tRTP-min-tck = <2>;
tW2W-C2C-min-tck = <0>;
tR2R-C2C-min-tck = <0>;
tWL-min-tck = <8>;
tDQSCK-min-tck = <5>;
tRL-min-tck = <14>;
tFAW-min-tck = <5>;
tXSR-min-tck = <12>;
tXP-min-tck = <2>;
tCKE-min-tck = <2>;
tCKESR-min-tck = <2>;
tMRD-min-tck = <5>;
timings_samsung_K3QF2F20DB_800mhz: lpddr3-timings@800000000 {
compatible = "jedec,lpddr3-timings";
/* workaround: 'reg' shows max-freq */
reg = <800000000>;
min-freq = <100000000>;
tRFC = <65000>;
tRRD = <6000>;
tRPab = <12000>;
tRPpb = <12000>;
tRCD = <10000>;
tRC = <33750>;
tRAS = <23000>;
tWTR = <3750>;
tWR = <7500>;
tRTP = <3750>;
tW2W-C2C = <0>;
tR2R-C2C = <0>;
tFAW = <25000>;
tXSR = <70000>;
tXP = <3750>;
tCKE = <3750>;
tCKESR = <3750>;
tMRD = <7000>;
};
}

102
Documentation/devicetree/bindings/display/bridge/anx6345.yaml Normal file
View File

@@ -0,0 +1,102 @@
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/bridge/anx6345.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Analogix ANX6345 eDP Transmitter Device Tree Bindings
maintainers:
- Torsten Duwe <duwe@lst.de>
description: |
The ANX6345 is an ultra-low power Full-HD eDP transmitter designed for
portable devices.
properties:
compatible:
const: analogix,anx6345
reg:
maxItems: 1
description: base I2C address of the device
reset-gpios:
maxItems: 1
description: GPIO connected to active low reset
dvdd12-supply:
maxItems: 1
description: Regulator for 1.2V digital core power.
dvdd25-supply:
maxItems: 1
description: Regulator for 2.5V digital core power.
ports:
type: object
properties:
port@0:
type: object
description: |
Video port for LVTTL input
port@1:
type: object
description: |
Video port for eDP output (panel or connector).
May be omitted if EDID works reliably.
required:
- port@0
required:
- compatible
- reg
- reset-gpios
- dvdd12-supply
- dvdd25-supply
- ports
additionalProperties: false
examples:
- |
i2c0 {
#address-cells = <1>;
#size-cells = <0>;
anx6345: anx6345@38 {
compatible = "analogix,anx6345";
reg = <0x38>;
reset-gpios = <&pio42 1 /* GPIO_ACTIVE_LOW */>;
dvdd25-supply = <&reg_dldo2>;
dvdd12-supply = <&reg_fldo1>;
ports {
#address-cells = <1>;
#size-cells = <0>;
anx6345_in: port@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
anx6345_in_tcon0: endpoint@0 {
reg = <0>;
remote-endpoint = <&tcon0_out_anx6345>;
};
};
anx6345_out: port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
anx6345_out_panel: endpoint@0 {
reg = <0>;
remote-endpoint = <&panel_in_edp>;
};
};
};
};
};

5
Documentation/devicetree/bindings/gpu/arm,mali-midgard.yaml
View File

@@ -31,6 +31,10 @@ properties:
- amlogic,meson-gxm-mali
- realtek,rtd1295-mali
- const: arm,mali-t820
- items:
- enum:
- arm,juno-mali
- const: arm,mali-t624
- items:
- enum:
- rockchip,rk3288-mali
@@ -41,7 +45,6 @@ properties:
- rockchip,rk3399-mali
- const: arm,mali-t860
# "arm,mali-t624"
# "arm,mali-t830"
# "arm,mali-t880"

14
Documentation/devicetree/bindings/interrupt-controller/mrvl,intc.txt
View File

@@ -1,13 +1,17 @@
* Marvell MMP Interrupt controller
Required properties:
- compatible : Should be "mrvl,mmp-intc", "mrvl,mmp2-intc" or
"mrvl,mmp2-mux-intc"
- compatible : Should be
"mrvl,mmp-intc" on Marvel MMP,
"mrvl,mmp2-intc" along with "mrvl,mmp2-mux-intc" on MMP2 or
"marvell,mmp3-intc" with "mrvl,mmp2-mux-intc" on MMP3
- reg : Address and length of the register set of the interrupt controller.
If the interrupt controller is intc, address and length means the range
of the whole interrupt controller. If the interrupt controller is mux-intc,
address and length means one register. Since address of mux-intc is in the
range of intc. mux-intc is secondary interrupt controller.
of the whole interrupt controller. The "marvell,mmp3-intc" controller
also has a secondary range for the second CPU core. If the interrupt
controller is mux-intc, address and length means one register. Since
address of mux-intc is in the range of intc. mux-intc is secondary
interrupt controller.
- reg-names : Name of the register set of the interrupt controller. It's
only required in mux-intc interrupt controller.
- interrupts : Should be the port interrupt shared by mux interrupts. It's

84
Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt Normal file
View File

@@ -0,0 +1,84 @@
* Exynos5422 frequency and voltage scaling for Dynamic Memory Controller device
The Samsung Exynos5422 SoC has DMC (Dynamic Memory Controller) to which the DRAM
memory chips are connected. The driver is to monitor the controller in runtime
and switch frequency and voltage. To monitor the usage of the controller in
runtime, the driver uses the PPMU (Platform Performance Monitoring Unit), which
is able to measure the current load of the memory.
When 'userspace' governor is used for the driver, an application is able to
switch the DMC and memory frequency.
Required properties for DMC device for Exynos5422:
- compatible: Should be "samsung,exynos5422-dmc".
- clocks : list of clock specifiers, must contain an entry for each
required entry in clock-names for CLK_FOUT_SPLL, CLK_MOUT_SCLK_SPLL,
CLK_FF_DOUT_SPLL2, CLK_FOUT_BPLL, CLK_MOUT_BPLL, CLK_SCLK_BPLL,
CLK_MOUT_MX_MSPLL_CCORE, CLK_MOUT_MX_MSPLL_CCORE_PHY, CLK_MOUT_MCLK_CDREX,
- clock-names : should include "fout_spll", "mout_sclk_spll", "ff_dout_spll2",
"fout_bpll", "mout_bpll", "sclk_bpll", "mout_mx_mspll_ccore",
"mout_mclk_cdrex" entries
- devfreq-events : phandles for PPMU devices connected to this DMC.
- vdd-supply : phandle for voltage regulator which is connected.
- reg : registers of two CDREX controllers.
- operating-points-v2 : phandle for OPPs described in v2 definition.
- device-handle : phandle of the connected DRAM memory device. For more
information please refer to documentation file:
Documentation/devicetree/bindings/ddr/lpddr3.txt
- devfreq-events : phandles of the PPMU events used by the controller.
- samsung,syscon-clk : phandle of the clock register set used by the controller,
these registers are used for enabling a 'pause' feature and are not
exposed by clock framework but they must be used in a safe way.
The register offsets are in the driver code and specyfic for this SoC
type.
Optional properties for DMC device for Exynos5422:
- interrupt-parent : The parent interrupt controller.
- interrupts : Contains the IRQ line numbers for the DMC internal performance
event counters in DREX0 and DREX1 channels. Align with specification of the
interrupt line(s) in the interrupt-parent controller.
- interrupt-names : IRQ names "drex_0" and "drex_1", the order should be the
same as in the 'interrupts' list above.
Example:
ppmu_dmc0_0: ppmu@10d00000 {
compatible = "samsung,exynos-ppmu";
reg = <0x10d00000 0x2000>;
clocks = <&clock CLK_PCLK_PPMU_DREX0_0>;
clock-names = "ppmu";
events {
ppmu_event_dmc0_0: ppmu-event3-dmc0_0 {
event-name = "ppmu-event3-dmc0_0";
};
};
};
dmc: memory-controller@10c20000 {
compatible = "samsung,exynos5422-dmc";
reg = <0x10c20000 0x10000>, <0x10c30000 0x10000>;
clocks = <&clock CLK_FOUT_SPLL>,
<&clock CLK_MOUT_SCLK_SPLL>,
<&clock CLK_FF_DOUT_SPLL2>,
<&clock CLK_FOUT_BPLL>,
<&clock CLK_MOUT_BPLL>,
<&clock CLK_SCLK_BPLL>,
<&clock CLK_MOUT_MX_MSPLL_CCORE>,
<&clock CLK_MOUT_MCLK_CDREX>;
clock-names = "fout_spll",
"mout_sclk_spll",
"ff_dout_spll2",
"fout_bpll",
"mout_bpll",
"sclk_bpll",
"mout_mx_mspll_ccore",
"mout_mclk_cdrex";
operating-points-v2 = <&dmc_opp_table>;
devfreq-events = <&ppmu_event3_dmc0_0>, <&ppmu_event3_dmc0_1>,
<&ppmu_event3_dmc1_0>, <&ppmu_event3_dmc1_1>;
device-handle = <&samsung_K3QF2F20DB>;
vdd-supply = <&buck1_reg>;
samsung,syscon-clk = <&clock>;
interrupt-parent = <&combiner>;
interrupts = <16 0>, <16 1>;
interrupt-names = "drex_0", "drex_1";
};

152
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml Normal file
View File

@@ -0,0 +1,152 @@
# SPDX-License-Identifier: (GPL-2.0)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra124-mc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra124 SoC Memory Controller
maintainers:
- Jon Hunter <jonathanh@nvidia.com>
- Thierry Reding <thierry.reding@gmail.com>
description: |
Tegra124 SoC features a hybrid 2x32-bit / 1x64-bit memory controller.
These are interleaved to provide high performance with the load shared across
two memory channels. The Tegra124 Memory Controller handles memory requests
from internal clients and arbitrates among them to allocate memory bandwidth
for DDR3L and LPDDR3 SDRAMs.
properties:
compatible:
const: nvidia,tegra124-mc
reg:
maxItems: 1
clocks:
maxItems: 1
clock-names:
items:
- const: mc
interrupts:
maxItems: 1
"#reset-cells":
const: 1
"#iommu-cells":
const: 1
patternProperties:
"^emc-timings-[0-9]+$":
type: object
properties:
nvidia,ram-code:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Value of RAM_CODE this timing set is used for.
patternProperties:
"^timing-[0-9]+$":
type: object
properties:
clock-frequency:
description:
Memory clock rate in Hz.
minimum: 1000000
maximum: 1066000000
nvidia,emem-configuration:
$ref: /schemas/types.yaml#/definitions/uint32-array
description: |
Values to be written to the EMEM register block. See section
"15.6.1 MC Registers" in the TRM.
items:
- description: MC_EMEM_ARB_CFG
- description: MC_EMEM_ARB_OUTSTANDING_REQ
- description: MC_EMEM_ARB_TIMING_RCD
- description: MC_EMEM_ARB_TIMING_RP
- description: MC_EMEM_ARB_TIMING_RC
- description: MC_EMEM_ARB_TIMING_RAS
- description: MC_EMEM_ARB_TIMING_FAW
- description: MC_EMEM_ARB_TIMING_RRD
- description: MC_EMEM_ARB_TIMING_RAP2PRE
- description: MC_EMEM_ARB_TIMING_WAP2PRE
- description: MC_EMEM_ARB_TIMING_R2R
- description: MC_EMEM_ARB_TIMING_W2W
- description: MC_EMEM_ARB_TIMING_R2W
- description: MC_EMEM_ARB_TIMING_W2R
- description: MC_EMEM_ARB_DA_TURNS
- description: MC_EMEM_ARB_DA_COVERS
- description: MC_EMEM_ARB_MISC0
- description: MC_EMEM_ARB_MISC1
- description: MC_EMEM_ARB_RING1_THROTTLE
required:
- clock-frequency
- nvidia,emem-configuration
additionalProperties: false
required:
- nvidia,ram-code
additionalProperties: false
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
- "#reset-cells"
- "#iommu-cells"
additionalProperties: false
examples:
- |
memory-controller@70019000 {
compatible = "nvidia,tegra124-mc";
reg = <0x0 0x70019000 0x0 0x1000>;
clocks = <&tegra_car 32>;
clock-names = "mc";
interrupts = <0 77 4>;
#iommu-cells = <1>;
#reset-cells = <1>;
emc-timings-3 {
nvidia,ram-code = <3>;
timing-12750000 {
clock-frequency = <12750000>;
nvidia,emem-configuration = <
0x40040001 /* MC_EMEM_ARB_CFG */
0x8000000a /* MC_EMEM_ARB_OUTSTANDING_REQ */
0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
0x00000001 /* MC_EMEM_ARB_TIMING_RP */
0x00000002 /* MC_EMEM_ARB_TIMING_RC */
0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
0x00000002 /* MC_EMEM_ARB_TIMING_FAW */
0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */
0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
0x00000003 /* MC_EMEM_ARB_TIMING_R2R */
0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
0x00000003 /* MC_EMEM_ARB_TIMING_R2W */
0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
0x06030203 /* MC_EMEM_ARB_DA_TURNS */
0x000a0402 /* MC_EMEM_ARB_DA_COVERS */
0x77e30303 /* MC_EMEM_ARB_MISC0 */
0x70000f03 /* MC_EMEM_ARB_MISC1 */
0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
>;
};
};
};

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# SPDX-License-Identifier: (GPL-2.0)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra30-emc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra30 SoC External Memory Controller
maintainers:
- Dmitry Osipenko <digetx@gmail.com>
- Jon Hunter <jonathanh@nvidia.com>
- Thierry Reding <thierry.reding@gmail.com>
description: |
The EMC interfaces with the off-chip SDRAM to service the request stream
sent from Memory Controller. The EMC also has various performance-affecting
settings beyond the obvious SDRAM configuration parameters and initialization
settings. Tegra30 EMC supports multiple JEDEC standard protocols: LPDDR2,
LPDDR3, and DDR3.
properties:
compatible:
const: nvidia,tegra30-emc
reg:
maxItems: 1
clocks:
maxItems: 1
interrupts:
maxItems: 1
nvidia,memory-controller:
$ref: /schemas/types.yaml#/definitions/phandle
description:
Phandle of the Memory Controller node.
patternProperties:
"^emc-timings-[0-9]+$":
type: object
properties:
nvidia,ram-code:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Value of RAM_CODE this timing set is used for.
patternProperties:
"^timing-[0-9]+$":
type: object
properties:
clock-frequency:
description:
Memory clock rate in Hz.
minimum: 1000000
maximum: 900000000
nvidia,emc-auto-cal-interval:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Pad calibration interval in microseconds.
minimum: 0
maximum: 2097151
nvidia,emc-mode-1:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Mode Register 1.
nvidia,emc-mode-2:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Mode Register 2.
nvidia,emc-mode-reset:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Mode Register 0.
nvidia,emc-zcal-cnt-long:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Number of EMC clocks to wait before issuing any commands after
sending ZCAL_MRW_CMD.
minimum: 0
maximum: 1023
nvidia,emc-cfg-dyn-self-ref:
type: boolean
description:
Dynamic self-refresh enabled.
nvidia,emc-cfg-periodic-qrst:
type: boolean
description:
FBIO "read" FIFO periodic resetting enabled.
nvidia,emc-configuration:
$ref: /schemas/types.yaml#/definitions/uint32-array
description:
EMC timing characterization data. These are the registers
(see section "18.13.2 EMC Registers" in the TRM) whose values
need to be specified, according to the board documentation.
items:
- description: EMC_RC
- description: EMC_RFC
- description: EMC_RAS
- description: EMC_RP
- description: EMC_R2W
- description: EMC_W2R
- description: EMC_R2P
- description: EMC_W2P
- description: EMC_RD_RCD
- description: EMC_WR_RCD
- description: EMC_RRD
- description: EMC_REXT
- description: EMC_WEXT
- description: EMC_WDV
- description: EMC_QUSE
- description: EMC_QRST
- description: EMC_QSAFE
- description: EMC_RDV
- description: EMC_REFRESH
- description: EMC_BURST_REFRESH_NUM
- description: EMC_PRE_REFRESH_REQ_CNT
- description: EMC_PDEX2WR
- description: EMC_PDEX2RD
- description: EMC_PCHG2PDEN
- description: EMC_ACT2PDEN
- description: EMC_AR2PDEN
- description: EMC_RW2PDEN
- description: EMC_TXSR
- description: EMC_TXSRDLL
- description: EMC_TCKE
- description: EMC_TFAW
- description: EMC_TRPAB
- description: EMC_TCLKSTABLE
- description: EMC_TCLKSTOP
- description: EMC_TREFBW
- description: EMC_QUSE_EXTRA
- description: EMC_FBIO_CFG6
- description: EMC_ODT_WRITE
- description: EMC_ODT_READ
- description: EMC_FBIO_CFG5
- description: EMC_CFG_DIG_DLL
- description: EMC_CFG_DIG_DLL_PERIOD
- description: EMC_DLL_XFORM_DQS0
- description: EMC_DLL_XFORM_DQS1
- description: EMC_DLL_XFORM_DQS2
- description: EMC_DLL_XFORM_DQS3
- description: EMC_DLL_XFORM_DQS4
- description: EMC_DLL_XFORM_DQS5
- description: EMC_DLL_XFORM_DQS6
- description: EMC_DLL_XFORM_DQS7
- description: EMC_DLL_XFORM_QUSE0
- description: EMC_DLL_XFORM_QUSE1
- description: EMC_DLL_XFORM_QUSE2
- description: EMC_DLL_XFORM_QUSE3
- description: EMC_DLL_XFORM_QUSE4
- description: EMC_DLL_XFORM_QUSE5
- description: EMC_DLL_XFORM_QUSE6
- description: EMC_DLL_XFORM_QUSE7
- description: EMC_DLI_TRIM_TXDQS0
- description: EMC_DLI_TRIM_TXDQS1
- description: EMC_DLI_TRIM_TXDQS2
- description: EMC_DLI_TRIM_TXDQS3
- description: EMC_DLI_TRIM_TXDQS4
- description: EMC_DLI_TRIM_TXDQS5
- description: EMC_DLI_TRIM_TXDQS6
- description: EMC_DLI_TRIM_TXDQS7
- description: EMC_DLL_XFORM_DQ0
- description: EMC_DLL_XFORM_DQ1
- description: EMC_DLL_XFORM_DQ2
- description: EMC_DLL_XFORM_DQ3
- description: EMC_XM2CMDPADCTRL
- description: EMC_XM2DQSPADCTRL2
- description: EMC_XM2DQPADCTRL2
- description: EMC_XM2CLKPADCTRL
- description: EMC_XM2COMPPADCTRL
- description: EMC_XM2VTTGENPADCTRL
- description: EMC_XM2VTTGENPADCTRL2
- description: EMC_XM2QUSEPADCTRL
- description: EMC_XM2DQSPADCTRL3
- description: EMC_CTT_TERM_CTRL
- description: EMC_ZCAL_INTERVAL
- description: EMC_ZCAL_WAIT_CNT
- description: EMC_MRS_WAIT_CNT
- description: EMC_AUTO_CAL_CONFIG
- description: EMC_CTT
- description: EMC_CTT_DURATION
- description: EMC_DYN_SELF_REF_CONTROL
- description: EMC_FBIO_SPARE
- description: EMC_CFG_RSV
required:
- clock-frequency
- nvidia,emc-auto-cal-interval
- nvidia,emc-mode-1
- nvidia,emc-mode-2
- nvidia,emc-mode-reset
- nvidia,emc-zcal-cnt-long
- nvidia,emc-configuration
additionalProperties: false
required:
- nvidia,ram-code
additionalProperties: false
required:
- compatible
- reg
- interrupts
- clocks
- nvidia,memory-controller
additionalProperties: false
examples:
- |
external-memory-controller@7000f400 {
compatible = "nvidia,tegra30-emc";
reg = <0x7000f400 0x400>;
interrupts = <0 78 4>;
clocks = <&tegra_car 57>;
nvidia,memory-controller = <&mc>;
emc-timings-1 {
nvidia,ram-code = <1>;
timing-667000000 {
clock-frequency = <667000000>;
nvidia,emc-auto-cal-interval = <0x001fffff>;
nvidia,emc-mode-1 = <0x80100002>;
nvidia,emc-mode-2 = <0x80200018>;
nvidia,emc-mode-reset = <0x80000b71>;
nvidia,emc-zcal-cnt-long = <0x00000040>;
nvidia,emc-cfg-periodic-qrst;
nvidia,emc-configuration = <
0x00000020 /* EMC_RC */
0x0000006a /* EMC_RFC */
0x00000017 /* EMC_RAS */
0x00000007 /* EMC_RP */
0x00000005 /* EMC_R2W */
0x0000000c /* EMC_W2R */
0x00000003 /* EMC_R2P */
0x00000011 /* EMC_W2P */
0x00000007 /* EMC_RD_RCD */
0x00000007 /* EMC_WR_RCD */
0x00000002 /* EMC_RRD */
0x00000001 /* EMC_REXT */
0x00000000 /* EMC_WEXT */
0x00000007 /* EMC_WDV */
0x0000000a /* EMC_QUSE */
0x00000009 /* EMC_QRST */
0x0000000b /* EMC_QSAFE */
0x00000011 /* EMC_RDV */
0x00001412 /* EMC_REFRESH */
0x00000000 /* EMC_BURST_REFRESH_NUM */
0x00000504 /* EMC_PRE_REFRESH_REQ_CNT */
0x00000002 /* EMC_PDEX2WR */
0x0000000e /* EMC_PDEX2RD */
0x00000001 /* EMC_PCHG2PDEN */
0x00000000 /* EMC_ACT2PDEN */
0x0000000c /* EMC_AR2PDEN */
0x00000016 /* EMC_RW2PDEN */
0x00000072 /* EMC_TXSR */
0x00000200 /* EMC_TXSRDLL */
0x00000005 /* EMC_TCKE */
0x00000015 /* EMC_TFAW */
0x00000000 /* EMC_TRPAB */
0x00000006 /* EMC_TCLKSTABLE */
0x00000007 /* EMC_TCLKSTOP */
0x00001453 /* EMC_TREFBW */
0x0000000b /* EMC_QUSE_EXTRA */
0x00000006 /* EMC_FBIO_CFG6 */
0x00000000 /* EMC_ODT_WRITE */
0x00000000 /* EMC_ODT_READ */
0x00005088 /* EMC_FBIO_CFG5 */
0xf00b0191 /* EMC_CFG_DIG_DLL */
0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
0x00000008 /* EMC_DLL_XFORM_DQS0 */
0x00000008 /* EMC_DLL_XFORM_DQS1 */
0x00000008 /* EMC_DLL_XFORM_DQS2 */
0x00000008 /* EMC_DLL_XFORM_DQS3 */
0x0000000a /* EMC_DLL_XFORM_DQS4 */
0x0000000a /* EMC_DLL_XFORM_DQS5 */
0x0000000a /* EMC_DLL_XFORM_DQS6 */
0x0000000a /* EMC_DLL_XFORM_DQS7 */
0x00018000 /* EMC_DLL_XFORM_QUSE0 */
0x00018000 /* EMC_DLL_XFORM_QUSE1 */
0x00018000 /* EMC_DLL_XFORM_QUSE2 */
0x00018000 /* EMC_DLL_XFORM_QUSE3 */
0x00000000 /* EMC_DLL_XFORM_QUSE4 */
0x00000000 /* EMC_DLL_XFORM_QUSE5 */
0x00000000 /* EMC_DLL_XFORM_QUSE6 */
0x00000000 /* EMC_DLL_XFORM_QUSE7 */
0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
0x0000000a /* EMC_DLL_XFORM_DQ0 */
0x0000000a /* EMC_DLL_XFORM_DQ1 */
0x0000000a /* EMC_DLL_XFORM_DQ2 */
0x0000000a /* EMC_DLL_XFORM_DQ3 */
0x000002a0 /* EMC_XM2CMDPADCTRL */
0x0800013d /* EMC_XM2DQSPADCTRL2 */
0x22220000 /* EMC_XM2DQPADCTRL2 */
0x77fff884 /* EMC_XM2CLKPADCTRL */
0x01f1f501 /* EMC_XM2COMPPADCTRL */
0x07077404 /* EMC_XM2VTTGENPADCTRL */
0x54000000 /* EMC_XM2VTTGENPADCTRL2 */
0x080001e8 /* EMC_XM2QUSEPADCTRL */
0x0c000021 /* EMC_XM2DQSPADCTRL3 */
0x00000802 /* EMC_CTT_TERM_CTRL */
0x00020000 /* EMC_ZCAL_INTERVAL */
0x00000100 /* EMC_ZCAL_WAIT_CNT */
0x0155000c /* EMC_MRS_WAIT_CNT */
0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
0x00000000 /* EMC_CTT */
0x00000000 /* EMC_CTT_DURATION */
0x800028a5 /* EMC_DYN_SELF_REF_CONTROL */
0xe8000000 /* EMC_FBIO_SPARE */
0xff00ff49 /* EMC_CFG_RSV */
>;
};
};
};

123
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@@ -1,123 +0,0 @@
NVIDIA Tegra Memory Controller device tree bindings
===================================================
memory-controller node
----------------------
Required properties:
- compatible: Should be "nvidia,tegra<chip>-mc"
- reg: Physical base address and length of the controller's registers.
- clocks: Must contain an entry for each entry in clock-names.
See ../clocks/clock-bindings.txt for details.
- clock-names: Must include the following entries:
- mc: the module's clock input
- interrupts: The interrupt outputs from the controller.
- #reset-cells : Should be 1. This cell represents memory client module ID.
The assignments may be found in header file <dt-bindings/memory/tegra30-mc.h>
or in the TRM documentation.
Required properties for Tegra30, Tegra114, Tegra124, Tegra132 and Tegra210:
- #iommu-cells: Should be 1. The single cell of the IOMMU specifier defines
the SWGROUP of the master.
This device implements an IOMMU that complies with the generic IOMMU binding.
See ../iommu/iommu.txt for details.
emc-timings subnode
-------------------
The node should contain a "emc-timings" subnode for each supported RAM type (see field RAM_CODE in
register PMC_STRAPPING_OPT_A).
Required properties for "emc-timings" nodes :
- nvidia,ram-code : Should contain the value of RAM_CODE this timing set is used for.
timing subnode
--------------
Each "emc-timings" node should contain a subnode for every supported EMC clock rate.
Required properties for timing nodes :
- clock-frequency : Should contain the memory clock rate in Hz.
- nvidia,emem-configuration : Values to be written to the EMEM register block. For the Tegra124 SoC
(see section "15.6.1 MC Registers" in the TRM), these are the registers whose values need to be
specified, according to the board documentation:
MC_EMEM_ARB_CFG
MC_EMEM_ARB_OUTSTANDING_REQ
MC_EMEM_ARB_TIMING_RCD
MC_EMEM_ARB_TIMING_RP
MC_EMEM_ARB_TIMING_RC
MC_EMEM_ARB_TIMING_RAS
MC_EMEM_ARB_TIMING_FAW
MC_EMEM_ARB_TIMING_RRD
MC_EMEM_ARB_TIMING_RAP2PRE
MC_EMEM_ARB_TIMING_WAP2PRE
MC_EMEM_ARB_TIMING_R2R
MC_EMEM_ARB_TIMING_W2W
MC_EMEM_ARB_TIMING_R2W
MC_EMEM_ARB_TIMING_W2R
MC_EMEM_ARB_DA_TURNS
MC_EMEM_ARB_DA_COVERS
MC_EMEM_ARB_MISC0
MC_EMEM_ARB_MISC1
MC_EMEM_ARB_RING1_THROTTLE
Example SoC include file:
/ {
mc: memory-controller@70019000 {
compatible = "nvidia,tegra124-mc";
reg = <0x0 0x70019000 0x0 0x1000>;
clocks = <&tegra_car TEGRA124_CLK_MC>;
clock-names = "mc";
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
#iommu-cells = <1>;
#reset-cells = <1>;
};
sdhci@700b0000 {
compatible = "nvidia,tegra124-sdhci";
...
iommus = <&mc TEGRA_SWGROUP_SDMMC1A>;
resets = <&mc TEGRA124_MC_RESET_SDMMC1>;
};
};
Example board file:
/ {
memory-controller@70019000 {
emc-timings-3 {
nvidia,ram-code = <3>;
timing-12750000 {
clock-frequency = <12750000>;
nvidia,emem-configuration = <
0x40040001 /* MC_EMEM_ARB_CFG */
0x8000000a /* MC_EMEM_ARB_OUTSTANDING_REQ */
0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
0x00000001 /* MC_EMEM_ARB_TIMING_RP */
0x00000002 /* MC_EMEM_ARB_TIMING_RC */
0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
0x00000002 /* MC_EMEM_ARB_TIMING_FAW */
0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */
0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
0x00000003 /* MC_EMEM_ARB_TIMING_R2R */
0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
0x00000003 /* MC_EMEM_ARB_TIMING_R2W */
0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
0x06030203 /* MC_EMEM_ARB_DA_TURNS */
0x000a0402 /* MC_EMEM_ARB_DA_COVERS */
0x77e30303 /* MC_EMEM_ARB_MISC0 */
0x70000f03 /* MC_EMEM_ARB_MISC1 */
0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
>;
};
};
};
};

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# SPDX-License-Identifier: (GPL-2.0)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra30-mc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra30 SoC Memory Controller
maintainers:
- Dmitry Osipenko <digetx@gmail.com>
- Jon Hunter <jonathanh@nvidia.com>
- Thierry Reding <thierry.reding@gmail.com>
description: |
Tegra30 Memory Controller architecturally consists of the following parts:
Arbitration Domains, which can handle a single request or response per
clock from a group of clients. Typically, a system has a single Arbitration
Domain, but an implementation may divide the client space into multiple
Arbitration Domains to increase the effective system bandwidth.
Protocol Arbiter, which manage a related pool of memory devices. A system
may have a single Protocol Arbiter or multiple Protocol Arbiters.
Memory Crossbar, which routes request and responses between Arbitration
Domains and Protocol Arbiters. In the simplest version of the system, the
Memory Crossbar is just a pass through between a single Arbitration Domain
and a single Protocol Arbiter.
Global Resources, which include things like configuration registers which
are shared across the Memory Subsystem.
The Tegra30 Memory Controller handles memory requests from internal clients
and arbitrates among them to allocate memory bandwidth for DDR3L and LPDDR2
SDRAMs.
properties:
compatible:
const: nvidia,tegra30-mc
reg:
maxItems: 1
clocks:
maxItems: 1
clock-names:
items:
- const: mc
interrupts:
maxItems: 1
"#reset-cells":
const: 1
"#iommu-cells":
const: 1
patternProperties:
"^emc-timings-[0-9]+$":
type: object
properties:
nvidia,ram-code:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Value of RAM_CODE this timing set is used for.
patternProperties:
"^timing-[0-9]+$":
type: object
properties:
clock-frequency:
description:
Memory clock rate in Hz.
minimum: 1000000
maximum: 900000000
nvidia,emem-configuration:
$ref: /schemas/types.yaml#/definitions/uint32-array
description: |
Values to be written to the EMEM register block. See section
"18.13.1 MC Registers" in the TRM.
items:
- description: MC_EMEM_ARB_CFG
- description: MC_EMEM_ARB_OUTSTANDING_REQ
- description: MC_EMEM_ARB_TIMING_RCD
- description: MC_EMEM_ARB_TIMING_RP
- description: MC_EMEM_ARB_TIMING_RC
- description: MC_EMEM_ARB_TIMING_RAS
- description: MC_EMEM_ARB_TIMING_FAW
- description: MC_EMEM_ARB_TIMING_RRD
- description: MC_EMEM_ARB_TIMING_RAP2PRE
- description: MC_EMEM_ARB_TIMING_WAP2PRE
- description: MC_EMEM_ARB_TIMING_R2R
- description: MC_EMEM_ARB_TIMING_W2W
- description: MC_EMEM_ARB_TIMING_R2W
- description: MC_EMEM_ARB_TIMING_W2R
- description: MC_EMEM_ARB_DA_TURNS
- description: MC_EMEM_ARB_DA_COVERS
- description: MC_EMEM_ARB_MISC0
- description: MC_EMEM_ARB_RING1_THROTTLE
required:
- clock-frequency
- nvidia,emem-configuration
additionalProperties: false
required:
- nvidia,ram-code
additionalProperties: false
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
- "#reset-cells"
- "#iommu-cells"
additionalProperties: false
examples:
- |
memory-controller@7000f000 {
compatible = "nvidia,tegra30-mc";
reg = <0x7000f000 0x400>;
clocks = <&tegra_car 32>;
clock-names = "mc";
interrupts = <0 77 4>;
#iommu-cells = <1>;
#reset-cells = <1>;
emc-timings-1 {
nvidia,ram-code = <1>;
timing-667000000 {
clock-frequency = <667000000>;
nvidia,emem-configuration = <
0x0000000a /* MC_EMEM_ARB_CFG */
0xc0000079 /* MC_EMEM_ARB_OUTSTANDING_REQ */
0x00000003 /* MC_EMEM_ARB_TIMING_RCD */
0x00000004 /* MC_EMEM_ARB_TIMING_RP */
0x00000010 /* MC_EMEM_ARB_TIMING_RC */
0x0000000b /* MC_EMEM_ARB_TIMING_RAS */
0x0000000a /* MC_EMEM_ARB_TIMING_FAW */
0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
0x0000000b /* MC_EMEM_ARB_TIMING_WAP2PRE */
0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
0x00000004 /* MC_EMEM_ARB_TIMING_R2W */
0x00000008 /* MC_EMEM_ARB_TIMING_W2R */
0x08040202 /* MC_EMEM_ARB_DA_TURNS */
0x00130b10 /* MC_EMEM_ARB_DA_COVERS */
0x70ea1f11 /* MC_EMEM_ARB_MISC0 */
0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
>;
};
};
};

13
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Marvell MMP3 USB PHY
--------------------
Required properties:
- compatible: must be "marvell,mmp3-usb-phy"
- #phy-cells: must be 0
Example:
usb-phy: usb-phy@d4207000 {
compatible = "marvell,mmp3-usb-phy";
reg = <0xd4207000 0x40>;
#phy-cells = <0>;
};

2
Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt
View File

@@ -12,6 +12,7 @@ Required properties:
- "renesas,r8a7745-sysc" (RZ/G1E)
- "renesas,r8a77470-sysc" (RZ/G1C)
- "renesas,r8a774a1-sysc" (RZ/G2M)
- "renesas,r8a774b1-sysc" (RZ/G2N)
- "renesas,r8a774c0-sysc" (RZ/G2E)
- "renesas,r8a7779-sysc" (R-Car H1)
- "renesas,r8a7790-sysc" (R-Car H2)
@@ -21,6 +22,7 @@ Required properties:
- "renesas,r8a7794-sysc" (R-Car E2)
- "renesas,r8a7795-sysc" (R-Car H3)
- "renesas,r8a7796-sysc" (R-Car M3-W)
- "renesas,r8a77961-sysc" (R-Car M3-W+)
- "renesas,r8a77965-sysc" (R-Car M3-N)
- "renesas,r8a77970-sysc" (R-Car V3M)
- "renesas,r8a77980-sysc" (R-Car V3H)

65
Documentation/devicetree/bindings/regulator/nvidia,tegra-regulators-coupling.txt Normal file
View File

@@ -0,0 +1,65 @@
NVIDIA Tegra Regulators Coupling
================================
NVIDIA Tegra SoC's have a mandatory voltage-coupling between regulators.
Thus on Tegra20 there are 3 coupled regulators and on NVIDIA Tegra30
there are 2.
Tegra20 voltage coupling
------------------------
On Tegra20 SoC's there are 3 coupled regulators: CORE, RTC and CPU.
The CORE and RTC voltages shall be in a range of 170mV from each other
and they both shall be higher than the CPU voltage by at least 120mV.
Tegra30 voltage coupling
------------------------
On Tegra30 SoC's there are 2 coupled regulators: CORE and CPU. The CORE
and CPU voltages shall be in a range of 300mV from each other and CORE
voltage shall be higher than the CPU by N mV, where N depends on the CPU
voltage.
Required properties:
- nvidia,tegra-core-regulator: Boolean property that designates regulator
as the "Core domain" voltage regulator.
- nvidia,tegra-rtc-regulator: Boolean property that designates regulator
as the "RTC domain" voltage regulator.
- nvidia,tegra-cpu-regulator: Boolean property that designates regulator
as the "CPU domain" voltage regulator.
Example:
pmic {
regulators {
core_vdd_reg: core {
regulator-name = "vdd_core";
regulator-min-microvolt = <950000>;
regulator-max-microvolt = <1300000>;
regulator-coupled-with = <&rtc_vdd_reg &cpu_vdd_reg>;
regulator-coupled-max-spread = <170000 550000>;
nvidia,tegra-core-regulator;
};
rtc_vdd_reg: rtc {
regulator-name = "vdd_rtc";
regulator-min-microvolt = <950000>;
regulator-max-microvolt = <1300000>;
regulator-coupled-with = <&core_vdd_reg &cpu_vdd_reg>;
regulator-coupled-max-spread = <170000 550000>;
nvidia,tegra-rtc-regulator;
};
cpu_vdd_reg: cpu {
regulator-name = "vdd_cpu";
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <1125000>;
regulator-coupled-with = <&core_vdd_reg &rtc_vdd_reg>;
regulator-coupled-max-spread = <550000 550000>;
nvidia,tegra-cpu-regulator;
};
};
};

2
Documentation/devicetree/bindings/reset/renesas,rst.txt
View File

@@ -20,6 +20,7 @@ Required properties:
- "renesas,r8a7745-rst" (RZ/G1E)
- "renesas,r8a77470-rst" (RZ/G1C)
- "renesas,r8a774a1-rst" (RZ/G2M)
- "renesas,r8a774b1-rst" (RZ/G2N)
- "renesas,r8a774c0-rst" (RZ/G2E)
- "renesas,r8a7778-reset-wdt" (R-Car M1A)
- "renesas,r8a7779-reset-wdt" (R-Car H1)
@@ -30,6 +31,7 @@ Required properties:
- "renesas,r8a7794-rst" (R-Car E2)
- "renesas,r8a7795-rst" (R-Car H3)
- "renesas,r8a7796-rst" (R-Car M3-W)
- "renesas,r8a77961-rst" (R-Car M3-W+)
- "renesas,r8a77965-rst" (R-Car M3-N)
- "renesas,r8a77970-rst" (R-Car V3M)
- "renesas,r8a77980-rst" (R-Car V3H)

18
Documentation/devicetree/bindings/soc/rockchip/grf.txt
View File

@@ -10,6 +10,12 @@ From RK3368 SoCs, the GRF is divided into two sections,
On RK3328 SoCs, the GRF adds a section for USB2PHYGRF,
ON RK3308 SoC, the GRF is divided into four sections:
- GRF, used for general non-secure system,
- SGRF, used for general secure system,
- DETECTGRF, used for audio codec system,
- COREGRF, used for pvtm,
Required Properties:
- compatible: GRF should be one of the following:
@@ -19,19 +25,25 @@ Required Properties:
- "rockchip,rk3188-grf", "syscon": for rk3188
- "rockchip,rk3228-grf", "syscon": for rk3228
- "rockchip,rk3288-grf", "syscon": for rk3288
- "rockchip,rk3308-grf", "syscon": for rk3308
- "rockchip,rk3328-grf", "syscon": for rk3328
- "rockchip,rk3368-grf", "syscon": for rk3368
- "rockchip,rk3399-grf", "syscon": for rk3399
- "rockchip,rv1108-grf", "syscon": for rv1108
- compatible: DETECTGRF should be one of the following:
- "rockchip,rk3308-detect-grf", "syscon": for rk3308
- compatilbe: COREGRF should be one of the following:
- "rockchip,rk3308-core-grf", "syscon": for rk3308
- compatible: PMUGRF should be one of the following:
- "rockchip,px30-pmugrf", "syscon": for px30
- "rockchip,rk3368-pmugrf", "syscon": for rk3368
- "rockchip,rk3399-pmugrf", "syscon": for rk3399
- compatible: SGRF should be one of the following
- compatible: SGRF should be one of the following:
- "rockchip,rk3288-sgrf", "syscon": for rk3288
- compatible: USB2PHYGRF should be one of the followings
- compatible: USB2PHYGRF should be one of the following:
- "rockchip,px30-usb2phy-grf", "syscon": for px30
- "rockchip,rk3328-usb2phy-grf", "syscon": for rk3328
- compatible: USBGRF should be one of the following
- compatible: USBGRF should be one of the following:
- "rockchip,rv1108-usbgrf", "syscon": for rv1108
- reg: physical base address of the controller and length of memory mapped
region.

1
Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt
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@@ -21,6 +21,7 @@ Required properties:
* "mediatek,mt6577-timer" for MT6577 and all above compatible timers (GPT)
For those SoCs that use SYST
* "mediatek,mt8183-timer" for MT8183 compatible timers (SYST)
* "mediatek,mt7629-timer" for MT7629 compatible timers (SYST)
* "mediatek,mt6765-timer" for MT6765 and all above compatible timers (SYST)

1
Documentation/devicetree/bindings/timer/renesas,tmu.txt
View File

@@ -10,6 +10,7 @@ Required Properties:
- compatible: must contain one or more of the following:
- "renesas,tmu-r8a7740" for the r8a7740 TMU
- "renesas,tmu-r8a774a1" for the r8a774A1 TMU
- "renesas,tmu-r8a774c0" for the r8a774C0 TMU
- "renesas,tmu-r8a7778" for the r8a7778 TMU
- "renesas,tmu-r8a7779" for the r8a7779 TMU

4
Documentation/devicetree/bindings/vendor-prefixes.yaml
View File

@@ -707,6 +707,8 @@ patternProperties:
description: Ortus Technology Co., Ltd.
"^osddisplays,.*":
description: OSD Displays
"^overkiz,.*":
description: Overkiz SAS
"^ovti,.*":
description: OmniVision Technologies
"^oxsemi,.*":
@@ -990,6 +992,8 @@ patternProperties:
description: Ubiquiti Networks
"^udoo,.*":
description: Udoo
"^ugoos,.*":
description: Ugoos Industrial Co., Ltd.
"^uniwest,.*":
description: United Western Technologies Corp (UniWest)
"^upisemi,.*":