[MIPS] Remove support for NEC DDB5074.
As warned several times before. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Ralf Baechle
@@ -56,10 +56,7 @@ void __init prom_init(void)
|
||||
|
||||
mips_machgroup = MACH_GROUP_NEC_DDB;
|
||||
|
||||
#if defined(CONFIG_DDB5074)
|
||||
mips_machtype = MACH_NEC_DDB5074;
|
||||
add_memory_region(0, DDB_SDRAM_SIZE, BOOT_MEM_RAM);
|
||||
#elif defined(CONFIG_DDB5476)
|
||||
#if defined(CONFIG_DDB5476)
|
||||
mips_machtype = MACH_NEC_DDB5476;
|
||||
add_memory_region(0, DDB_SDRAM_SIZE, BOOT_MEM_RAM);
|
||||
#elif defined(CONFIG_DDB5477)
|
||||
|
||||
@@ -1,8 +0,0 @@
|
||||
#
|
||||
# Makefile for the NEC DDB Vrc-5074 specific kernel interface routines
|
||||
# under Linux.
|
||||
#
|
||||
|
||||
obj-y += setup.o irq.o nile4_pic.o
|
||||
|
||||
EXTRA_AFLAGS := $(CFLAGS)
|
||||
@@ -1,169 +0,0 @@
|
||||
/*
|
||||
* arch/mips/ddb5074/irq.c -- NEC DDB Vrc-5074 interrupt routines
|
||||
*
|
||||
* Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
|
||||
* Sony Software Development Center Europe (SDCE), Brussels
|
||||
*/
|
||||
#include <linux/init.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/signal.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/ioport.h>
|
||||
|
||||
#include <asm/i8259.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/irq_cpu.h>
|
||||
#include <asm/ptrace.h>
|
||||
#include <asm/nile4.h>
|
||||
#include <asm/ddb5xxx/ddb5xxx.h>
|
||||
#include <asm/ddb5xxx/ddb5074.h>
|
||||
|
||||
|
||||
static struct irqaction irq_cascade = { no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL };
|
||||
|
||||
#define M1543_PNP_CONFIG 0x03f0 /* PnP Config Port */
|
||||
#define M1543_PNP_INDEX 0x03f0 /* PnP Index Port */
|
||||
#define M1543_PNP_DATA 0x03f1 /* PnP Data Port */
|
||||
|
||||
#define M1543_PNP_ALT_CONFIG 0x0370 /* Alternative PnP Config Port */
|
||||
#define M1543_PNP_ALT_INDEX 0x0370 /* Alternative PnP Index Port */
|
||||
#define M1543_PNP_ALT_DATA 0x0371 /* Alternative PnP Data Port */
|
||||
|
||||
#define M1543_INT1_MASTER_CTRL 0x0020 /* INT_1 (master) Control Register */
|
||||
#define M1543_INT1_MASTER_MASK 0x0021 /* INT_1 (master) Mask Register */
|
||||
|
||||
#define M1543_INT1_SLAVE_CTRL 0x00a0 /* INT_1 (slave) Control Register */
|
||||
#define M1543_INT1_SLAVE_MASK 0x00a1 /* INT_1 (slave) Mask Register */
|
||||
|
||||
#define M1543_INT1_MASTER_ELCR 0x04d0 /* INT_1 (master) Edge/Level Control */
|
||||
#define M1543_INT1_SLAVE_ELCR 0x04d1 /* INT_1 (slave) Edge/Level Control */
|
||||
|
||||
|
||||
static void m1543_irq_setup(void)
|
||||
{
|
||||
/*
|
||||
* The ALI M1543 has 13 interrupt inputs, IRQ1..IRQ13. Not all
|
||||
* the possible IO sources in the M1543 are in use by us. We will
|
||||
* use the following mapping:
|
||||
*
|
||||
* IRQ1 - keyboard (default set by M1543)
|
||||
* IRQ3 - reserved for UART B (default set by M1543) (note that
|
||||
* the schematics for the DDB Vrc-5074 board seem to
|
||||
* indicate that IRQ3 is connected to the DS1386
|
||||
* watchdog timer interrupt output so we might have
|
||||
* a conflict)
|
||||
* IRQ4 - reserved for UART A (default set by M1543)
|
||||
* IRQ5 - parallel (default set by M1543)
|
||||
* IRQ8 - DS1386 time of day (RTC) interrupt
|
||||
* IRQ12 - mouse
|
||||
*/
|
||||
|
||||
/*
|
||||
* Assing mouse interrupt to IRQ12
|
||||
*/
|
||||
|
||||
/* Enter configuration mode */
|
||||
outb(0x51, M1543_PNP_CONFIG);
|
||||
outb(0x23, M1543_PNP_CONFIG);
|
||||
|
||||
/* Select logical device 7 (Keyboard) */
|
||||
outb(0x07, M1543_PNP_INDEX);
|
||||
outb(0x07, M1543_PNP_DATA);
|
||||
|
||||
/* Select IRQ12 */
|
||||
outb(0x72, M1543_PNP_INDEX);
|
||||
outb(0x0c, M1543_PNP_DATA);
|
||||
|
||||
outb(0x30, M1543_PNP_INDEX);
|
||||
printk("device 7, 0x30: %02x\n",inb(M1543_PNP_DATA));
|
||||
|
||||
outb(0x70, M1543_PNP_INDEX);
|
||||
printk("device 7, 0x70: %02x\n",inb(M1543_PNP_DATA));
|
||||
|
||||
/* Leave configration mode */
|
||||
outb(0xbb, M1543_PNP_CONFIG);
|
||||
|
||||
|
||||
}
|
||||
|
||||
static void ddb_local0_irqdispatch(struct pt_regs *regs)
|
||||
{
|
||||
u32 mask;
|
||||
int nile4_irq;
|
||||
|
||||
mask = nile4_get_irq_stat(0);
|
||||
|
||||
/* Handle the timer interrupt first */
|
||||
#if 0
|
||||
if (mask & (1 << NILE4_INT_GPT)) {
|
||||
do_IRQ(nile4_to_irq(NILE4_INT_GPT), regs);
|
||||
mask &= ~(1 << NILE4_INT_GPT);
|
||||
}
|
||||
#endif
|
||||
for (nile4_irq = 0; mask; nile4_irq++, mask >>= 1)
|
||||
if (mask & 1) {
|
||||
if (nile4_irq == NILE4_INT_INTE) {
|
||||
int i8259_irq;
|
||||
|
||||
nile4_clear_irq(NILE4_INT_INTE);
|
||||
i8259_irq = nile4_i8259_iack();
|
||||
do_IRQ(i8259_irq, regs);
|
||||
} else
|
||||
do_IRQ(nile4_to_irq(nile4_irq), regs);
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
static void ddb_local1_irqdispatch(void)
|
||||
{
|
||||
printk("ddb_local1_irqdispatch called\n");
|
||||
}
|
||||
|
||||
static void ddb_buserror_irq(void)
|
||||
{
|
||||
printk("ddb_buserror_irq called\n");
|
||||
}
|
||||
|
||||
static void ddb_8254timer_irq(void)
|
||||
{
|
||||
printk("ddb_8254timer_irq called\n");
|
||||
}
|
||||
|
||||
asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
|
||||
{
|
||||
unsigned int pending = read_c0_cause() & read_c0_status();
|
||||
|
||||
if (pending & CAUSEF_IP2)
|
||||
ddb_local0_irqdispatch(regs);
|
||||
else if (pending & CAUSEF_IP3)
|
||||
ddb_local1_irqdispatch();
|
||||
else if (pending & CAUSEF_IP6)
|
||||
ddb_buserror_irq();
|
||||
else if (pending & (CAUSEF_IP4 | CAUSEF_IP5))
|
||||
ddb_8254timer_irq();
|
||||
}
|
||||
|
||||
void __init arch_init_irq(void)
|
||||
{
|
||||
/* setup cascade interrupts */
|
||||
setup_irq(NILE4_IRQ_BASE + NILE4_INT_INTE, &irq_cascade);
|
||||
setup_irq(CPU_IRQ_BASE + CPU_NILE4_CASCADE, &irq_cascade);
|
||||
|
||||
nile4_irq_setup(NILE4_IRQ_BASE);
|
||||
m1543_irq_setup();
|
||||
init_i8259_irqs();
|
||||
|
||||
|
||||
printk("CPU_IRQ_BASE: %d\n",CPU_IRQ_BASE);
|
||||
|
||||
mips_cpu_irq_init(CPU_IRQ_BASE);
|
||||
|
||||
printk("enabling 8259 cascade\n");
|
||||
|
||||
ddb5074_led_hex(0);
|
||||
|
||||
/* Enable the interrupt cascade */
|
||||
nile4_enable_irq(NILE4_IRQ_BASE+IRQ_I8259_CASCADE);
|
||||
}
|
||||
@@ -1,286 +0,0 @@
|
||||
/*
|
||||
* arch/mips/ddb5476/nile4.c --
|
||||
* low-level PIC code for NEC Vrc-5476 (Nile 4)
|
||||
*
|
||||
* Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
|
||||
* Sony Software Development Center Europe (SDCE), Brussels
|
||||
*
|
||||
* Copyright 2001 MontaVista Software Inc.
|
||||
* Author: jsun@mvista.com or jsun@junsun.net
|
||||
*
|
||||
*/
|
||||
#include <linux/config.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/ioport.h>
|
||||
|
||||
#include <asm/addrspace.h>
|
||||
|
||||
#include <asm/ddb5xxx/ddb5xxx.h>
|
||||
|
||||
static int irq_base;
|
||||
|
||||
/*
|
||||
* Interrupt Programming
|
||||
*/
|
||||
void nile4_map_irq(int nile4_irq, int cpu_irq)
|
||||
{
|
||||
u32 offset, t;
|
||||
|
||||
offset = DDB_INTCTRL;
|
||||
if (nile4_irq >= 8) {
|
||||
offset += 4;
|
||||
nile4_irq -= 8;
|
||||
}
|
||||
t = ddb_in32(offset);
|
||||
t &= ~(7 << (nile4_irq * 4));
|
||||
t |= cpu_irq << (nile4_irq * 4);
|
||||
ddb_out32(offset, t);
|
||||
}
|
||||
|
||||
void nile4_map_irq_all(int cpu_irq)
|
||||
{
|
||||
u32 all, t;
|
||||
|
||||
all = cpu_irq;
|
||||
all |= all << 4;
|
||||
all |= all << 8;
|
||||
all |= all << 16;
|
||||
t = ddb_in32(DDB_INTCTRL);
|
||||
t &= 0x88888888;
|
||||
t |= all;
|
||||
ddb_out32(DDB_INTCTRL, t);
|
||||
t = ddb_in32(DDB_INTCTRL + 4);
|
||||
t &= 0x88888888;
|
||||
t |= all;
|
||||
ddb_out32(DDB_INTCTRL + 4, t);
|
||||
}
|
||||
|
||||
void nile4_enable_irq(unsigned int nile4_irq)
|
||||
{
|
||||
u32 offset, t;
|
||||
|
||||
nile4_irq-=irq_base;
|
||||
|
||||
ddb5074_led_hex(8);
|
||||
|
||||
offset = DDB_INTCTRL;
|
||||
if (nile4_irq >= 8) {
|
||||
offset += 4;
|
||||
nile4_irq -= 8;
|
||||
}
|
||||
ddb5074_led_hex(9);
|
||||
t = ddb_in32(offset);
|
||||
ddb5074_led_hex(0xa);
|
||||
t |= 8 << (nile4_irq * 4);
|
||||
ddb_out32(offset, t);
|
||||
ddb5074_led_hex(0xb);
|
||||
}
|
||||
|
||||
void nile4_disable_irq(unsigned int nile4_irq)
|
||||
{
|
||||
u32 offset, t;
|
||||
|
||||
nile4_irq-=irq_base;
|
||||
|
||||
offset = DDB_INTCTRL;
|
||||
if (nile4_irq >= 8) {
|
||||
offset += 4;
|
||||
nile4_irq -= 8;
|
||||
}
|
||||
t = ddb_in32(offset);
|
||||
t &= ~(8 << (nile4_irq * 4));
|
||||
ddb_out32(offset, t);
|
||||
}
|
||||
|
||||
void nile4_disable_irq_all(void)
|
||||
{
|
||||
ddb_out32(DDB_INTCTRL, 0);
|
||||
ddb_out32(DDB_INTCTRL + 4, 0);
|
||||
}
|
||||
|
||||
u16 nile4_get_irq_stat(int cpu_irq)
|
||||
{
|
||||
return ddb_in16(DDB_INTSTAT0 + cpu_irq * 2);
|
||||
}
|
||||
|
||||
void nile4_enable_irq_output(int cpu_irq)
|
||||
{
|
||||
u32 t;
|
||||
|
||||
t = ddb_in32(DDB_INTSTAT1 + 4);
|
||||
t |= 1 << (16 + cpu_irq);
|
||||
ddb_out32(DDB_INTSTAT1, t);
|
||||
}
|
||||
|
||||
void nile4_disable_irq_output(int cpu_irq)
|
||||
{
|
||||
u32 t;
|
||||
|
||||
t = ddb_in32(DDB_INTSTAT1 + 4);
|
||||
t &= ~(1 << (16 + cpu_irq));
|
||||
ddb_out32(DDB_INTSTAT1, t);
|
||||
}
|
||||
|
||||
void nile4_set_pci_irq_polarity(int pci_irq, int high)
|
||||
{
|
||||
u32 t;
|
||||
|
||||
t = ddb_in32(DDB_INTPPES);
|
||||
if (high)
|
||||
t &= ~(1 << (pci_irq * 2));
|
||||
else
|
||||
t |= 1 << (pci_irq * 2);
|
||||
ddb_out32(DDB_INTPPES, t);
|
||||
}
|
||||
|
||||
void nile4_set_pci_irq_level_or_edge(int pci_irq, int level)
|
||||
{
|
||||
u32 t;
|
||||
|
||||
t = ddb_in32(DDB_INTPPES);
|
||||
if (level)
|
||||
t |= 2 << (pci_irq * 2);
|
||||
else
|
||||
t &= ~(2 << (pci_irq * 2));
|
||||
ddb_out32(DDB_INTPPES, t);
|
||||
}
|
||||
|
||||
void nile4_clear_irq(int nile4_irq)
|
||||
{
|
||||
nile4_irq-=irq_base;
|
||||
ddb_out32(DDB_INTCLR, 1 << nile4_irq);
|
||||
}
|
||||
|
||||
void nile4_clear_irq_mask(u32 mask)
|
||||
{
|
||||
ddb_out32(DDB_INTCLR, mask);
|
||||
}
|
||||
|
||||
u8 nile4_i8259_iack(void)
|
||||
{
|
||||
u8 irq;
|
||||
u32 reg;
|
||||
|
||||
/* Set window 0 for interrupt acknowledge */
|
||||
reg = ddb_in32(DDB_PCIINIT0);
|
||||
|
||||
ddb_set_pmr(DDB_PCIINIT0, DDB_PCICMD_IACK, 0, DDB_PCI_ACCESS_32);
|
||||
irq = *(volatile u8 *) KSEG1ADDR(DDB_PCI_IACK_BASE);
|
||||
/* restore window 0 for PCI I/O space */
|
||||
// ddb_set_pmr(DDB_PCIINIT0, DDB_PCICMD_IO, 0, DDB_PCI_ACCESS_32);
|
||||
ddb_out32(DDB_PCIINIT0, reg);
|
||||
|
||||
/* i8269.c set the base vector to be 0x0 */
|
||||
return irq ;
|
||||
}
|
||||
|
||||
static unsigned int nile4_irq_startup(unsigned int irq) {
|
||||
|
||||
nile4_enable_irq(irq);
|
||||
return 0;
|
||||
|
||||
}
|
||||
|
||||
static void nile4_ack_irq(unsigned int irq) {
|
||||
|
||||
ddb5074_led_hex(4);
|
||||
|
||||
nile4_clear_irq(irq);
|
||||
ddb5074_led_hex(2);
|
||||
nile4_disable_irq(irq);
|
||||
|
||||
ddb5074_led_hex(0);
|
||||
}
|
||||
|
||||
static void nile4_irq_end(unsigned int irq) {
|
||||
|
||||
ddb5074_led_hex(3);
|
||||
if(!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
|
||||
ddb5074_led_hex(5);
|
||||
nile4_enable_irq(irq);
|
||||
ddb5074_led_hex(7);
|
||||
}
|
||||
|
||||
ddb5074_led_hex(1);
|
||||
}
|
||||
|
||||
#define nile4_irq_shutdown nile4_disable_irq
|
||||
|
||||
static hw_irq_controller nile4_irq_controller = {
|
||||
.typename = "nile4",
|
||||
.startup = nile4_irq_startup,
|
||||
.shutdown = nile4_irq_shutdown,
|
||||
.enable = nile4_enable_irq,
|
||||
.disable = nile4_disable_irq,
|
||||
.ack = nile4_ack_irq,
|
||||
.end = nile4_irq_end,
|
||||
};
|
||||
|
||||
void nile4_irq_setup(u32 base) {
|
||||
|
||||
int i;
|
||||
|
||||
irq_base=base;
|
||||
|
||||
/* Map all interrupts to CPU int #0 */
|
||||
nile4_map_irq_all(0);
|
||||
|
||||
/* PCI INTA#-E# must be level triggered */
|
||||
nile4_set_pci_irq_level_or_edge(0, 1);
|
||||
nile4_set_pci_irq_level_or_edge(1, 1);
|
||||
nile4_set_pci_irq_level_or_edge(2, 1);
|
||||
nile4_set_pci_irq_level_or_edge(3, 1);
|
||||
nile4_set_pci_irq_level_or_edge(4, 1);
|
||||
|
||||
/* PCI INTA#-D# must be active low, INTE# must be active high */
|
||||
nile4_set_pci_irq_polarity(0, 0);
|
||||
nile4_set_pci_irq_polarity(1, 0);
|
||||
nile4_set_pci_irq_polarity(2, 0);
|
||||
nile4_set_pci_irq_polarity(3, 0);
|
||||
nile4_set_pci_irq_polarity(4, 1);
|
||||
|
||||
|
||||
for (i = 0; i < 16; i++) {
|
||||
nile4_clear_irq(i);
|
||||
nile4_disable_irq(i);
|
||||
}
|
||||
|
||||
/* Enable CPU int #0 */
|
||||
nile4_enable_irq_output(0);
|
||||
|
||||
for (i= base; i< base + NUM_NILE4_INTERRUPTS; i++) {
|
||||
irq_desc[i].status = IRQ_DISABLED;
|
||||
irq_desc[i].action = NULL;
|
||||
irq_desc[i].depth = 1;
|
||||
irq_desc[i].handler = &nile4_irq_controller;
|
||||
}
|
||||
}
|
||||
|
||||
#if defined(CONFIG_RUNTIME_DEBUG)
|
||||
void nile4_dump_irq_status(void)
|
||||
{
|
||||
printk(KERN_DEBUG "
|
||||
CPUSTAT = %p:%p\n", (void *) ddb_in32(DDB_CPUSTAT + 4),
|
||||
(void *) ddb_in32(DDB_CPUSTAT));
|
||||
printk(KERN_DEBUG "
|
||||
INTCTRL = %p:%p\n", (void *) ddb_in32(DDB_INTCTRL + 4),
|
||||
(void *) ddb_in32(DDB_INTCTRL));
|
||||
printk(KERN_DEBUG
|
||||
"INTSTAT0 = %p:%p\n",
|
||||
(void *) ddb_in32(DDB_INTSTAT0 + 4),
|
||||
(void *) ddb_in32(DDB_INTSTAT0));
|
||||
printk(KERN_DEBUG
|
||||
"INTSTAT1 = %p:%p\n",
|
||||
(void *) ddb_in32(DDB_INTSTAT1 + 4),
|
||||
(void *) ddb_in32(DDB_INTSTAT1));
|
||||
printk(KERN_DEBUG
|
||||
"INTCLR = %p:%p\n", (void *) ddb_in32(DDB_INTCLR + 4),
|
||||
(void *) ddb_in32(DDB_INTCLR));
|
||||
printk(KERN_DEBUG
|
||||
"INTPPES = %p:%p\n", (void *) ddb_in32(DDB_INTPPES + 4),
|
||||
(void *) ddb_in32(DDB_INTPPES));
|
||||
}
|
||||
|
||||
#endif
|
||||
@@ -1,234 +0,0 @@
|
||||
/*
|
||||
* arch/mips/ddb5074/setup.c -- NEC DDB Vrc-5074 setup routines
|
||||
*
|
||||
* Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
|
||||
* Sony Software Development Center Europe (SDCE), Brussels
|
||||
*/
|
||||
#include <linux/init.h>
|
||||
#include <linux/kbd_ll.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/kdev_t.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/ide.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/pm.h>
|
||||
|
||||
#include <asm/addrspace.h>
|
||||
#include <asm/bcache.h>
|
||||
#include <asm/irq.h>
|
||||
#include <asm/reboot.h>
|
||||
#include <asm/gdb-stub.h>
|
||||
#include <asm/time.h>
|
||||
#include <asm/nile4.h>
|
||||
#include <asm/ddb5xxx/ddb5074.h>
|
||||
#include <asm/ddb5xxx/ddb5xxx.h>
|
||||
|
||||
static void (*back_to_prom) (void) = (void (*)(void)) 0xbfc00000;
|
||||
|
||||
static void ddb_machine_restart(char *command)
|
||||
{
|
||||
u32 t;
|
||||
|
||||
/* PCI cold reset */
|
||||
t = nile4_in32(NILE4_PCICTRL + 4);
|
||||
t |= 0x40000000;
|
||||
nile4_out32(NILE4_PCICTRL + 4, t);
|
||||
/* CPU cold reset */
|
||||
t = nile4_in32(NILE4_CPUSTAT);
|
||||
t |= 1;
|
||||
nile4_out32(NILE4_CPUSTAT, t);
|
||||
/* Call the PROM */
|
||||
back_to_prom();
|
||||
}
|
||||
|
||||
static void ddb_machine_halt(void)
|
||||
{
|
||||
printk("DDB Vrc-5074 halted.\n");
|
||||
do {
|
||||
} while (1);
|
||||
}
|
||||
|
||||
static void ddb_machine_power_off(void)
|
||||
{
|
||||
printk("DDB Vrc-5074 halted. Please turn off the power.\n");
|
||||
do {
|
||||
} while (1);
|
||||
}
|
||||
|
||||
extern void rtc_ds1386_init(unsigned long base);
|
||||
|
||||
extern void (*board_timer_setup) (struct irqaction * irq);
|
||||
|
||||
static void __init ddb_timer_init(struct irqaction *irq)
|
||||
{
|
||||
/* set the clock to 1 Hz */
|
||||
nile4_out32(NILE4_T2CTRL, 1000000);
|
||||
/* enable the General-Purpose Timer */
|
||||
nile4_out32(NILE4_T2CTRL + 4, 0x00000001);
|
||||
/* reset timer */
|
||||
nile4_out32(NILE4_T2CNTR, 0);
|
||||
/* enable interrupt */
|
||||
setup_irq(nile4_to_irq(NILE4_INT_GPT), irq);
|
||||
nile4_enable_irq(nile4_to_irq(NILE4_INT_GPT));
|
||||
change_c0_status(ST0_IM,
|
||||
IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4);
|
||||
|
||||
}
|
||||
|
||||
static void __init ddb_time_init(void)
|
||||
{
|
||||
/* we have ds1396 RTC chip */
|
||||
rtc_ds1386_init(KSEG1ADDR(DDB_PCI_MEM_BASE));
|
||||
}
|
||||
|
||||
|
||||
|
||||
void __init plat_mem_setup(void)
|
||||
{
|
||||
set_io_port_base(NILE4_PCI_IO_BASE);
|
||||
isa_slot_offset = NILE4_PCI_MEM_BASE;
|
||||
board_timer_setup = ddb_timer_init;
|
||||
board_time_init = ddb_time_init;
|
||||
|
||||
|
||||
_machine_restart = ddb_machine_restart;
|
||||
_machine_halt = ddb_machine_halt;
|
||||
pm_power_off = ddb_machine_power_off;
|
||||
|
||||
ddb_out32(DDB_BAR0, 0);
|
||||
|
||||
ddb_set_pmr(DDB_PCIINIT0, DDB_PCICMD_IO, 0, 0x10);
|
||||
ddb_set_pmr(DDB_PCIINIT1, DDB_PCICMD_MEM, DDB_PCI_MEM_BASE , 0x10);
|
||||
|
||||
/* Reboot on panic */
|
||||
panic_timeout = 180;
|
||||
}
|
||||
|
||||
#define USE_NILE4_SERIAL 0
|
||||
|
||||
#if USE_NILE4_SERIAL
|
||||
#define ns16550_in(reg) nile4_in8((reg)*8)
|
||||
#define ns16550_out(reg, val) nile4_out8((reg)*8, (val))
|
||||
#else
|
||||
#define NS16550_BASE (NILE4_PCI_IO_BASE+0x03f8)
|
||||
static inline u8 ns16550_in(u32 reg)
|
||||
{
|
||||
return *(volatile u8 *) (NS16550_BASE + reg);
|
||||
}
|
||||
|
||||
static inline void ns16550_out(u32 reg, u8 val)
|
||||
{
|
||||
*(volatile u8 *) (NS16550_BASE + reg) = val;
|
||||
}
|
||||
#endif
|
||||
|
||||
#define NS16550_RBR 0
|
||||
#define NS16550_THR 0
|
||||
#define NS16550_DLL 0
|
||||
#define NS16550_IER 1
|
||||
#define NS16550_DLM 1
|
||||
#define NS16550_FCR 2
|
||||
#define NS16550_IIR 2
|
||||
#define NS16550_LCR 3
|
||||
#define NS16550_MCR 4
|
||||
#define NS16550_LSR 5
|
||||
#define NS16550_MSR 6
|
||||
#define NS16550_SCR 7
|
||||
|
||||
#define NS16550_LSR_DR 0x01 /* Data ready */
|
||||
#define NS16550_LSR_OE 0x02 /* Overrun */
|
||||
#define NS16550_LSR_PE 0x04 /* Parity error */
|
||||
#define NS16550_LSR_FE 0x08 /* Framing error */
|
||||
#define NS16550_LSR_BI 0x10 /* Break */
|
||||
#define NS16550_LSR_THRE 0x20 /* Xmit holding register empty */
|
||||
#define NS16550_LSR_TEMT 0x40 /* Xmitter empty */
|
||||
#define NS16550_LSR_ERR 0x80 /* Error */
|
||||
|
||||
|
||||
void _serinit(void)
|
||||
{
|
||||
#if USE_NILE4_SERIAL
|
||||
ns16550_out(NS16550_LCR, 0x80);
|
||||
ns16550_out(NS16550_DLM, 0x00);
|
||||
ns16550_out(NS16550_DLL, 0x36); /* 9600 baud */
|
||||
ns16550_out(NS16550_LCR, 0x00);
|
||||
ns16550_out(NS16550_LCR, 0x03);
|
||||
ns16550_out(NS16550_FCR, 0x47);
|
||||
#else
|
||||
/* done by PMON */
|
||||
#endif
|
||||
}
|
||||
|
||||
void _putc(char c)
|
||||
{
|
||||
while (!(ns16550_in(NS16550_LSR) & NS16550_LSR_THRE));
|
||||
ns16550_out(NS16550_THR, c);
|
||||
if (c == '\n') {
|
||||
while (!(ns16550_in(NS16550_LSR) & NS16550_LSR_THRE));
|
||||
ns16550_out(NS16550_THR, '\r');
|
||||
}
|
||||
}
|
||||
|
||||
void _puts(const char *s)
|
||||
{
|
||||
char c;
|
||||
while ((c = *s++))
|
||||
_putc(c);
|
||||
}
|
||||
|
||||
char _getc(void)
|
||||
{
|
||||
while (!(ns16550_in(NS16550_LSR) & NS16550_LSR_DR));
|
||||
return ns16550_in(NS16550_RBR);
|
||||
}
|
||||
|
||||
int _testc(void)
|
||||
{
|
||||
return (ns16550_in(NS16550_LSR) & NS16550_LSR_DR) != 0;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Hexadecimal 7-segment LED
|
||||
*/
|
||||
void ddb5074_led_hex(int hex)
|
||||
{
|
||||
outb(hex, 0x80);
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* LEDs D2 and D3, connected to the GPIO pins of the PMU in the ALi M1543
|
||||
*/
|
||||
struct pci_dev *pci_pmu = NULL;
|
||||
|
||||
void ddb5074_led_d2(int on)
|
||||
{
|
||||
u8 t;
|
||||
|
||||
if (pci_pmu) {
|
||||
pci_read_config_byte(pci_pmu, 0x7e, &t);
|
||||
if (on)
|
||||
t &= 0x7f;
|
||||
else
|
||||
t |= 0x80;
|
||||
pci_write_config_byte(pci_pmu, 0x7e, t);
|
||||
}
|
||||
}
|
||||
|
||||
void ddb5074_led_d3(int on)
|
||||
{
|
||||
u8 t;
|
||||
|
||||
if (pci_pmu) {
|
||||
pci_read_config_byte(pci_pmu, 0x7e, &t);
|
||||
if (on)
|
||||
t &= 0xbf;
|
||||
else
|
||||
t |= 0x40;
|
||||
pci_write_config_byte(pci_pmu, 0x7e, t);
|
||||
}
|
||||
}
|
||||
Reference in New Issue
Block a user