Merge tag 'mtd/for-4.21' of git://git.infradead.org/linux-mtd
Pull mtd updates from Boris Brezillon:
"SPI NOR Core changes:
- Parse the 4BAIT SFDP section
- Add a bunch of SPI NOR entries to the flash_info table
- Add the concept of SFDP fixups and use it to fix a bug on MX25L25635F
- A bunch of minor cleanups/comestic changes
NAND core changes:
- kernel-doc miscellaneous fixes.
- Third batch of fixes/cleanup to the raw NAND core impacting various
controller drivers (ams-delta, marvell, fsmc, denali, tegra,
vf610):
* Stop to pass mtd_info objects to internal functions
* Reorganize code to avoid forward declarations
* Drop useless test in nand_legacy_set_defaults()
* Move nand_exec_op() to internal.h
* Add nand_[de]select_target() helpers
* Pass the CS line to be selected in struct nand_operation
* Make ->select_chip() optional when ->exec_op() is implemented
* Deprecate the ->select_chip() hook
* Move the ->exec_op() method to nand_controller_ops
* Move ->setup_data_interface() to nand_controller_ops
* Deprecate the dummy_controller field
* Fix JEDEC detection
* Provide a helper for polling GPIO R/B pin
Raw NAND chip drivers changes:
- Macronix:
* Flag 1.8V AC chips with a broken GET_FEATURES(TIMINGS)
Raw NAND controllers drivers changes:
- Ams-delta:
* Fix the error path
* SPDX tag added
* May be compiled with COMPILE_TEST=y
* Conversion to ->exec_op() interface
* Drop .IOADDR_R/W use
* Use GPIO API for data I/O
- Denali:
* Remove denali_reset_banks()
* Remove ->dev_ready() hook
* Include <linux/bits.h> instead of <linux/bitops.h>
* Changes to comply with the above fixes/cleanup done in the core.
- FSMC:
* Add an SPDX tag to replace the license text
* Make conversion from chip to fsmc consistent
* Fix unchecked return value in fsmc_read_page_hwecc
* Changes to comply with the above fixes/cleanup done in the core.
- Marvell:
* Prevent timeouts on a loaded machine (fix)
* Changes to comply with the above fixes/cleanup done in the core.
- OMAP2:
* Pass the parent of pdev to dma_request_chan() (fix)
- R852:
* Use generic DMA API
- sh_flctl:
* Convert to SPDX identifiers
- Sunxi:
* Write pageprog related opcodes to the right register: WCMD_SET (fix)
- Tegra:
* Stop implementing ->select_chip()
- VF610:
* Add an SPDX tag to replace the license text
* Changes to comply with the above fixes/cleanup done in the core.
- Various trivial/spelling/coding style fixes.
SPI-NAND drivers changes:
- Remove the depreacated mt29f_spinand driver from staging.
- Add support for:
* Toshiba TC58CVG2S0H
* GigaDevice GD5FxGQ4xA
* Winbond W25N01GV
JFFS2 changes:
- Fix a lockdep issue
MTD changes:
- Rework the physmap driver to merge gpio-addr-flash and physmap_of
in it
- Add a new compatible for RedBoot partitions
- Make sub-partitions RW if the parent partition was RO because of a
mis-alignment
- Add pinctrl support to the
- Addition of /* fall-through */ comments where appropriate
- Various minor fixes and cleanups
Other changes:
- Update my email address"
* tag 'mtd/for-4.21' of git://git.infradead.org/linux-mtd: (108 commits)
mtd: rawnand: sunxi: Write pageprog related opcodes to WCMD_SET
MAINTAINERS: Update my email address
mtd: rawnand: marvell: prevent timeouts on a loaded machine
mtd: rawnand: omap2: Pass the parent of pdev to dma_request_chan()
mtd: rawnand: Fix JEDEC detection
mtd: spi-nor: Add support for is25lp016d
mtd: spi-nor: parse SFDP 4-byte Address Instruction Table
mtd: spi-nor: Add 4B_OPCODES flag to is25lp256
mtd: spi-nor: Add an SPDX tag to spi-nor.{c,h}
mtd: spi-nor: Make the enable argument passed to set_byte() a bool
mtd: spi-nor: Stop passing flash_info around
mtd: spi-nor: Avoid forward declaration of internal functions
mtd: spi-nor: Drop inline on all internal helpers
mtd: spi-nor: Add a post BFPT fixup for MX25L25635E
mtd: spi-nor: Add a post BFPT parsing fixup hook
mtd: spi-nor: Add the SNOR_F_4B_OPCODES flag
mtd: spi-nor: cast to u64 to avoid uint overflows
mtd: spi-nor: Add support for IS25LP032/064
mtd: spi-nor: add entry for mt35xu512aba flash
mtd: spi-nor: add macros related to MICRON flash
...
This commit is contained in:
Linus Torvalds
@@ -377,6 +377,7 @@ struct cfi_fixup {
|
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#define CFI_MFR_SHARP 0x00B0
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#define CFI_MFR_SST 0x00BF
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#define CFI_MFR_ST 0x0020 /* STMicroelectronics */
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#define CFI_MFR_MICRON 0x002C /* Micron */
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#define CFI_MFR_TOSHIBA 0x0098
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#define CFI_MFR_WINBOND 0x00DA
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@@ -207,6 +207,7 @@ struct mtd_debug_info {
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struct mtd_info {
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u_char type;
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uint32_t flags;
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uint32_t orig_flags; /* Flags as before running mtd checks */
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uint64_t size; // Total size of the MTD
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/* "Major" erase size for the device. Naïve users may take this
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@@ -386,7 +387,7 @@ static inline struct device_node *mtd_get_of_node(struct mtd_info *mtd)
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return dev_of_node(&mtd->dev);
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}
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static inline int mtd_oobavail(struct mtd_info *mtd, struct mtd_oob_ops *ops)
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static inline u32 mtd_oobavail(struct mtd_info *mtd, struct mtd_oob_ops *ops)
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{
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return ops->mode == MTD_OPS_AUTO_OOB ? mtd->oobavail : mtd->oobsize;
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}
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@@ -203,9 +203,12 @@ enum nand_ecc_algo {
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*/
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#define NAND_IS_BOOT_MEDIUM 0x00400000
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/* Options set by nand scan */
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/* Nand scan has allocated controller struct */
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#define NAND_CONTROLLER_ALLOC 0x80000000
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/*
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* Do not try to tweak the timings at runtime. This is needed when the
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* controller initializes the timings on itself or when it relies on
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* configuration done by the bootloader.
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*/
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#define NAND_KEEP_TIMINGS 0x00800000
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/* Cell info constants */
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#define NAND_CI_CHIPNR_MSK 0x03
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@@ -244,49 +247,6 @@ struct nand_id {
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int len;
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};
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/**
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* struct nand_controller_ops - Controller operations
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*
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* @attach_chip: this method is called after the NAND detection phase after
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* flash ID and MTD fields such as erase size, page size and OOB
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* size have been set up. ECC requirements are available if
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* provided by the NAND chip or device tree. Typically used to
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* choose the appropriate ECC configuration and allocate
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* associated resources.
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* This hook is optional.
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* @detach_chip: free all resources allocated/claimed in
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* nand_controller_ops->attach_chip().
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* This hook is optional.
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*/
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struct nand_controller_ops {
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int (*attach_chip)(struct nand_chip *chip);
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void (*detach_chip)(struct nand_chip *chip);
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};
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/**
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* struct nand_controller - Structure used to describe a NAND controller
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*
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* @lock: protection lock
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* @active: the mtd device which holds the controller currently
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* @wq: wait queue to sleep on if a NAND operation is in
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* progress used instead of the per chip wait queue
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* when a hw controller is available.
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* @ops: NAND controller operations.
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*/
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struct nand_controller {
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spinlock_t lock;
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struct nand_chip *active;
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wait_queue_head_t wq;
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const struct nand_controller_ops *ops;
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};
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static inline void nand_controller_init(struct nand_controller *nfc)
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{
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nfc->active = NULL;
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spin_lock_init(&nfc->lock);
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init_waitqueue_head(&nfc->wq);
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}
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/**
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* struct nand_ecc_step_info - ECC step information of ECC engine
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* @stepsize: data bytes per ECC step
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@@ -879,18 +839,21 @@ struct nand_op_parser {
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/**
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* struct nand_operation - NAND operation descriptor
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* @cs: the CS line to select for this NAND operation
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* @instrs: array of instructions to execute
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* @ninstrs: length of the @instrs array
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*
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* The actual operation structure that will be passed to chip->exec_op().
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*/
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struct nand_operation {
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unsigned int cs;
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const struct nand_op_instr *instrs;
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unsigned int ninstrs;
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};
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#define NAND_OPERATION(_instrs) \
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#define NAND_OPERATION(_cs, _instrs) \
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{ \
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.cs = _cs, \
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.instrs = _instrs, \
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.ninstrs = ARRAY_SIZE(_instrs), \
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}
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@@ -898,11 +861,68 @@ struct nand_operation {
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int nand_op_parser_exec_op(struct nand_chip *chip,
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const struct nand_op_parser *parser,
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const struct nand_operation *op, bool check_only);
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/**
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* struct nand_controller_ops - Controller operations
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*
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* @attach_chip: this method is called after the NAND detection phase after
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* flash ID and MTD fields such as erase size, page size and OOB
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* size have been set up. ECC requirements are available if
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* provided by the NAND chip or device tree. Typically used to
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* choose the appropriate ECC configuration and allocate
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* associated resources.
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* This hook is optional.
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* @detach_chip: free all resources allocated/claimed in
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* nand_controller_ops->attach_chip().
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* This hook is optional.
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* @exec_op: controller specific method to execute NAND operations.
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* This method replaces chip->legacy.cmdfunc(),
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* chip->legacy.{read,write}_{buf,byte,word}(),
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* chip->legacy.dev_ready() and chip->legacy.waifunc().
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* @setup_data_interface: setup the data interface and timing. If
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* chipnr is set to %NAND_DATA_IFACE_CHECK_ONLY this
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* means the configuration should not be applied but
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* only checked.
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* This hook is optional.
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*/
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struct nand_controller_ops {
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int (*attach_chip)(struct nand_chip *chip);
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void (*detach_chip)(struct nand_chip *chip);
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int (*exec_op)(struct nand_chip *chip,
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const struct nand_operation *op,
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bool check_only);
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int (*setup_data_interface)(struct nand_chip *chip, int chipnr,
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const struct nand_data_interface *conf);
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};
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/**
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* struct nand_controller - Structure used to describe a NAND controller
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*
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* @lock: protection lock
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* @active: the mtd device which holds the controller currently
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* @wq: wait queue to sleep on if a NAND operation is in
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* progress used instead of the per chip wait queue
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* when a hw controller is available.
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* @ops: NAND controller operations.
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*/
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struct nand_controller {
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spinlock_t lock;
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struct nand_chip *active;
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wait_queue_head_t wq;
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const struct nand_controller_ops *ops;
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};
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static inline void nand_controller_init(struct nand_controller *nfc)
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{
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nfc->active = NULL;
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spin_lock_init(&nfc->lock);
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init_waitqueue_head(&nfc->wq);
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}
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/**
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* struct nand_legacy - NAND chip legacy fields/hooks
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* @IO_ADDR_R: address to read the 8 I/O lines of the flash device
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* @IO_ADDR_W: address to write the 8 I/O lines of the flash device
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* @select_chip: select/deselect a specific target/die
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* @read_byte: read one byte from the chip
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* @write_byte: write a single byte to the chip on the low 8 I/O lines
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* @write_buf: write data from the buffer to the chip
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@@ -921,6 +941,8 @@ int nand_op_parser_exec_op(struct nand_chip *chip,
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* @get_features: get the NAND chip features
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* @chip_delay: chip dependent delay for transferring data from array to read
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* regs (tR).
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* @dummy_controller: dummy controller implementation for drivers that can
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* only control a single chip
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*
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* If you look at this structure you're already wrong. These fields/hooks are
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* all deprecated.
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@@ -928,6 +950,7 @@ int nand_op_parser_exec_op(struct nand_chip *chip,
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struct nand_legacy {
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void __iomem *IO_ADDR_R;
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void __iomem *IO_ADDR_W;
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void (*select_chip)(struct nand_chip *chip, int cs);
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u8 (*read_byte)(struct nand_chip *chip);
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void (*write_byte)(struct nand_chip *chip, u8 byte);
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void (*write_buf)(struct nand_chip *chip, const u8 *buf, int len);
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@@ -945,6 +968,7 @@ struct nand_legacy {
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int (*get_features)(struct nand_chip *chip, int feature_addr,
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u8 *subfeature_para);
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int chip_delay;
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struct nand_controller dummy_controller;
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};
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/**
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@@ -955,17 +979,10 @@ struct nand_legacy {
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* you're modifying an existing driver that is using those
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* fields/hooks, you should consider reworking the driver
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* avoid using them.
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* @select_chip: [REPLACEABLE] select chip nr
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* @exec_op: controller specific method to execute NAND operations.
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* This method replaces ->cmdfunc(),
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* ->legacy.{read,write}_{buf,byte,word}(),
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* ->legacy.dev_ready() and ->waifunc().
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* @setup_read_retry: [FLASHSPECIFIC] flash (vendor) specific function for
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* setting the read-retry mode. Mostly needed for MLC NAND.
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* @ecc: [BOARDSPECIFIC] ECC control structure
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* @buf_align: minimum buffer alignment required by a platform
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* @dummy_controller: dummy controller implementation for drivers that can
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* only control a single chip
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* @state: [INTERN] the current state of the NAND device
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* @oob_poi: "poison value buffer," used for laying out OOB data
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* before writing
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@@ -1012,11 +1029,11 @@ struct nand_legacy {
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* this nand device will encounter their life times.
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* @blocks_per_die: [INTERN] The number of PEBs in a die
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* @data_interface: [INTERN] NAND interface timing information
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* @cur_cs: currently selected target. -1 means no target selected,
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* otherwise we should always have cur_cs >= 0 &&
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* cur_cs < numchips. NAND Controller drivers should not
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* modify this value, but they're allowed to read it.
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* @read_retries: [INTERN] the number of read retry modes supported
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* @setup_data_interface: [OPTIONAL] setup the data interface and timing. If
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* chipnr is set to %NAND_DATA_IFACE_CHECK_ONLY this
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* means the configuration should not be applied but
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* only checked.
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* @bbt: [INTERN] bad block table pointer
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* @bbt_td: [REPLACEABLE] bad block table descriptor for flash
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* lookup.
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@@ -1037,13 +1054,7 @@ struct nand_chip {
|
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struct nand_legacy legacy;
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void (*select_chip)(struct nand_chip *chip, int cs);
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int (*exec_op)(struct nand_chip *chip,
|
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const struct nand_operation *op,
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bool check_only);
|
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int (*setup_read_retry)(struct nand_chip *chip, int retry_mode);
|
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int (*setup_data_interface)(struct nand_chip *chip, int chipnr,
|
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const struct nand_data_interface *conf);
|
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|
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unsigned int options;
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unsigned int bbt_options;
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@@ -1073,6 +1084,8 @@ struct nand_chip {
|
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struct nand_data_interface data_interface;
|
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int cur_cs;
|
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int read_retries;
|
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|
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flstate_t state;
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@@ -1082,7 +1095,6 @@ struct nand_chip {
|
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struct nand_ecc_ctrl ecc;
|
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unsigned long buf_align;
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struct nand_controller dummy_controller;
|
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uint8_t *bbt;
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struct nand_bbt_descr *bbt_td;
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@@ -1098,15 +1110,6 @@ struct nand_chip {
|
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} manufacturer;
|
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};
|
||||
|
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static inline int nand_exec_op(struct nand_chip *chip,
|
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const struct nand_operation *op)
|
||||
{
|
||||
if (!chip->exec_op)
|
||||
return -ENOTSUPP;
|
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|
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return chip->exec_op(chip, op, false);
|
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}
|
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|
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extern const struct mtd_ooblayout_ops nand_ooblayout_sp_ops;
|
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extern const struct mtd_ooblayout_ops nand_ooblayout_lp_ops;
|
||||
|
||||
@@ -1345,5 +1348,12 @@ void nand_release(struct nand_chip *chip);
|
||||
* instruction and have no physical pin to check it.
|
||||
*/
|
||||
int nand_soft_waitrdy(struct nand_chip *chip, unsigned long timeout_ms);
|
||||
struct gpio_desc;
|
||||
int nand_gpio_waitrdy(struct nand_chip *chip, struct gpio_desc *gpiod,
|
||||
unsigned long timeout_ms);
|
||||
|
||||
/* Select/deselect a NAND target. */
|
||||
void nand_select_target(struct nand_chip *chip, unsigned int cs);
|
||||
void nand_deselect_target(struct nand_chip *chip);
|
||||
|
||||
#endif /* __LINUX_MTD_RAWNAND_H */
|
||||
|
||||
@@ -1,20 +1,8 @@
|
||||
/*
|
||||
/* SPDX-License-Identifier: GPL-2.0
|
||||
*
|
||||
* SuperH FLCTL nand controller
|
||||
*
|
||||
* Copyright © 2008 Renesas Solutions Corp.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#ifndef __SH_FLCTL_H__
|
||||
|
||||
@@ -1,10 +1,6 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2014 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef __LINUX_MTD_SPI_NOR_H
|
||||
@@ -23,7 +19,8 @@
|
||||
#define SNOR_MFR_ATMEL CFI_MFR_ATMEL
|
||||
#define SNOR_MFR_GIGADEVICE 0xc8
|
||||
#define SNOR_MFR_INTEL CFI_MFR_INTEL
|
||||
#define SNOR_MFR_MICRON CFI_MFR_ST /* ST Micro <--> Micron */
|
||||
#define SNOR_MFR_ST CFI_MFR_ST /* ST Micro */
|
||||
#define SNOR_MFR_MICRON CFI_MFR_MICRON /* Micron */
|
||||
#define SNOR_MFR_MACRONIX CFI_MFR_MACRONIX
|
||||
#define SNOR_MFR_SPANSION CFI_MFR_AMD
|
||||
#define SNOR_MFR_SST CFI_MFR_SST
|
||||
@@ -236,6 +233,8 @@ enum spi_nor_option_flags {
|
||||
SNOR_F_READY_XSR_RDY = BIT(4),
|
||||
SNOR_F_USE_CLSR = BIT(5),
|
||||
SNOR_F_BROKEN_RESET = BIT(6),
|
||||
SNOR_F_4B_OPCODES = BIT(7),
|
||||
SNOR_F_HAS_4BAIT = BIT(8),
|
||||
};
|
||||
|
||||
/**
|
||||
|
||||
@@ -194,8 +194,10 @@ struct spinand_manufacturer {
|
||||
};
|
||||
|
||||
/* SPI NAND manufacturers */
|
||||
extern const struct spinand_manufacturer gigadevice_spinand_manufacturer;
|
||||
extern const struct spinand_manufacturer macronix_spinand_manufacturer;
|
||||
extern const struct spinand_manufacturer micron_spinand_manufacturer;
|
||||
extern const struct spinand_manufacturer toshiba_spinand_manufacturer;
|
||||
extern const struct spinand_manufacturer winbond_spinand_manufacturer;
|
||||
|
||||
/**
|
||||
|
||||
Reference in New Issue
Block a user