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Merge tag 'clk-for-linus-4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

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Pull clock framework updates from Michael Turquette:
 "The changes to the common clock framework for 4.0 are mostly new clock
  drivers and updates to existing ones for feature enhancements and bug
  fixes.

  There is more churn than usual in the framework core due to the change
  to introduce per-user unique struct clk pointers in 4.0.  This caused
  several regressions to surface, some of which were sent as fixes to
  4.0.  New generic clock drivers were added for GPIO- and PWM-based
  clock controllers.

  Additionally the common clk-divider code recieved several fixes to the
  way it rounds rates"

* tag 'clk-for-linus-4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (91 commits)
  clk: check ->determine/round_rate() return value in clk_calc_new_rates
  clk: at91: usb: propagate rate modification to the parent clk
  clk: samsung: exynos4: Disable ARMCLK down feature on Exynos4210 SoC
  clk: don't use __initconst for non-const arrays
  clk: at91: change to using endian agnositc IO
  clk: clk-gpio-gate: Fix active low
  clk: Add PWM clock driver
  clk: Add clock driver for mb86s7x
  clk: pxa: pxa3xx: add missing os timer clock
  clk: tegra: Use the proper parent for plld_dsi
  clk: tegra: Use generic tegra_osc_clk_init() on Tegra114
  clk: tegra: Model oscillator as clock
  clk: tegra: Add peripheral registers for bank Y
  clk: tegra: Register the proper number of resets
  clk: tegra: Remove needless initializations
  clk: tegra: Use consistent indentation
  clk: tegra: Various whitespace cleanups
  clk: tegra: Enable HDA to HDMI clocks on Tegra124
  clk: tegra: Fix a bunch of sparse warnings
  clk: tegra: Fix typo tabel -> table
  ...
This commit is contained in:
Linus Torvalds
2015-04-21 09:24:09 -07:00
parent 8f443e2372 03bc10ab5b
commit e98bf5cedf
107 changed files with 13215 additions and 837 deletions
Download Patch File Download Diff File Expand all files Collapse all files

61
include/dt-bindings/clock/exynos3250.h
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@@ -282,4 +282,65 @@
*/
#define NR_CLKS_DMC 21
/*
* CMU ISP
*/
/* Dividers */
#define CLK_DIV_ISP1 1
#define CLK_DIV_ISP0 2
#define CLK_DIV_MCUISP1 3
#define CLK_DIV_MCUISP0 4
#define CLK_DIV_MPWM 5
/* Gates */
#define CLK_UART_ISP 8
#define CLK_WDT_ISP 9
#define CLK_PWM_ISP 10
#define CLK_I2C1_ISP 11
#define CLK_I2C0_ISP 12
#define CLK_MPWM_ISP 13
#define CLK_MCUCTL_ISP 14
#define CLK_PPMUISPX 15
#define CLK_PPMUISPMX 16
#define CLK_QE_LITE1 17
#define CLK_QE_LITE0 18
#define CLK_QE_FD 19
#define CLK_QE_DRC 20
#define CLK_QE_ISP 21
#define CLK_CSIS1 22
#define CLK_SMMU_LITE1 23
#define CLK_SMMU_LITE0 24
#define CLK_SMMU_FD 25
#define CLK_SMMU_DRC 26
#define CLK_SMMU_ISP 27
#define CLK_GICISP 28
#define CLK_CSIS0 29
#define CLK_MCUISP 30
#define CLK_LITE1 31
#define CLK_LITE0 32
#define CLK_FD 33
#define CLK_DRC 34
#define CLK_ISP 35
#define CLK_QE_ISPCX 36
#define CLK_QE_SCALERP 37
#define CLK_QE_SCALERC 38
#define CLK_SMMU_SCALERP 39
#define CLK_SMMU_SCALERC 40
#define CLK_SCALERP 41
#define CLK_SCALERC 42
#define CLK_SPI1_ISP 43
#define CLK_SPI0_ISP 44
#define CLK_SMMU_ISPCX 45
#define CLK_ASYNCAXIM 46
#define CLK_SCLK_MPWM_ISP 47
/*
* Total number of clocks of CMU_ISP.
* NOTE: Must be equal to last clock ID increased by one.
*/
#define NR_CLKS_ISP 48
#endif /* _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H */

1403
include/dt-bindings/clock/exynos5433.h Normal file
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File diff suppressed because it is too large Load Diff

1
include/dt-bindings/clock/qcom,gcc-ipq806x.h
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@@ -288,5 +288,6 @@
#define UBI32_CORE2_CLK_SRC 278
#define UBI32_CORE1_CLK 279
#define UBI32_CORE2_CLK 280
#define EBI2_AON_CLK 281
#endif

156
include/dt-bindings/clock/qcom,gcc-msm8916.h Normal file
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@@ -0,0 +1,156 @@
/*
* Copyright 2015 Linaro Limited
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _DT_BINDINGS_CLK_MSM_GCC_8916_H
#define _DT_BINDINGS_CLK_MSM_GCC_8916_H
#define GPLL0 0
#define GPLL0_VOTE 1
#define BIMC_PLL 2
#define BIMC_PLL_VOTE 3
#define GPLL1 4
#define GPLL1_VOTE 5
#define GPLL2 6
#define GPLL2_VOTE 7
#define PCNOC_BFDCD_CLK_SRC 8
#define SYSTEM_NOC_BFDCD_CLK_SRC 9
#define CAMSS_AHB_CLK_SRC 10
#define APSS_AHB_CLK_SRC 11
#define CSI0_CLK_SRC 12
#define CSI1_CLK_SRC 13
#define GFX3D_CLK_SRC 14
#define VFE0_CLK_SRC 15
#define BLSP1_QUP1_I2C_APPS_CLK_SRC 16
#define BLSP1_QUP1_SPI_APPS_CLK_SRC 17
#define BLSP1_QUP2_I2C_APPS_CLK_SRC 18
#define BLSP1_QUP2_SPI_APPS_CLK_SRC 19
#define BLSP1_QUP3_I2C_APPS_CLK_SRC 20
#define BLSP1_QUP3_SPI_APPS_CLK_SRC 21
#define BLSP1_QUP4_I2C_APPS_CLK_SRC 22
#define BLSP1_QUP4_SPI_APPS_CLK_SRC 23
#define BLSP1_QUP5_I2C_APPS_CLK_SRC 24
#define BLSP1_QUP5_SPI_APPS_CLK_SRC 25
#define BLSP1_QUP6_I2C_APPS_CLK_SRC 26
#define BLSP1_QUP6_SPI_APPS_CLK_SRC 27
#define BLSP1_UART1_APPS_CLK_SRC 28
#define BLSP1_UART2_APPS_CLK_SRC 29
#define CCI_CLK_SRC 30
#define CAMSS_GP0_CLK_SRC 31
#define CAMSS_GP1_CLK_SRC 32
#define JPEG0_CLK_SRC 33
#define MCLK0_CLK_SRC 34
#define MCLK1_CLK_SRC 35
#define CSI0PHYTIMER_CLK_SRC 36
#define CSI1PHYTIMER_CLK_SRC 37
#define CPP_CLK_SRC 38
#define CRYPTO_CLK_SRC 39
#define GP1_CLK_SRC 40
#define GP2_CLK_SRC 41
#define GP3_CLK_SRC 42
#define BYTE0_CLK_SRC 43
#define ESC0_CLK_SRC 44
#define MDP_CLK_SRC 45
#define PCLK0_CLK_SRC 46
#define VSYNC_CLK_SRC 47
#define PDM2_CLK_SRC 48
#define SDCC1_APPS_CLK_SRC 49
#define SDCC2_APPS_CLK_SRC 50
#define APSS_TCU_CLK_SRC 51
#define USB_HS_SYSTEM_CLK_SRC 52
#define VCODEC0_CLK_SRC 53
#define GCC_BLSP1_AHB_CLK 54
#define GCC_BLSP1_SLEEP_CLK 55
#define GCC_BLSP1_QUP1_I2C_APPS_CLK 56
#define GCC_BLSP1_QUP1_SPI_APPS_CLK 57
#define GCC_BLSP1_QUP2_I2C_APPS_CLK 58
#define GCC_BLSP1_QUP2_SPI_APPS_CLK 59
#define GCC_BLSP1_QUP3_I2C_APPS_CLK 60
#define GCC_BLSP1_QUP3_SPI_APPS_CLK 61
#define GCC_BLSP1_QUP4_I2C_APPS_CLK 62
#define GCC_BLSP1_QUP4_SPI_APPS_CLK 63
#define GCC_BLSP1_QUP5_I2C_APPS_CLK 64
#define GCC_BLSP1_QUP5_SPI_APPS_CLK 65
#define GCC_BLSP1_QUP6_I2C_APPS_CLK 66
#define GCC_BLSP1_QUP6_SPI_APPS_CLK 67
#define GCC_BLSP1_UART1_APPS_CLK 68
#define GCC_BLSP1_UART2_APPS_CLK 69
#define GCC_BOOT_ROM_AHB_CLK 70
#define GCC_CAMSS_CCI_AHB_CLK 71
#define GCC_CAMSS_CCI_CLK 72
#define GCC_CAMSS_CSI0_AHB_CLK 73
#define GCC_CAMSS_CSI0_CLK 74
#define GCC_CAMSS_CSI0PHY_CLK 75
#define GCC_CAMSS_CSI0PIX_CLK 76
#define GCC_CAMSS_CSI0RDI_CLK 77
#define GCC_CAMSS_CSI1_AHB_CLK 78
#define GCC_CAMSS_CSI1_CLK 79
#define GCC_CAMSS_CSI1PHY_CLK 80
#define GCC_CAMSS_CSI1PIX_CLK 81
#define GCC_CAMSS_CSI1RDI_CLK 82
#define GCC_CAMSS_CSI_VFE0_CLK 83
#define GCC_CAMSS_GP0_CLK 84
#define GCC_CAMSS_GP1_CLK 85
#define GCC_CAMSS_ISPIF_AHB_CLK 86
#define GCC_CAMSS_JPEG0_CLK 87
#define GCC_CAMSS_JPEG_AHB_CLK 88
#define GCC_CAMSS_JPEG_AXI_CLK 89
#define GCC_CAMSS_MCLK0_CLK 90
#define GCC_CAMSS_MCLK1_CLK 91
#define GCC_CAMSS_MICRO_AHB_CLK 92
#define GCC_CAMSS_CSI0PHYTIMER_CLK 93
#define GCC_CAMSS_CSI1PHYTIMER_CLK 94
#define GCC_CAMSS_AHB_CLK 95
#define GCC_CAMSS_TOP_AHB_CLK 96
#define GCC_CAMSS_CPP_AHB_CLK 97
#define GCC_CAMSS_CPP_CLK 98
#define GCC_CAMSS_VFE0_CLK 99
#define GCC_CAMSS_VFE_AHB_CLK 100
#define GCC_CAMSS_VFE_AXI_CLK 101
#define GCC_CRYPTO_AHB_CLK 102
#define GCC_CRYPTO_AXI_CLK 103
#define GCC_CRYPTO_CLK 104
#define GCC_OXILI_GMEM_CLK 105
#define GCC_GP1_CLK 106
#define GCC_GP2_CLK 107
#define GCC_GP3_CLK 108
#define GCC_MDSS_AHB_CLK 109
#define GCC_MDSS_AXI_CLK 110
#define GCC_MDSS_BYTE0_CLK 111
#define GCC_MDSS_ESC0_CLK 112
#define GCC_MDSS_MDP_CLK 113
#define GCC_MDSS_PCLK0_CLK 114
#define GCC_MDSS_VSYNC_CLK 115
#define GCC_MSS_CFG_AHB_CLK 116
#define GCC_OXILI_AHB_CLK 117
#define GCC_OXILI_GFX3D_CLK 118
#define GCC_PDM2_CLK 119
#define GCC_PDM_AHB_CLK 120
#define GCC_PRNG_AHB_CLK 121
#define GCC_SDCC1_AHB_CLK 122
#define GCC_SDCC1_APPS_CLK 123
#define GCC_SDCC2_AHB_CLK 124
#define GCC_SDCC2_APPS_CLK 125
#define GCC_GTCU_AHB_CLK 126
#define GCC_JPEG_TBU_CLK 127
#define GCC_MDP_TBU_CLK 128
#define GCC_SMMU_CFG_CLK 129
#define GCC_VENUS_TBU_CLK 130
#define GCC_VFE_TBU_CLK 131
#define GCC_USB2A_PHY_SLEEP_CLK 132
#define GCC_USB_HS_AHB_CLK 133
#define GCC_USB_HS_SYSTEM_CLK 134
#define GCC_VENUS0_AHB_CLK 135
#define GCC_VENUS0_AXI_CLK 136
#define GCC_VENUS0_VCODEC0_CLK 137
#endif

2
include/dt-bindings/clock/tegra124-car-common.h
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@@ -297,7 +297,7 @@
#define TEGRA124_CLK_PLL_C4 270
#define TEGRA124_CLK_PLL_DP 271
#define TEGRA124_CLK_PLL_E_MUX 272
#define TEGRA124_CLK_PLLD_DSI 273
#define TEGRA124_CLK_PLL_D_DSI_OUT 273
/* 274 */
/* 275 */
/* 276 */