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clk: tegra: dfll: Make code more comprehensible

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Rename some variables and structure fields to make the code more
comprehensible. Also change the prototype of internal functions to be
more in line with the OPP core functions.

Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Thierry Reding
2016-04-08 15:09:56 +02:00
parent 27ed2f7e7c
commit e8f6a68c50
3 changed files with 38 additions and 42 deletions
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12
drivers/clk/tegra/cvb.h
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@@ -53,15 +53,13 @@ struct cvb_table {
int speedo_scale;
int voltage_scale;
struct cvb_table_freq_entry cvb_table[MAX_DVFS_FREQS];
struct cvb_table_freq_entry entries[MAX_DVFS_FREQS];
struct cvb_cpu_dfll_data cpu_dfll_data;
};
const struct cvb_table *tegra_cvb_build_opp_table(
const struct cvb_table *cvb_tables,
size_t sz, int process_id,
int speedo_id, int speedo_value,
unsigned long max_rate,
struct device *opp_dev);
const struct cvb_table *
tegra_cvb_add_opp_table(struct device *dev, const struct cvb_table *cvb_tables,
size_t count, int process_id, int speedo_id,
int speedo_value, unsigned long max_freq);
#endif