ath5k: Update reset code
* Update reset and sync with HALs * Clean up eeprom settings and tweaking of initvals and put them on separate functions * Set/Restore 32KHz ref clk operation * Add some more documentation TODO: Spur mitigation, tpc, half/quarter rate, compression etc v2: Address comments from Bob and Felix and fix RSSI threshold bug introduced on the first version of the patch Signed-off-by: Nick Kossifidis <mickflemm@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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John W. Linville

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e8f055f0c3
@@ -25,6 +25,7 @@
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#define AR5K_EEPROM_MAGIC_5211 0x0000145b /* 5211 */
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#define AR5K_EEPROM_MAGIC_5210 0x0000145a /* 5210 */
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#define AR5K_EEPROM_IS_HB63 0x000b /* Talon detect */
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#define AR5K_EEPROM_REG_DOMAIN 0x00bf /* EEPROM regdom */
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#define AR5K_EEPROM_CHECKSUM 0x00c0 /* EEPROM checksum */
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#define AR5K_EEPROM_INFO_BASE 0x00c0 /* EEPROM header */
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