Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM Device-tree updates from Olof Johansson:
"Besides new bindings and additional descriptions of hardware blocks
for various SoCs and boards, the main new contents here is:
SoCs:
- Intel Agilex (SoCFPGA)
- NXP i.MX8MM (Quad Cortex-A53 with media/graphics focus)
New boards:
- Allwinner:
+ RerVision H3-DVK (H3)
+ Oceanic 5205 5inMFD (H6)
+ Beelink GS2 (H6)
+ Orange Pi 3 (H6)
- Rockchip:
+ Orange Pi RK3399
+ Nanopi NEO4
+ Veyron-Mighty Chromebook variant
- Amlogic:
+ SEI Robotics SEI510
- ST Micro:
+ stm32mp157a discovery1
+ stm32mp157c discovery2
- NXP:
+ Eckelmann ci4x10 (i.MX6DL)
+ i.MX8MM EVK (i.MX8MM)
+ ZII i.MX7 RPU2 (i.MX7)
+ ZII SPB4 (VF610)
+ Zii Ultra (i.MX8M)
+ TQ TQMa7S (i.MX7Solo)
+ TQ TQMa7D (i.MX7Dual)
+ Kobo Aura (i.MX50)
+ Menlosystems M53 (i.MX53)j
- Nvidia:
+ Jetson Nano (Tegra T210)"
* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (593 commits)
arm64: dts: bitmain: Add UART pinctrl support for Sophon Edge
arm64: dts: bitmain: Add pinctrl support for BM1880 SoC
arm64: dts: bitmain: Add GPIO Line names for Sophon Edge board
arm64: dts: bitmain: Add GPIO support for BM1880 SoC
ARM: dts: gemini: Indent DIR-685 partition table
dt-bindings: hwmon (pwm-fan) Remove dead "cooling-*-state" properties
ARM: dts: qcom-apq8064: Set 'cxo_board' as ref clock of the DSI PHY
arm64: dts: msm8998: thermal: Restrict thermal zone name length to under 20
arm64: dts: msm8998: thermal: Fix number of supported sensors
arm64: dts: msm8998-mtp: thermal: Remove skin and battery thermal zones
arm64: dts: exynos: Move fixed-clocks out of soc
arm64: dts: exynos: Move pmu and timer nodes out of soc
ARM: dts: s5pv210: Fix camera clock provider on Goni board
ARM: dts: exynos: Properly override node to use MDMA0 on Universal C210
ARM: dts: exynos: Move fixed-clocks out of soc on Exynos3250
ARM: dts: exynos: Remove unneeded address/size cells from fixed-clock on Exynos3250
ARM: dts: exynos: Move pmu and timer nodes out of soc
arm64: dts: rockchip: fix IO domain voltage setting of APIO5 on rockpro64
arm64: dts: db820c: Add sound card support
arm64: dts: apq8096-db820c: Add HDMI display support
...
This commit is contained in:
Linus Torvalds
@@ -54,14 +54,14 @@
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#define IOU_SWITCH 42
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#define GEM_TSU_REF 43
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#define GEM_TSU 44
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#define GEM0_REF 45
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#define GEM1_REF 46
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#define GEM2_REF 47
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#define GEM3_REF 48
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#define GEM0_TX 49
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#define GEM1_TX 50
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#define GEM2_TX 51
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#define GEM3_TX 52
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#define GEM0_TX 45
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#define GEM1_TX 46
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#define GEM2_TX 47
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#define GEM3_TX 48
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#define GEM0_RX 49
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#define GEM1_RX 50
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#define GEM2_RX 51
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#define GEM3_RX 52
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#define QSPI_REF 53
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#define SDIO0_REF 54
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#define SDIO1_REF 55
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@@ -112,5 +112,15 @@
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#define VPLL_POST_SRC 100
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#define CAN0_MIO 101
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#define CAN1_MIO 102
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#define ACPU_FULL 103
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#define GEM0_REF 104
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#define GEM1_REF 105
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#define GEM2_REF 106
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#define GEM3_REF 107
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#define GEM0_REF_UNG 108
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#define GEM1_REF_UNG 109
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#define GEM2_REF_UNG 110
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#define GEM3_REF_UNG 111
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#define LPD_WDT 112
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#endif
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@@ -36,15 +36,11 @@
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#define IMX_SC_R_DC_0_BLIT1 20
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#define IMX_SC_R_DC_0_BLIT2 21
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#define IMX_SC_R_DC_0_BLIT_OUT 22
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#define IMX_SC_R_DC_0_CAPTURE0 23
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#define IMX_SC_R_DC_0_CAPTURE1 24
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#define IMX_SC_R_PERF 23
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#define IMX_SC_R_DC_0_WARP 25
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#define IMX_SC_R_DC_0_INTEGRAL0 26
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#define IMX_SC_R_DC_0_INTEGRAL1 27
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#define IMX_SC_R_DC_0_VIDEO0 28
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#define IMX_SC_R_DC_0_VIDEO1 29
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#define IMX_SC_R_DC_0_FRAC0 30
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#define IMX_SC_R_DC_0_FRAC1 31
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#define IMX_SC_R_DC_0 32
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#define IMX_SC_R_GPU_2_PID0 33
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#define IMX_SC_R_DC_0_PLL_0 34
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@@ -53,17 +49,11 @@
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#define IMX_SC_R_DC_1_BLIT1 37
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#define IMX_SC_R_DC_1_BLIT2 38
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#define IMX_SC_R_DC_1_BLIT_OUT 39
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#define IMX_SC_R_DC_1_CAPTURE0 40
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#define IMX_SC_R_DC_1_CAPTURE1 41
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#define IMX_SC_R_DC_1_WARP 42
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#define IMX_SC_R_DC_1_INTEGRAL0 43
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#define IMX_SC_R_DC_1_INTEGRAL1 44
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#define IMX_SC_R_DC_1_VIDEO0 45
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#define IMX_SC_R_DC_1_VIDEO1 46
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#define IMX_SC_R_DC_1_FRAC0 47
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#define IMX_SC_R_DC_1_FRAC1 48
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#define IMX_SC_R_DC_1 49
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#define IMX_SC_R_GPU_3_PID0 50
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#define IMX_SC_R_DC_1_PLL_0 51
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#define IMX_SC_R_DC_1_PLL_1 52
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#define IMX_SC_R_SPI_0 53
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@@ -303,8 +293,6 @@
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#define IMX_SC_R_M4_0_UART 287
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#define IMX_SC_R_M4_0_I2C 288
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#define IMX_SC_R_M4_0_INTMUX 289
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#define IMX_SC_R_M4_0_SIM 290
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#define IMX_SC_R_M4_0_WDOG 291
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#define IMX_SC_R_M4_0_MU_0B 292
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#define IMX_SC_R_M4_0_MU_0A0 293
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#define IMX_SC_R_M4_0_MU_0A1 294
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@@ -323,8 +311,6 @@
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#define IMX_SC_R_M4_1_UART 307
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#define IMX_SC_R_M4_1_I2C 308
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#define IMX_SC_R_M4_1_INTMUX 309
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#define IMX_SC_R_M4_1_SIM 310
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#define IMX_SC_R_M4_1_WDOG 311
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#define IMX_SC_R_M4_1_MU_0B 312
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#define IMX_SC_R_M4_1_MU_0A0 313
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#define IMX_SC_R_M4_1_MU_0A1 314
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@@ -337,7 +323,7 @@
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#define IMX_SC_R_IRQSTR_SCU2 321
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#define IMX_SC_R_IRQSTR_DSP 322
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#define IMX_SC_R_ELCDIF_PLL 323
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#define IMX_SC_R_UNUSED6 324
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#define IMX_SC_R_OCRAM 324
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#define IMX_SC_R_AUDIO_PLL_0 325
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#define IMX_SC_R_PI_0 326
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#define IMX_SC_R_PI_0_PWM_0 327
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@@ -554,6 +540,11 @@
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#define IMX_SC_R_VPU_MU_3 538
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#define IMX_SC_R_VPU_ENC_1 539
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#define IMX_SC_R_VPU 540
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#define IMX_SC_R_LAST 541
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#define IMX_SC_R_DMA_5_CH0 541
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#define IMX_SC_R_DMA_5_CH1 542
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#define IMX_SC_R_DMA_5_CH2 543
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#define IMX_SC_R_DMA_5_CH3 544
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#define IMX_SC_R_ATTESTATION 545
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#define IMX_SC_R_LAST 546
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#endif /* __DT_BINDINGS_RSCRC_IMX_H */
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@@ -40,5 +40,133 @@
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#undef PIN_OFF_INPUT_PULLDOWN
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#undef PIN_OFF_WAKEUPENABLE
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#endif
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#define AM335X_PIN_OFFSET_MIN 0x0800U
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#define AM335X_PIN_GPMC_AD0 0x800
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#define AM335X_PIN_GPMC_AD1 0x804
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#define AM335X_PIN_GPMC_AD2 0x808
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#define AM335X_PIN_GPMC_AD3 0x80c
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#define AM335X_PIN_GPMC_AD4 0x810
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#define AM335X_PIN_GPMC_AD5 0x814
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#define AM335X_PIN_GPMC_AD6 0x818
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#define AM335X_PIN_GPMC_AD7 0x81c
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#define AM335X_PIN_GPMC_AD8 0x820
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#define AM335X_PIN_GPMC_AD9 0x824
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#define AM335X_PIN_GPMC_AD10 0x828
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#define AM335X_PIN_GPMC_AD11 0x82c
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#define AM335X_PIN_GPMC_AD12 0x830
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#define AM335X_PIN_GPMC_AD13 0x834
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#define AM335X_PIN_GPMC_AD14 0x838
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#define AM335X_PIN_GPMC_AD15 0x83c
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#define AM335X_PIN_GPMC_A0 0x840
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#define AM335X_PIN_GPMC_A1 0x844
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#define AM335X_PIN_GPMC_A2 0x848
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#define AM335X_PIN_GPMC_A3 0x84c
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#define AM335X_PIN_GPMC_A4 0x850
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#define AM335X_PIN_GPMC_A5 0x854
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#define AM335X_PIN_GPMC_A6 0x858
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#define AM335X_PIN_GPMC_A7 0x85c
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#define AM335X_PIN_GPMC_A8 0x860
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#define AM335X_PIN_GPMC_A9 0x864
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#define AM335X_PIN_GPMC_A10 0x868
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#define AM335X_PIN_GPMC_A11 0x86c
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#define AM335X_PIN_GPMC_WAIT0 0x870
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#define AM335X_PIN_GPMC_WPN 0x874
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#define AM335X_PIN_GPMC_BEN1 0x878
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#define AM335X_PIN_GPMC_CSN0 0x87c
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#define AM335X_PIN_GPMC_CSN1 0x880
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#define AM335X_PIN_GPMC_CSN2 0x884
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#define AM335X_PIN_GPMC_CSN3 0x888
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#define AM335X_PIN_GPMC_CLK 0x88c
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#define AM335X_PIN_GPMC_ADVN_ALE 0x890
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#define AM335X_PIN_GPMC_OEN_REN 0x894
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#define AM335X_PIN_GPMC_WEN 0x898
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#define AM335X_PIN_GPMC_BEN0_CLE 0x89c
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#define AM335X_PIN_LCD_DATA0 0x8a0
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#define AM335X_PIN_LCD_DATA1 0x8a4
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#define AM335X_PIN_LCD_DATA2 0x8a8
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#define AM335X_PIN_LCD_DATA3 0x8ac
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#define AM335X_PIN_LCD_DATA4 0x8b0
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#define AM335X_PIN_LCD_DATA5 0x8b4
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#define AM335X_PIN_LCD_DATA6 0x8b8
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#define AM335X_PIN_LCD_DATA7 0x8bc
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#define AM335X_PIN_LCD_DATA8 0x8c0
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#define AM335X_PIN_LCD_DATA9 0x8c4
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#define AM335X_PIN_LCD_DATA10 0x8c8
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#define AM335X_PIN_LCD_DATA11 0x8cc
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#define AM335X_PIN_LCD_DATA12 0x8d0
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#define AM335X_PIN_LCD_DATA13 0x8d4
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#define AM335X_PIN_LCD_DATA14 0x8d8
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#define AM335X_PIN_LCD_DATA15 0x8dc
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#define AM335X_PIN_LCD_VSYNC 0x8e0
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#define AM335X_PIN_LCD_HSYNC 0x8e4
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#define AM335X_PIN_LCD_PCLK 0x8e8
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#define AM335X_PIN_LCD_AC_BIAS_EN 0x8ec
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#define AM335X_PIN_MMC0_DAT3 0x8f0
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#define AM335X_PIN_MMC0_DAT2 0x8f4
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#define AM335X_PIN_MMC0_DAT1 0x8f8
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#define AM335X_PIN_MMC0_DAT0 0x8fc
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#define AM335X_PIN_MMC0_CLK 0x900
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#define AM335X_PIN_MMC0_CMD 0x904
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#define AM335X_PIN_MII1_COL 0x908
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#define AM335X_PIN_MII1_CRS 0x90c
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#define AM335X_PIN_MII1_RX_ER 0x910
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#define AM335X_PIN_MII1_TX_EN 0x914
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#define AM335X_PIN_MII1_RX_DV 0x918
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#define AM335X_PIN_MII1_TXD3 0x91c
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#define AM335X_PIN_MII1_TXD2 0x920
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#define AM335X_PIN_MII1_TXD1 0x924
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#define AM335X_PIN_MII1_TXD0 0x928
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#define AM335X_PIN_MII1_TX_CLK 0x92c
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#define AM335X_PIN_MII1_RX_CLK 0x930
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#define AM335X_PIN_MII1_RXD3 0x934
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#define AM335X_PIN_MII1_RXD2 0x938
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#define AM335X_PIN_MII1_RXD1 0x93c
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#define AM335X_PIN_MII1_RXD0 0x940
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#define AM335X_PIN_RMII1_REF_CLK 0x944
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#define AM335X_PIN_MDIO 0x948
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#define AM335X_PIN_MDC 0x94c
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#define AM335X_PIN_SPI0_SCLK 0x950
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#define AM335X_PIN_SPI0_D0 0x954
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#define AM335X_PIN_SPI0_D1 0x958
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#define AM335X_PIN_SPI0_CS0 0x95c
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#define AM335X_PIN_SPI0_CS1 0x960
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#define AM335X_PIN_ECAP0_IN_PWM0_OUT 0x964
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#define AM335X_PIN_UART0_CTSN 0x968
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#define AM335X_PIN_UART0_RTSN 0x96c
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#define AM335X_PIN_UART0_RXD 0x970
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#define AM335X_PIN_UART0_TXD 0x974
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#define AM335X_PIN_UART1_CTSN 0x978
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#define AM335X_PIN_UART1_RTSN 0x97c
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#define AM335X_PIN_UART1_RXD 0x980
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#define AM335X_PIN_UART1_TXD 0x984
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#define AM335X_PIN_I2C0_SDA 0x988
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#define AM335X_PIN_I2C0_SCL 0x98c
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#define AM335X_PIN_MCASP0_ACLKX 0x990
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#define AM335X_PIN_MCASP0_FSX 0x994
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#define AM335X_PIN_MCASP0_AXR0 0x998
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#define AM335X_PIN_MCASP0_AHCLKR 0x99c
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#define AM335X_PIN_MCASP0_ACLKR 0x9a0
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#define AM335X_PIN_MCASP0_FSR 0x9a4
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#define AM335X_PIN_MCASP0_AXR1 0x9a8
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#define AM335X_PIN_MCASP0_AHCLKX 0x9ac
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#define AM335X_PIN_XDMA_EVENT_INTR0 0x9b0
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#define AM335X_PIN_XDMA_EVENT_INTR1 0x9b4
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#define AM335X_PIN_WARMRSTN 0x9b8
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#define AM335X_PIN_NNMI 0x9c0
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#define AM335X_PIN_TMS 0x9d0
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#define AM335X_PIN_TDI 0x9d4
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#define AM335X_PIN_TDO 0x9d8
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#define AM335X_PIN_TCK 0x9dc
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#define AM335X_PIN_TRSTN 0x9e0
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#define AM335X_PIN_EMU0 0x9e4
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#define AM335X_PIN_EMU1 0x9e8
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#define AM335X_PIN_RTC_PWRONRSTN 0x9f8
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#define AM335X_PIN_PMIC_POWER_EN 0x9fc
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#define AM335X_PIN_EXT_WAKEUP 0xa00
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#define AM335X_PIN_USB0_DRVVBUS 0xa1c
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#define AM335X_PIN_USB1_DRVVBUS 0xa34
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#define AM335X_PIN_OFFSET_MAX 0x0a34U
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#endif
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@@ -65,6 +65,7 @@
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#define DM814X_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val)
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#define DM816X_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val)
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#define AM33XX_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val)
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#define AM33XX_PADCONF(pa, dir, mux) OMAP_IOPAD_OFFSET((pa), 0x0800) ((dir) | (mux))
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/*
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* Macros to allow using the offset from the padconf physical address
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@@ -21,7 +21,6 @@
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#define R8A77965_PD_A3VC 14
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#define R8A77965_PD_3DG_A 17
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#define R8A77965_PD_3DG_B 18
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#define R8A77965_PD_A3IR 24
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#define R8A77965_PD_A2VC1 26
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/* Always-on power area */
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