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clk: qcom: gdsc: Add support to poll CFG register to check GDSC state

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The default behavior of the GDSC enable/disable sequence is to
poll the status bits of either the actual GDSCR or the
corresponding HW_CTRL registers.

On targets which have support for a CFG_GDSCR register, the
status bits might not show the correct state of the GDSC,
especially in the disable sequence, where the status bit
will be cleared even before the core is completely power
collapsed. On targets with this issue, poll the power on/off
bits in the CFG_GDSCR register instead to correctly determine
the GDSC state.

Signed-off-by: Amit Nischal <anischal@codeaurora.org>
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Amit Nischal
2018-05-01 10:33:33 +05:30
committed by Stephen Boyd
parent 9fb38caee2
commit e892e17d0c
2 changed files with 27 additions and 16 deletions
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1
drivers/clk/qcom/gdsc.h
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@@ -55,6 +55,7 @@ struct gdsc {
#define HW_CTRL BIT(2)
#define SW_RESET BIT(3)
#define AON_RESET BIT(4)
#define POLL_CFG_GDSCR BIT(5)
struct reset_controller_dev *rcdev;
unsigned int *resets;
unsigned int reset_count;