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arm64: dts: mt8173: fix some indentation

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Fix indentation nits to make mt8173.dtsi more consistent.

Signed-off-by: Eddie Huang <eddie.huang@mediatek.com>
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
This commit is contained in:
Daniel Kurtz
2015-05-20 18:20:07 +08:00
committed by Matthias Brugger
parent 6769b93c08
commit e881ad1bc6
1 changed files with 9 additions and 10 deletions
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19
arch/arm64/boot/dts/mediatek/mt8173.dtsi
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@@ -91,13 +91,13 @@
compatible = "arm,armv8-timer"; compatible = "arm,armv8-timer";
interrupt-parent = <&gic>; interrupt-parent = <&gic>;
interrupts = <GIC_PPI 13 interrupts = <GIC_PPI 13
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 <GIC_PPI 14
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 <GIC_PPI 11
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 <GIC_PPI 10
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
}; };
soc { soc {
@@ -131,7 +131,7 @@
sysirq: intpol-controller@10200620 { sysirq: intpol-controller@10200620 {
compatible = "mediatek,mt8173-sysirq", compatible = "mediatek,mt8173-sysirq",
"mediatek,mt6577-sysirq"; "mediatek,mt6577-sysirq";
interrupt-controller; interrupt-controller;
#interrupt-cells = <3>; #interrupt-cells = <3>;
interrupt-parent = <&gic>; interrupt-parent = <&gic>;
@@ -153,7 +153,7 @@
uart0: serial@11002000 { uart0: serial@11002000 {
compatible = "mediatek,mt8173-uart", compatible = "mediatek,mt8173-uart",
"mediatek,mt6577-uart"; "mediatek,mt6577-uart";
reg = <0 0x11002000 0 0x400>; reg = <0 0x11002000 0 0x400>;
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>; interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>;
clocks = <&uart_clk>; clocks = <&uart_clk>;
@@ -162,7 +162,7 @@
uart1: serial@11003000 { uart1: serial@11003000 {
compatible = "mediatek,mt8173-uart", compatible = "mediatek,mt8173-uart",
"mediatek,mt6577-uart"; "mediatek,mt6577-uart";
reg = <0 0x11003000 0 0x400>; reg = <0 0x11003000 0 0x400>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
clocks = <&uart_clk>; clocks = <&uart_clk>;
@@ -171,7 +171,7 @@
uart2: serial@11004000 { uart2: serial@11004000 {
compatible = "mediatek,mt8173-uart", compatible = "mediatek,mt8173-uart",
"mediatek,mt6577-uart"; "mediatek,mt6577-uart";
reg = <0 0x11004000 0 0x400>; reg = <0 0x11004000 0 0x400>;
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
clocks = <&uart_clk>; clocks = <&uart_clk>;
@@ -180,13 +180,12 @@
uart3: serial@11005000 { uart3: serial@11005000 {
compatible = "mediatek,mt8173-uart", compatible = "mediatek,mt8173-uart",
"mediatek,mt6577-uart"; "mediatek,mt6577-uart";
reg = <0 0x11005000 0 0x400>; reg = <0 0x11005000 0 0x400>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
clocks = <&uart_clk>; clocks = <&uart_clk>;
status = "disabled"; status = "disabled";
}; };
}; };
}; };