RDMA/cxgb3: MEM_MGT_EXTENSIONS support
- set IB_DEVICE_MEM_MGT_EXTENSIONS capability bit if fw supports it. - set max_fast_reg_page_list_len device attribute. - add iwch_alloc_fast_reg_mr function. - add iwch_alloc_fastreg_pbl - add iwch_free_fastreg_pbl - adjust the WQ depth for kernel mode work queues to account for fastreg possibly taking 2 WR slots. - add fastreg_mr work request support. - add local_inv work request support. - add send_with_inv and send_with_se_inv work request support. - removed useless duplicate enums/defines for TPT/MW/MR stuff. Signed-off-by: Steve Wise <swise@opengridcomputing.com> Signed-off-by: Roland Dreier <rolandd@cisco.com>
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committed by
Roland Dreier

parent
00f7ec36c9
commit
e7e5582999
@@ -81,6 +81,7 @@ static int iwch_poll_cq_one(struct iwch_dev *rhp, struct iwch_cq *chp,
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wc->wr_id = cookie;
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wc->qp = &qhp->ibqp;
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wc->vendor_err = CQE_STATUS(cqe);
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wc->wc_flags = 0;
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PDBG("%s qpid 0x%x type %d opcode %d status 0x%x wrid hi 0x%x "
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"lo 0x%x cookie 0x%llx\n", __func__,
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@@ -94,6 +95,11 @@ static int iwch_poll_cq_one(struct iwch_dev *rhp, struct iwch_cq *chp,
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else
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wc->byte_len = 0;
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wc->opcode = IB_WC_RECV;
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if (CQE_OPCODE(cqe) == T3_SEND_WITH_INV ||
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CQE_OPCODE(cqe) == T3_SEND_WITH_SE_INV) {
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wc->ex.invalidate_rkey = CQE_WRID_STAG(cqe);
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wc->wc_flags |= IB_WC_WITH_INVALIDATE;
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}
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} else {
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switch (CQE_OPCODE(cqe)) {
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case T3_RDMA_WRITE:
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@@ -105,17 +111,20 @@ static int iwch_poll_cq_one(struct iwch_dev *rhp, struct iwch_cq *chp,
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break;
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case T3_SEND:
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case T3_SEND_WITH_SE:
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case T3_SEND_WITH_INV:
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case T3_SEND_WITH_SE_INV:
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wc->opcode = IB_WC_SEND;
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break;
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case T3_BIND_MW:
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wc->opcode = IB_WC_BIND_MW;
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break;
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/* these aren't supported yet */
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case T3_SEND_WITH_INV:
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case T3_SEND_WITH_SE_INV:
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case T3_LOCAL_INV:
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wc->opcode = IB_WC_LOCAL_INV;
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break;
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case T3_FAST_REGISTER:
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wc->opcode = IB_WC_FAST_REG_MR;
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break;
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default:
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printk(KERN_ERR MOD "Unexpected opcode %d "
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"in the CQE received for QPID=0x%0x\n",
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