Merge tag v4.15 of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git
To resolve conflicts in: drivers/infiniband/hw/mlx5/main.c drivers/infiniband/hw/mlx5/qp.c From patches merged into the -rc cycle. The conflict resolution matches what linux-next has been carrying. Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
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@@ -36,6 +36,7 @@
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#include <linux/kernel.h>
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#include <linux/completion.h>
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#include <linux/pci.h>
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#include <linux/irq.h>
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#include <linux/spinlock_types.h>
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#include <linux/semaphore.h>
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#include <linux/slab.h>
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@@ -567,6 +568,7 @@ struct mlx5_core_sriov {
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};
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struct mlx5_irq_info {
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cpumask_var_t mask;
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char name[MLX5_MAX_IRQ_NAME];
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};
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@@ -1062,7 +1064,7 @@ int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx,
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enum mlx5_eq_type type);
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int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
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int mlx5_start_eqs(struct mlx5_core_dev *dev);
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int mlx5_stop_eqs(struct mlx5_core_dev *dev);
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void mlx5_stop_eqs(struct mlx5_core_dev *dev);
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int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn,
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unsigned int *irqn);
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int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
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@@ -1269,7 +1271,23 @@ enum {
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static inline const struct cpumask *
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mlx5_get_vector_affinity(struct mlx5_core_dev *dev, int vector)
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{
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return pci_irq_get_affinity(dev->pdev, MLX5_EQ_VEC_COMP_BASE + vector);
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const struct cpumask *mask;
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struct irq_desc *desc;
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unsigned int irq;
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int eqn;
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int err;
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err = mlx5_vector2eqn(dev, vector, &eqn, &irq);
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if (err)
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return NULL;
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desc = irq_to_desc(irq);
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#ifdef CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK
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mask = irq_data_get_effective_affinity_mask(&desc->irq_data);
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#else
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mask = desc->irq_common_data.affinity;
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#endif
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return mask;
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}
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#endif /* MLX5_DRIVER_H */
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@@ -147,7 +147,7 @@ enum {
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MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
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MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
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MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
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MLX5_CMD_OP_SET_RATE_LIMIT = 0x780,
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MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780,
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MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781,
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MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782,
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MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783,
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@@ -1030,8 +1030,9 @@ struct mlx5_ifc_cmd_hca_cap_bits {
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u8 log_max_wq_sz[0x5];
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u8 nic_vport_change_event[0x1];
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u8 disable_local_lb[0x1];
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u8 reserved_at_3e2[0x9];
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u8 disable_local_lb_uc[0x1];
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u8 disable_local_lb_mc[0x1];
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u8 reserved_at_3e3[0x8];
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u8 log_max_vlan_list[0x5];
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u8 reserved_at_3f0[0x3];
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u8 log_max_current_mc_list[0x5];
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@@ -7257,7 +7258,7 @@ struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
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u8 vxlan_udp_port[0x10];
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};
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struct mlx5_ifc_set_rate_limit_out_bits {
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struct mlx5_ifc_set_pp_rate_limit_out_bits {
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u8 status[0x8];
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u8 reserved_at_8[0x18];
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@@ -7266,7 +7267,7 @@ struct mlx5_ifc_set_rate_limit_out_bits {
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u8 reserved_at_40[0x40];
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};
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struct mlx5_ifc_set_rate_limit_in_bits {
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struct mlx5_ifc_set_pp_rate_limit_in_bits {
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u8 opcode[0x10];
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u8 reserved_at_10[0x10];
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@@ -7279,6 +7280,8 @@ struct mlx5_ifc_set_rate_limit_in_bits {
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u8 reserved_at_60[0x20];
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u8 rate_limit[0x20];
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u8 reserved_at_a0[0x160];
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};
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struct mlx5_ifc_access_register_out_bits {
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