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drm/i915/icl: Program DSI clock and data lane timing params

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This patch programs D-PHY timing parameters for the
clock and data lane (in escape clocks) of DSI
controller (DSI port 0 and 1).
These programmed timings would be used by DSI Controller
to calculate link transition latencies of the data and
clock lanes.

v2: Use newly defined bitfields for data and clock lane

v3 by Jani:
 - Rebase on dphy abstraction
 - Reduce local variables
 - Remove unrelated comment changes (Ville)
 - Use the same style for range checks as VLV (Ville)
 - Assign, don't OR dphy_reg contents

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/70d491e2357f328a63b67ea3c43cb57a1d469c15.1539613303.git.jani.nikula@intel.com
This commit is contained in:
Madhav Chauhan
2018-10-15 17:27:54 +03:00
committed by Jani Nikula
parent b687c1984c
commit e72cce5310
3 changed files with 130 additions and 1 deletions
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18
drivers/gpu/drm/i915/icl_dsi.c
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@@ -291,6 +291,24 @@ static void gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder)
tmp |= intel_dsi->init_count;
I915_WRITE(ICL_DSI_T_INIT_MASTER(port), tmp);
}
/* Program DPHY clock lanes timings */
for_each_dsi_port(port, intel_dsi->ports) {
I915_WRITE(DPHY_CLK_TIMING_PARAM(port), intel_dsi->dphy_reg);
/* shadow register inside display core */
I915_WRITE(DSI_CLK_TIMING_PARAM(port), intel_dsi->dphy_reg);
}
/* Program DPHY data lanes timings */
for_each_dsi_port(port, intel_dsi->ports) {
I915_WRITE(DPHY_DATA_TIMING_PARAM(port),
intel_dsi->dphy_data_lane_reg);
/* shadow register inside display core */
I915_WRITE(DSI_DATA_TIMING_PARAM(port),
intel_dsi->dphy_data_lane_reg);
}
}
static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)