firewire: ohci: do not clear PHY interrupt status inadvertently
The interrupt status bits in PHY register 5 are cleared by writing a one bit. To avoid clearing them unadvertently, do not write them back when they were read as set, but only when they have been explicitly requested to be set. Signed-off-by: Clemens Ladisch <clemens@ladisch.de> Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
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Stefan Richter

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@@ -28,6 +28,7 @@ struct fw_packet;
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#define PHY_CONTENDER 0x40
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#define PHY_BUS_RESET 0x40
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#define PHY_BUS_SHORT_RESET 0x40
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#define PHY_INT_STATUS_BITS 0x3c
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#define BANDWIDTH_AVAILABLE_INITIAL 4915
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#define BROADCAST_CHANNEL_INITIAL (1 << 31 | 31)
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