soc/fsl/qbman: Rework portal mapping calls for ARM/PPC
Rework portal mapping for PPC and ARM. The PPC devices require a cacheable coherent mapping while ARM will work with a non-cachable/write combine mapping. This also eliminates the need for manual cache flushes on ARM. This also fixes the code so sparse checking is clean. Signed-off-by: Roy Pledge <roy.pledge@nxp.com> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Li Yang <leoyang.li@nxp.com>
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@@ -153,11 +153,9 @@ static inline void qman_cgrs_xor(struct qman_cgrs *dest,
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void qman_init_cgr_all(void);
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struct qm_portal_config {
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/*
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* Corenet portal addresses;
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* [0]==cache-enabled, [1]==cache-inhibited.
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*/
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void __iomem *addr_virt[2];
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/* Portal addresses */
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void *addr_virt_ce;
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void __iomem *addr_virt_ci;
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struct device *dev;
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struct iommu_domain *iommu_domain;
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/* Allow these to be joined in lists */
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