Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus
Pull MIPS updates from Ralf Baechle: "This is the main pull request for 3.17. It contains: - misc Cavium Octeon, BCM47xx, BCM63xx and Alchemy updates - MIPS ptrace updates and cleanups - various fixes that will also go to -stable - a number of cleanups and small non-critical fixes. - NUMA support for the Loongson 3. - more support for MSA - support for MAAR - various FP enhancements and fixes" * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (139 commits) MIPS: jz4740: remove unnecessary null test before debugfs_remove MIPS: Octeon: remove unnecessary null test before debugfs_remove_recursive MIPS: ZBOOT: implement stack protector in compressed boot phase MIPS: mipsreg: remove duplicate MIPS_CONF4_FTLBSETS_SHIFT MIPS: Bonito64: remove a duplicate define MIPS: Malta: initialise MAARs MIPS: Initialise MAARs MIPS: detect presence of MAARs MIPS: define MAAR register accessors & bits MIPS: mark MSA experimental MIPS: Don't build MSA support unless it can be used MIPS: consistently clear MSA flags when starting & copying threads MIPS: 16 byte align MSA vector context MIPS: disable preemption whilst initialising MSA MIPS: ensure MSA gets disabled during boot MIPS: fix read_msa_* & write_msa_* functions on non-MSA toolchains MIPS: fix MSA context for tasks which don't use FP first MIPS: init upper 64b of vector registers when MSA is first used MIPS: save/disable MSA in lose_fpu MIPS: preserve scalar FP CSR when switching vector context ...
This commit is contained in:
Linus Torvalds
@@ -89,6 +89,124 @@ MODULE_DESCRIPTION(DRV_DESC);
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MODULE_LICENSE("GPL");
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MODULE_VERSION(DRV_VERSION);
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/* AU1000 MAC registers and bits */
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#define MAC_CONTROL 0x0
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# define MAC_RX_ENABLE (1 << 2)
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# define MAC_TX_ENABLE (1 << 3)
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# define MAC_DEF_CHECK (1 << 5)
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# define MAC_SET_BL(X) (((X) & 0x3) << 6)
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# define MAC_AUTO_PAD (1 << 8)
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# define MAC_DISABLE_RETRY (1 << 10)
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# define MAC_DISABLE_BCAST (1 << 11)
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# define MAC_LATE_COL (1 << 12)
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# define MAC_HASH_MODE (1 << 13)
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# define MAC_HASH_ONLY (1 << 15)
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# define MAC_PASS_ALL (1 << 16)
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# define MAC_INVERSE_FILTER (1 << 17)
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# define MAC_PROMISCUOUS (1 << 18)
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# define MAC_PASS_ALL_MULTI (1 << 19)
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# define MAC_FULL_DUPLEX (1 << 20)
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# define MAC_NORMAL_MODE 0
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# define MAC_INT_LOOPBACK (1 << 21)
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# define MAC_EXT_LOOPBACK (1 << 22)
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# define MAC_DISABLE_RX_OWN (1 << 23)
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# define MAC_BIG_ENDIAN (1 << 30)
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# define MAC_RX_ALL (1 << 31)
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#define MAC_ADDRESS_HIGH 0x4
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#define MAC_ADDRESS_LOW 0x8
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#define MAC_MCAST_HIGH 0xC
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#define MAC_MCAST_LOW 0x10
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#define MAC_MII_CNTRL 0x14
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# define MAC_MII_BUSY (1 << 0)
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# define MAC_MII_READ 0
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# define MAC_MII_WRITE (1 << 1)
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# define MAC_SET_MII_SELECT_REG(X) (((X) & 0x1f) << 6)
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# define MAC_SET_MII_SELECT_PHY(X) (((X) & 0x1f) << 11)
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#define MAC_MII_DATA 0x18
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#define MAC_FLOW_CNTRL 0x1C
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# define MAC_FLOW_CNTRL_BUSY (1 << 0)
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# define MAC_FLOW_CNTRL_ENABLE (1 << 1)
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# define MAC_PASS_CONTROL (1 << 2)
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# define MAC_SET_PAUSE(X) (((X) & 0xffff) << 16)
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#define MAC_VLAN1_TAG 0x20
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#define MAC_VLAN2_TAG 0x24
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/* Ethernet Controller Enable */
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# define MAC_EN_CLOCK_ENABLE (1 << 0)
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# define MAC_EN_RESET0 (1 << 1)
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# define MAC_EN_TOSS (0 << 2)
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# define MAC_EN_CACHEABLE (1 << 3)
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# define MAC_EN_RESET1 (1 << 4)
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# define MAC_EN_RESET2 (1 << 5)
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# define MAC_DMA_RESET (1 << 6)
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/* Ethernet Controller DMA Channels */
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/* offsets from MAC_TX_RING_ADDR address */
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#define MAC_TX_BUFF0_STATUS 0x0
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# define TX_FRAME_ABORTED (1 << 0)
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# define TX_JAB_TIMEOUT (1 << 1)
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# define TX_NO_CARRIER (1 << 2)
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# define TX_LOSS_CARRIER (1 << 3)
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# define TX_EXC_DEF (1 << 4)
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# define TX_LATE_COLL_ABORT (1 << 5)
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# define TX_EXC_COLL (1 << 6)
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# define TX_UNDERRUN (1 << 7)
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# define TX_DEFERRED (1 << 8)
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# define TX_LATE_COLL (1 << 9)
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# define TX_COLL_CNT_MASK (0xF << 10)
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# define TX_PKT_RETRY (1 << 31)
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#define MAC_TX_BUFF0_ADDR 0x4
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# define TX_DMA_ENABLE (1 << 0)
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# define TX_T_DONE (1 << 1)
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# define TX_GET_DMA_BUFFER(X) (((X) >> 2) & 0x3)
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#define MAC_TX_BUFF0_LEN 0x8
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#define MAC_TX_BUFF1_STATUS 0x10
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#define MAC_TX_BUFF1_ADDR 0x14
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#define MAC_TX_BUFF1_LEN 0x18
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#define MAC_TX_BUFF2_STATUS 0x20
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#define MAC_TX_BUFF2_ADDR 0x24
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#define MAC_TX_BUFF2_LEN 0x28
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#define MAC_TX_BUFF3_STATUS 0x30
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#define MAC_TX_BUFF3_ADDR 0x34
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#define MAC_TX_BUFF3_LEN 0x38
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/* offsets from MAC_RX_RING_ADDR */
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#define MAC_RX_BUFF0_STATUS 0x0
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# define RX_FRAME_LEN_MASK 0x3fff
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# define RX_WDOG_TIMER (1 << 14)
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# define RX_RUNT (1 << 15)
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# define RX_OVERLEN (1 << 16)
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# define RX_COLL (1 << 17)
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# define RX_ETHER (1 << 18)
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# define RX_MII_ERROR (1 << 19)
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# define RX_DRIBBLING (1 << 20)
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# define RX_CRC_ERROR (1 << 21)
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# define RX_VLAN1 (1 << 22)
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# define RX_VLAN2 (1 << 23)
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# define RX_LEN_ERROR (1 << 24)
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# define RX_CNTRL_FRAME (1 << 25)
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# define RX_U_CNTRL_FRAME (1 << 26)
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# define RX_MCAST_FRAME (1 << 27)
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# define RX_BCAST_FRAME (1 << 28)
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# define RX_FILTER_FAIL (1 << 29)
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# define RX_PACKET_FILTER (1 << 30)
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# define RX_MISSED_FRAME (1 << 31)
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# define RX_ERROR (RX_WDOG_TIMER | RX_RUNT | RX_OVERLEN | \
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RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | \
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RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME)
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#define MAC_RX_BUFF0_ADDR 0x4
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# define RX_DMA_ENABLE (1 << 0)
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# define RX_T_DONE (1 << 1)
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# define RX_GET_DMA_BUFFER(X) (((X) >> 2) & 0x3)
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# define RX_SET_BUFF_ADDR(X) ((X) & 0xffffffc0)
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#define MAC_RX_BUFF1_STATUS 0x10
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#define MAC_RX_BUFF1_ADDR 0x14
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#define MAC_RX_BUFF2_STATUS 0x20
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#define MAC_RX_BUFF2_ADDR 0x24
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#define MAC_RX_BUFF3_STATUS 0x30
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#define MAC_RX_BUFF3_ADDR 0x34
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/*
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* Theory of operation
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*
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@@ -152,10 +270,12 @@ static void au1000_enable_mac(struct net_device *dev, int force_reset)
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if (force_reset || (!aup->mac_enabled)) {
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writel(MAC_EN_CLOCK_ENABLE, aup->enable);
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au_sync_delay(2);
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wmb(); /* drain writebuffer */
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mdelay(2);
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writel((MAC_EN_RESET0 | MAC_EN_RESET1 | MAC_EN_RESET2
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| MAC_EN_CLOCK_ENABLE), aup->enable);
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au_sync_delay(2);
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wmb(); /* drain writebuffer */
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mdelay(2);
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aup->mac_enabled = 1;
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}
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@@ -273,7 +393,8 @@ static void au1000_hard_stop(struct net_device *dev)
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reg = readl(&aup->mac->control);
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reg &= ~(MAC_RX_ENABLE | MAC_TX_ENABLE);
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writel(reg, &aup->mac->control);
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au_sync_delay(10);
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wmb(); /* drain writebuffer */
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mdelay(10);
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}
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static void au1000_enable_rx_tx(struct net_device *dev)
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@@ -286,7 +407,8 @@ static void au1000_enable_rx_tx(struct net_device *dev)
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reg = readl(&aup->mac->control);
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reg |= (MAC_RX_ENABLE | MAC_TX_ENABLE);
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writel(reg, &aup->mac->control);
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au_sync_delay(10);
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wmb(); /* drain writebuffer */
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mdelay(10);
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}
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static void
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@@ -336,7 +458,8 @@ au1000_adjust_link(struct net_device *dev)
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reg |= MAC_DISABLE_RX_OWN;
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}
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writel(reg, &aup->mac->control);
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au_sync_delay(1);
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wmb(); /* drain writebuffer */
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mdelay(1);
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au1000_enable_rx_tx(dev);
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aup->old_duplex = phydev->duplex;
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@@ -500,9 +623,11 @@ static void au1000_reset_mac_unlocked(struct net_device *dev)
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au1000_hard_stop(dev);
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writel(MAC_EN_CLOCK_ENABLE, aup->enable);
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au_sync_delay(2);
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wmb(); /* drain writebuffer */
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mdelay(2);
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writel(0, aup->enable);
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au_sync_delay(2);
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wmb(); /* drain writebuffer */
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mdelay(2);
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aup->tx_full = 0;
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for (i = 0; i < NUM_RX_DMA; i++) {
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@@ -652,7 +777,7 @@ static int au1000_init(struct net_device *dev)
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for (i = 0; i < NUM_RX_DMA; i++)
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aup->rx_dma_ring[i]->buff_stat |= RX_DMA_ENABLE;
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au_sync();
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wmb(); /* drain writebuffer */
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control = MAC_RX_ENABLE | MAC_TX_ENABLE;
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#ifndef CONFIG_CPU_LITTLE_ENDIAN
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@@ -669,7 +794,7 @@ static int au1000_init(struct net_device *dev)
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writel(control, &aup->mac->control);
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writel(0x8100, &aup->mac->vlan1_tag); /* activate vlan support */
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au_sync();
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wmb(); /* drain writebuffer */
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spin_unlock_irqrestore(&aup->lock, flags);
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return 0;
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@@ -760,7 +885,7 @@ static int au1000_rx(struct net_device *dev)
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}
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prxd->buff_stat = (u32)(pDB->dma_addr | RX_DMA_ENABLE);
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aup->rx_head = (aup->rx_head + 1) & (NUM_RX_DMA - 1);
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au_sync();
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wmb(); /* drain writebuffer */
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/* next descriptor */
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prxd = aup->rx_dma_ring[aup->rx_head];
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@@ -808,7 +933,7 @@ static void au1000_tx_ack(struct net_device *dev)
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au1000_update_tx_stats(dev, ptxd->status);
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ptxd->buff_stat &= ~TX_T_DONE;
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ptxd->len = 0;
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au_sync();
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wmb(); /* drain writebuffer */
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aup->tx_tail = (aup->tx_tail + 1) & (NUM_TX_DMA - 1);
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ptxd = aup->tx_dma_ring[aup->tx_tail];
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@@ -939,7 +1064,7 @@ static netdev_tx_t au1000_tx(struct sk_buff *skb, struct net_device *dev)
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ps->tx_bytes += ptxd->len;
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ptxd->buff_stat = pDB->dma_addr | TX_DMA_ENABLE;
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au_sync();
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wmb(); /* drain writebuffer */
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dev_kfree_skb(skb);
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aup->tx_head = (aup->tx_head + 1) & (NUM_TX_DMA - 1);
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return NETDEV_TX_OK;
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