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Merge tag 'phy-for-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy into char-misc-next

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Kishon writes:

phy: for 5.4

  *) Add a new PHY driver for Lantiq VRX200/ARX300 PCIe PHY
  *) Add missing of_node_put() to a bunch of drivers using
     for_each_available_child_of_node()
  *) Add RXAUI/PCIe/SATA/USB3 support in Marvell's Armada
     CP110 COMPHY
  *) Other misc fixes and cleanup

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>

* tag 'phy-for-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy: (30 commits)
  phy: marvell: phy-mvebu-cp110-comphy: rename instances of DLT
  phy: marvell: phy-mvebu-cp110-comphy: implement RXAUI support
  dt-bindings: pci: add PHY properties to Armada 7K/8K controller bindings
  dt-bindings: phy: Add Marvell COMPHY clocks
  phy: mvebu-cp110-comphy: Update comment about powering off all lanes at boot
  phy: mvebu-cp110-comphy: Add PCIe support
  phy: mvebu-cp110-comphy: Cosmetic change in a helper
  phy: mvebu-cp110-comphy: Add SATA support
  phy: mvebu-cp110-comphy: Add USB3 host/device support
  phy: mvebu-cp110-comphy: Allow non-Ethernet modes to be configured
  phy: mvebu-cp110-comphy: Rename the macro handling only Ethernet modes
  phy: mvebu-cp110-comphy: Add RXAUI support
  phy: mvebu-cp110-comphy: List already supported Ethernet modes
  phy: mvebu-cp110-comphy: Add SMC call support
  phy: mvebu-cp110-comphy: Explicitly initialize the lane submode
  phy: mvebu-cp110-comphy: Add clocks support
  phy-rockchip-inno-hdmi: Fix RK3328_TERM_RESISTOR_CALIB_SPEED_7_0's third value
  phy: qcom-qmp: Correct ready status, again
  phy: qualcomm: phy-qcom-qmp: Add of_node_put() before return
  phy: renesas: rcar-gen3-usb2: Disable clearing VBUS in over-current
  ...
This commit is contained in:
Greg Kroah-Hartman
2019-09-03 21:49:11 +02:00
parent 4a79ce748f 5af67635c3
commit e6508c7efa
23 changed files with 1188 additions and 90 deletions
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11
include/dt-bindings/phy/phy-lantiq-vrx200-pcie.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (C) 2019 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
*/
#define LANTIQ_PCIE_PHY_MODE_25MHZ 0
#define LANTIQ_PCIE_PHY_MODE_25MHZ_SSC 1
#define LANTIQ_PCIE_PHY_MODE_36MHZ 2
#define LANTIQ_PCIE_PHY_MODE_36MHZ_SSC 3
#define LANTIQ_PCIE_PHY_MODE_100MHZ 4
#define LANTIQ_PCIE_PHY_MODE_100MHZ_SSC 5