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MIPS: SGI-IP27: abstract chipset irq from bridge

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Bridge ASIC is widely used in different SGI systems, but the connected
chipset is either HUB, HEART or BEDROCK. This commit switches to
irq domain hierarchy for hub and bridge interrupts to get bridge
setup out of hub interrupt code.

Signed-off-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
[paul.burton@mips.com:
  Resolve conflict with commit 69a07a41d9 ("MIPS: SGI-IP27: rework HUB
  interrupts").]
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: James Hogan <jhogan@kernel.org>
Cc: linux-mips@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
This commit is contained in:
Thomas Bogendoerfer
2019-05-07 23:09:15 +02:00
committed by Paul Burton
parent a57140e9a8
commit e6308b6d35
5 changed files with 265 additions and 119 deletions
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3
arch/mips/include/asm/pci/bridge.h
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@@ -805,6 +805,7 @@ struct bridge_controller {
struct bridge_regs *base;
unsigned long baddr;
unsigned long intr_addr;
struct irq_domain *domain;
unsigned int pci_int[8];
nasid_t nasid;
};
@@ -819,6 +820,4 @@ struct bridge_controller {
#define bridge_clr(bc, reg, val) \
__raw_writel(__raw_readl(&bc->base->reg) & ~(val), &bc->base->reg)
extern int request_bridge_irq(struct bridge_controller *bc, int pin);
#endif /* _ASM_PCI_BRIDGE_H */