net: nps_enet: Tx handler synchronization
Below is a description of a possible problematic sequence. CPU-A is sending a frame and CPU-B handles the interrupt that indicates the frame was sent. CPU-B reads an invalid value of tx_packet_sent. CPU-A CPU-B ----- ----- nps_enet_send_frame . . tx_skb = skb tx_packet_sent = true order HW to start tx . . HW complete tx ------> get tx complete interrupt . . if(tx_packet_sent == true) handle tx_skb end memory transaction (tx_packet_sent actually written) Furthermore there is a dependency between tx_skb and tx_packet_sent. There is no assurance that tx_skb contains a valid pointer at CPU B when it sees tx_packet_sent == true. Solution: Initialize tx_skb to NULL and use it to indicate that packet was sent, in this way tx_packet_sent can be removed. Add a write memory barrier after setting tx_skb in order to make sure that it is valid before HW is informed and IRQ is fired. Fixed sequence will be: CPU-A CPU-B ----- ----- tx_skb = skb wmb() . . order HW to start tx . . HW complete tx ------> get tx complete interrupt . . if(tx_skb != NULL) handle tx_skb tx_skb = NULL Signed-off-by: Elad Kanfi <eladkan@mellanox.com> Acked-by: Noam Camus <noamca@mellanox.com> Acked-by: Gilad Ben-Yossef <giladby@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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David S. Miller

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commit
e5df49d564
@@ -165,14 +165,12 @@
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* struct nps_enet_priv - Storage of ENET's private information.
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* @regs_base: Base address of ENET memory-mapped control registers.
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* @irq: For RX/TX IRQ number.
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* @tx_packet_sent: SW indication if frame is being sent.
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* @tx_skb: socket buffer of sent frame.
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* @napi: Structure for NAPI.
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*/
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struct nps_enet_priv {
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void __iomem *regs_base;
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s32 irq;
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bool tx_packet_sent;
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struct sk_buff *tx_skb;
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struct napi_struct napi;
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u32 ge_mac_cfg_2_value;
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