MIPS: BCM63XX: Add basic BCM6328 support
This includes CPU speed, memory size detection and working UART, but lacking the appropriate drivers, no support for attached flash. Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com> Cc: linux-mips@linux-mips.org Cc: Maxime Bizon <mbizon@freebox.fr> Cc: Florian Fainelli <florian@openwrt.org> Cc: Kevin Cernekee <cernekee@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/3951/ Reviewed-by: Florian Fainelli <florian@openwrt.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Jonas Gorski
committed by
Ralf Baechle
Ralf Baechle
parent
288752a8aa
commit
e5766aea5b
@@ -9,6 +9,7 @@
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* compile time if only one CPU support is enabled (idea stolen from
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* arm mach-types)
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*/
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#define BCM6328_CPU_ID 0x6328
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#define BCM6338_CPU_ID 0x6338
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#define BCM6345_CPU_ID 0x6345
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#define BCM6348_CPU_ID 0x6348
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@@ -20,6 +21,19 @@ u16 __bcm63xx_get_cpu_id(void);
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u16 bcm63xx_get_cpu_rev(void);
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unsigned int bcm63xx_get_cpu_freq(void);
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#ifdef CONFIG_BCM63XX_CPU_6328
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# ifdef bcm63xx_get_cpu_id
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# undef bcm63xx_get_cpu_id
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# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
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# define BCMCPU_RUNTIME_DETECT
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# else
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# define bcm63xx_get_cpu_id() BCM6328_CPU_ID
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# endif
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# define BCMCPU_IS_6328() (bcm63xx_get_cpu_id() == BCM6328_CPU_ID)
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#else
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# define BCMCPU_IS_6328() (0)
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#endif
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#ifdef CONFIG_BCM63XX_CPU_6338
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# ifdef bcm63xx_get_cpu_id
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# undef bcm63xx_get_cpu_id
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@@ -129,7 +143,8 @@ enum bcm63xx_regs_set {
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RSET_PCMDMA,
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RSET_PCMDMAC,
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RSET_PCMDMAS,
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RSET_RNG
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RSET_RNG,
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RSET_MISC
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};
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#define RSET_DSL_LMEM_SIZE (64 * 1024 * 4)
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@@ -155,6 +170,49 @@ enum bcm63xx_regs_set {
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#define RSET_XTMDMAS_SIZE(chans) (16 * (chans))
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#define RSET_RNG_SIZE 20
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/*
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* 6328 register sets base address
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*/
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#define BCM_6328_DSL_LMEM_BASE (0xdeadbeef)
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#define BCM_6328_PERF_BASE (0xb0000000)
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#define BCM_6328_TIMER_BASE (0xb0000040)
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#define BCM_6328_WDT_BASE (0xb000005c)
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#define BCM_6328_UART0_BASE (0xb0000100)
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#define BCM_6328_UART1_BASE (0xb0000120)
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#define BCM_6328_GPIO_BASE (0xb0000080)
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#define BCM_6328_SPI_BASE (0xdeadbeef)
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#define BCM_6328_UDC0_BASE (0xdeadbeef)
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#define BCM_6328_USBDMA_BASE (0xdeadbeef)
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#define BCM_6328_OHCI0_BASE (0xdeadbeef)
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#define BCM_6328_OHCI_PRIV_BASE (0xdeadbeef)
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#define BCM_6328_USBH_PRIV_BASE (0xdeadbeef)
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#define BCM_6328_MPI_BASE (0xdeadbeef)
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#define BCM_6328_PCMCIA_BASE (0xdeadbeef)
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#define BCM_6328_SDRAM_REGS_BASE (0xdeadbeef)
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#define BCM_6328_DSL_BASE (0xb0001900)
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#define BCM_6328_UBUS_BASE (0xdeadbeef)
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#define BCM_6328_ENET0_BASE (0xdeadbeef)
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#define BCM_6328_ENET1_BASE (0xdeadbeef)
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#define BCM_6328_ENETDMA_BASE (0xb000d800)
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#define BCM_6328_ENETDMAC_BASE (0xb000da00)
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#define BCM_6328_ENETDMAS_BASE (0xb000dc00)
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#define BCM_6328_ENETSW_BASE (0xb0e00000)
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#define BCM_6328_EHCI0_BASE (0x10002500)
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#define BCM_6328_SDRAM_BASE (0xdeadbeef)
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#define BCM_6328_MEMC_BASE (0xdeadbeef)
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#define BCM_6328_DDR_BASE (0xb0003000)
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#define BCM_6328_M2M_BASE (0xdeadbeef)
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#define BCM_6328_ATM_BASE (0xdeadbeef)
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#define BCM_6328_XTM_BASE (0xdeadbeef)
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#define BCM_6328_XTMDMA_BASE (0xb000b800)
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#define BCM_6328_XTMDMAC_BASE (0xdeadbeef)
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#define BCM_6328_XTMDMAS_BASE (0xdeadbeef)
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#define BCM_6328_PCM_BASE (0xb000a800)
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#define BCM_6328_PCMDMA_BASE (0xdeadbeef)
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#define BCM_6328_PCMDMAC_BASE (0xdeadbeef)
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#define BCM_6328_PCMDMAS_BASE (0xdeadbeef)
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#define BCM_6328_RNG_BASE (0xdeadbeef)
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#define BCM_6328_MISC_BASE (0xb0001800)
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/*
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* 6338 register sets base address
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*/
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@@ -198,6 +256,7 @@ enum bcm63xx_regs_set {
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#define BCM_6338_PCMDMAC_BASE (0xdeadbeef)
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#define BCM_6338_PCMDMAS_BASE (0xdeadbeef)
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#define BCM_6338_RNG_BASE (0xdeadbeef)
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#define BCM_6338_MISC_BASE (0xdeadbeef)
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/*
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* 6345 register sets base address
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@@ -242,6 +301,7 @@ enum bcm63xx_regs_set {
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#define BCM_6345_PCMDMAC_BASE (0xdeadbeef)
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#define BCM_6345_PCMDMAS_BASE (0xdeadbeef)
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#define BCM_6345_RNG_BASE (0xdeadbeef)
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#define BCM_6345_MISC_BASE (0xdeadbeef)
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/*
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* 6348 register sets base address
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@@ -283,6 +343,7 @@ enum bcm63xx_regs_set {
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#define BCM_6348_PCMDMAC_BASE (0xdeadbeef)
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#define BCM_6348_PCMDMAS_BASE (0xdeadbeef)
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#define BCM_6348_RNG_BASE (0xdeadbeef)
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#define BCM_6348_MISC_BASE (0xdeadbeef)
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/*
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* 6358 register sets base address
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@@ -324,6 +385,7 @@ enum bcm63xx_regs_set {
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#define BCM_6358_PCMDMAC_BASE (0xfffe1900)
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#define BCM_6358_PCMDMAS_BASE (0xfffe1a00)
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#define BCM_6358_RNG_BASE (0xdeadbeef)
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#define BCM_6358_MISC_BASE (0xdeadbeef)
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/*
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@@ -366,6 +428,7 @@ enum bcm63xx_regs_set {
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#define BCM_6368_PCMDMAC_BASE (0xb0005a00)
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#define BCM_6368_PCMDMAS_BASE (0xb0005c00)
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#define BCM_6368_RNG_BASE (0xb0004180)
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#define BCM_6368_MISC_BASE (0xdeadbeef)
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extern const unsigned long *bcm63xx_regs_base;
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@@ -412,6 +475,7 @@ extern const unsigned long *bcm63xx_regs_base;
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__GEN_RSET_BASE(__cpu, PCMDMAC) \
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__GEN_RSET_BASE(__cpu, PCMDMAS) \
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__GEN_RSET_BASE(__cpu, RNG) \
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__GEN_RSET_BASE(__cpu, MISC) \
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}
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#define __GEN_CPU_REGS_TABLE(__cpu) \
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@@ -451,6 +515,7 @@ extern const unsigned long *bcm63xx_regs_base;
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[RSET_PCMDMAC] = BCM_## __cpu ##_PCMDMAC_BASE, \
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[RSET_PCMDMAS] = BCM_## __cpu ##_PCMDMAS_BASE, \
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[RSET_RNG] = BCM_## __cpu ##_RNG_BASE, \
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[RSET_MISC] = BCM_## __cpu ##_MISC_BASE, \
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static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
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@@ -458,6 +523,9 @@ static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
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#ifdef BCMCPU_RUNTIME_DETECT
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return bcm63xx_regs_base[set];
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#else
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#ifdef CONFIG_BCM63XX_CPU_6328
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__GEN_RSET(6328)
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#endif
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#ifdef CONFIG_BCM63XX_CPU_6338
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__GEN_RSET(6338)
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#endif
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@@ -511,6 +579,47 @@ enum bcm63xx_irq {
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IRQ_XTM_DMA0,
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};
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/*
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* 6328 irqs
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*/
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#define BCM_6328_HIGH_IRQ_BASE (IRQ_INTERNAL_BASE + 32)
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#define BCM_6328_TIMER_IRQ (IRQ_INTERNAL_BASE + 31)
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#define BCM_6328_SPI_IRQ 0
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#define BCM_6328_UART0_IRQ (IRQ_INTERNAL_BASE + 28)
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#define BCM_6328_UART1_IRQ (BCM_6328_HIGH_IRQ_BASE + 7)
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#define BCM_6328_DSL_IRQ (IRQ_INTERNAL_BASE + 4)
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#define BCM_6328_UDC0_IRQ 0
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#define BCM_6328_ENET0_IRQ 0
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#define BCM_6328_ENET1_IRQ 0
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#define BCM_6328_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12)
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#define BCM_6328_OHCI0_IRQ (IRQ_INTERNAL_BASE + 9)
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#define BCM_6328_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10)
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#define BCM_6328_PCMCIA_IRQ 0
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#define BCM_6328_ENET0_RXDMA_IRQ 0
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#define BCM_6328_ENET0_TXDMA_IRQ 0
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#define BCM_6328_ENET1_RXDMA_IRQ 0
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#define BCM_6328_ENET1_TXDMA_IRQ 0
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#define BCM_6328_PCI_IRQ (IRQ_INTERNAL_BASE + 23)
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#define BCM_6328_ATM_IRQ 0
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#define BCM_6328_ENETSW_RXDMA0_IRQ (BCM_6328_HIGH_IRQ_BASE + 0)
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#define BCM_6328_ENETSW_RXDMA1_IRQ (BCM_6328_HIGH_IRQ_BASE + 1)
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#define BCM_6328_ENETSW_RXDMA2_IRQ (BCM_6328_HIGH_IRQ_BASE + 2)
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#define BCM_6328_ENETSW_RXDMA3_IRQ (BCM_6328_HIGH_IRQ_BASE + 3)
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#define BCM_6328_ENETSW_TXDMA0_IRQ (BCM_6328_HIGH_IRQ_BASE + 4)
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#define BCM_6328_ENETSW_TXDMA1_IRQ (BCM_6328_HIGH_IRQ_BASE + 5)
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#define BCM_6328_ENETSW_TXDMA2_IRQ (BCM_6328_HIGH_IRQ_BASE + 6)
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#define BCM_6328_ENETSW_TXDMA3_IRQ (BCM_6328_HIGH_IRQ_BASE + 7)
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#define BCM_6328_XTM_IRQ (BCM_6328_HIGH_IRQ_BASE + 31)
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#define BCM_6328_XTM_DMA0_IRQ (BCM_6328_HIGH_IRQ_BASE + 11)
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#define BCM_6328_PCM_DMA0_IRQ (IRQ_INTERNAL_BASE + 2)
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#define BCM_6328_PCM_DMA1_IRQ (IRQ_INTERNAL_BASE + 3)
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#define BCM_6328_EXT_IRQ0 (IRQ_INTERNAL_BASE + 24)
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#define BCM_6328_EXT_IRQ1 (IRQ_INTERNAL_BASE + 25)
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#define BCM_6328_EXT_IRQ2 (IRQ_INTERNAL_BASE + 26)
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#define BCM_6328_EXT_IRQ3 (IRQ_INTERNAL_BASE + 27)
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/*
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* 6338 irqs
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*/
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@@ -9,6 +9,8 @@ int __init bcm63xx_gpio_init(void);
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static inline unsigned long bcm63xx_gpio_count(void)
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{
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switch (bcm63xx_get_cpu_id()) {
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case BCM6328_CPU_ID:
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return 32;
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case BCM6358_CPU_ID:
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return 40;
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case BCM6338_CPU_ID:
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@@ -91,5 +91,7 @@
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#define bcm_memc_writel(v, o) bcm_rset_writel(RSET_MEMC, (v), (o))
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#define bcm_ddr_readl(o) bcm_rset_readl(RSET_DDR, (o))
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#define bcm_ddr_writel(v, o) bcm_rset_writel(RSET_DDR, (v), (o))
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#define bcm_misc_readl(o) bcm_rset_readl(RSET_MISC, (o))
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#define bcm_misc_writel(v, o) bcm_rset_writel(RSET_MISC, (v), (o))
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#endif /* ! BCM63XX_IO_H_ */
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@@ -15,6 +15,30 @@
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/* Clock Control register */
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#define PERF_CKCTL_REG 0x4
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#define CKCTL_6328_PHYMIPS_EN (1 << 0)
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#define CKCTL_6328_ADSL_QPROC_EN (1 << 1)
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#define CKCTL_6328_ADSL_AFE_EN (1 << 2)
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#define CKCTL_6328_ADSL_EN (1 << 3)
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#define CKCTL_6328_MIPS_EN (1 << 4)
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#define CKCTL_6328_SAR_EN (1 << 5)
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#define CKCTL_6328_PCM_EN (1 << 6)
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#define CKCTL_6328_USBD_EN (1 << 7)
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#define CKCTL_6328_USBH_EN (1 << 8)
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#define CKCTL_6328_HSSPI_EN (1 << 9)
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#define CKCTL_6328_PCIE_EN (1 << 10)
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#define CKCTL_6328_ROBOSW_EN (1 << 11)
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#define CKCTL_6328_ALL_SAFE_EN (CKCTL_6328_PHYMIPS_EN | \
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CKCTL_6328_ADSL_QPROC_EN | \
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CKCTL_6328_ADSL_AFE_EN | \
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CKCTL_6328_ADSL_EN | \
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CKCTL_6328_SAR_EN | \
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CKCTL_6328_PCM_EN | \
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CKCTL_6328_USBD_EN | \
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CKCTL_6328_USBH_EN | \
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CKCTL_6328_ROBOSW_EN | \
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CKCTL_6328_PCIE_EN)
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#define CKCTL_6338_ADSLPHY_EN (1 << 0)
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#define CKCTL_6338_MPI_EN (1 << 1)
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#define CKCTL_6338_DRAM_EN (1 << 2)
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@@ -119,6 +143,7 @@
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#define SYS_PLL_SOFT_RESET 0x1
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/* Interrupt Mask register */
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#define PERF_IRQMASK_6328_REG 0x20
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#define PERF_IRQMASK_6338_REG 0xc
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#define PERF_IRQMASK_6345_REG 0xc
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#define PERF_IRQMASK_6348_REG 0xc
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@@ -126,6 +151,7 @@
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#define PERF_IRQMASK_6368_REG 0x20
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/* Interrupt Status register */
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#define PERF_IRQSTAT_6328_REG 0x28
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#define PERF_IRQSTAT_6338_REG 0x10
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#define PERF_IRQSTAT_6345_REG 0x10
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#define PERF_IRQSTAT_6348_REG 0x10
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@@ -133,6 +159,7 @@
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#define PERF_IRQSTAT_6368_REG 0x28
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/* External Interrupt Configuration register */
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#define PERF_EXTIRQ_CFG_REG_6328 0x18
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#define PERF_EXTIRQ_CFG_REG_6338 0x14
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#define PERF_EXTIRQ_CFG_REG_6348 0x14
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#define PERF_EXTIRQ_CFG_REG_6358 0x14
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@@ -162,8 +189,21 @@
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/* Soft Reset register */
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#define PERF_SOFTRESET_REG 0x28
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#define PERF_SOFTRESET_6328_REG 0x10
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#define PERF_SOFTRESET_6368_REG 0x10
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#define SOFTRESET_6328_SPI_MASK (1 << 0)
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#define SOFTRESET_6328_EPHY_MASK (1 << 1)
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#define SOFTRESET_6328_SAR_MASK (1 << 2)
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#define SOFTRESET_6328_ENETSW_MASK (1 << 3)
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#define SOFTRESET_6328_USBS_MASK (1 << 4)
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#define SOFTRESET_6328_USBH_MASK (1 << 5)
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#define SOFTRESET_6328_PCM_MASK (1 << 6)
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#define SOFTRESET_6328_PCIE_CORE_MASK (1 << 7)
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#define SOFTRESET_6328_PCIE_MASK (1 << 8)
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#define SOFTRESET_6328_PCIE_EXT_MASK (1 << 9)
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#define SOFTRESET_6328_PCIE_HARD_MASK (1 << 10)
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#define SOFTRESET_6338_SPI_MASK (1 << 0)
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#define SOFTRESET_6338_ENET_MASK (1 << 2)
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#define SOFTRESET_6338_USBH_MASK (1 << 3)
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@@ -307,6 +347,8 @@
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/* Watchdog reset length register */
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#define WDT_RSTLEN_REG 0x8
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/* Watchdog soft reset register (BCM6328 only) */
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#define WDT_SOFTRESET_REG 0xc
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/*************************************************************************
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* _REG relative to RSET_UARTx
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@@ -933,6 +975,8 @@
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* _REG relative to RSET_DDR
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*************************************************************************/
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#define DDR_CSEND_REG 0x8
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#define DDR_DMIPSPLLCFG_REG 0x18
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#define DMIPSPLLCFG_M1_SHIFT 0
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#define DMIPSPLLCFG_M1_MASK (0xff << DMIPSPLLCFG_M1_SHIFT)
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@@ -1115,4 +1159,14 @@
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#define SPI_SSOFFTIME_SHIFT 3
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#define SPI_BYTE_SWAP 0x80
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/*************************************************************************
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* _REG relative to RSET_MISC
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*************************************************************************/
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#define MISC_STRAPBUS_6328_REG 0x240
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#define STRAPBUS_6328_FCVO_SHIFT 7
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#define STRAPBUS_6328_FCVO_MASK (0x1f << STRAPBUS_6328_FCVO_SHIFT)
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#define STRAPBUS_6328_BOOT_SEL_SERIAL (1 << 28)
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#define STRAPBUS_6328_BOOT_SEL_NAND (0 << 28)
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#endif /* BCM63XX_REGS_H_ */
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@@ -18,6 +18,7 @@ static inline int is_bcm63xx_internal_registers(phys_t offset)
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if (offset >= 0xfff00000)
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return 1;
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break;
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case BCM6328_CPU_ID:
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case BCM6368_CPU_ID:
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if (offset >= 0xb0000000 && offset < 0xb1000000)
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return 1;
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