Merge tag 'mfd-for-linus-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd
Pull MFD updates from Lee Jones: "Changes to existing drivers: - Use of managed resources - omap, twl4030, ti_am335x_tscadc - Advanced error handling - omap - Rework clk management - omap - Device Tree (re-)work - tc3589x, pm8921, da9055, sec - IRC management overhaul and !BROKEN - pm8921 - Convert to regmap - ssbi, pm8921 - Use simple power-management ops - ucb1x00 - Include file clean-up - adp5520, cs5535, janz, lpc_ich, - lpc_sch, max14577, mcp-sa11x0, pcf50633-adc, rc5t583, rdc321x-southbridge, retu, smsc-ece1099, ti-ssp, ti_am335x_tscadc, tps65912, vexpress-config, wm8350, ywm8350 - Various bug fixes across the subsystem - NULL/invalid pointer dereference prevention - Resource leak mitigation, - Variable used initialised - Staticise various containers - Enforce return value checks New drivers/supported devices: - Add support for s2mps14 and s2mpa01 to sec - Add support for da9063 (v5) to da9063 - Add support for atom-c2000 to gpio-ich - Add support for come-{mbt10,cbt6,chl6} to kempld - Add support for da9053 to da9052 - Add support for itco-wdt (v3) and baytrail to lpc_ich - Add new drivers for tps65218, rtsx_usb, bcm590xx (Re-)moved drivers: - twl4030 ==> drivers/iio - ti-ssp ==> /dev/null" * tag 'mfd-for-linus-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd: (103 commits) mfd: wm5110: Correct default for HEADPHONE_DETECT_1 mfd: arizona: Correct small errors in the DT binding documentation mfd: arizona: Mark DSP clocking register as volatile mfd: devicetree: bindings: Add pm8xxx RTC description mfd: kempld-core: Fix potential hang-up during boot mfd: sec-core: Fix uninitialized 'regmap_rtc' on S2MPA01 mfd: tps65910: Fix regmap_irq_chip_data leak on mfd_add_devices fail mfd: tps65910: Fix possible invalid pointer dereference on regmap_add_irq_chip fail mfd: sec-core: Fix I2C dummy device resource leak on probe failure mfd: sec-core: Add of_compatible strings for clock MFD cells mfd: Remove obsolete ti-ssp driver Documentation: mfd: s2mps11: Describe S5M8767 and S2MPS14 clocks mfd: bcm590xx: Fix type argument for module device table mfd: lpc_ich: Add support for Intel Bay Trail SoC mfd: lpc_ich: Add support for NM10 GPIO mfd: lpc_ich: Change Avoton to iTCO v3 watchdog: iTCO_wdt: Add support for v3 silicon mfd: lpc_ich: Add support for iTCO v3 mfd: lpc_ich: Remove lpc_ich_cfg struct use mfd: lpc_ich: Only configure watchdog or GPIO when present ...
This commit is contained in:
@@ -1034,6 +1034,27 @@
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#define ARIZONA_DSP1_STATUS_1 0x1104
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#define ARIZONA_DSP1_STATUS_2 0x1105
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#define ARIZONA_DSP1_STATUS_3 0x1106
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#define ARIZONA_DSP1_STATUS_4 0x1107
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#define ARIZONA_DSP1_WDMA_BUFFER_1 0x1110
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#define ARIZONA_DSP1_WDMA_BUFFER_2 0x1111
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#define ARIZONA_DSP1_WDMA_BUFFER_3 0x1112
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#define ARIZONA_DSP1_WDMA_BUFFER_4 0x1113
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#define ARIZONA_DSP1_WDMA_BUFFER_5 0x1114
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#define ARIZONA_DSP1_WDMA_BUFFER_6 0x1115
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#define ARIZONA_DSP1_WDMA_BUFFER_7 0x1116
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#define ARIZONA_DSP1_WDMA_BUFFER_8 0x1117
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#define ARIZONA_DSP1_RDMA_BUFFER_1 0x1120
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#define ARIZONA_DSP1_RDMA_BUFFER_2 0x1121
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#define ARIZONA_DSP1_RDMA_BUFFER_3 0x1122
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#define ARIZONA_DSP1_RDMA_BUFFER_4 0x1123
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#define ARIZONA_DSP1_RDMA_BUFFER_5 0x1124
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#define ARIZONA_DSP1_RDMA_BUFFER_6 0x1125
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#define ARIZONA_DSP1_WDMA_CONFIG_1 0x1130
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#define ARIZONA_DSP1_WDMA_CONFIG_2 0x1131
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#define ARIZONA_DSP1_WDMA_OFFSET_1 0x1132
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#define ARIZONA_DSP1_RDMA_CONFIG_1 0x1134
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#define ARIZONA_DSP1_RDMA_OFFSET_1 0x1135
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#define ARIZONA_DSP1_EXTERNAL_START_SELECT_1 0x1138
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#define ARIZONA_DSP1_SCRATCH_0 0x1140
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#define ARIZONA_DSP1_SCRATCH_1 0x1141
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#define ARIZONA_DSP1_SCRATCH_2 0x1142
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@@ -1043,6 +1064,27 @@
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#define ARIZONA_DSP2_STATUS_1 0x1204
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#define ARIZONA_DSP2_STATUS_2 0x1205
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#define ARIZONA_DSP2_STATUS_3 0x1206
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#define ARIZONA_DSP2_STATUS_4 0x1207
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#define ARIZONA_DSP2_WDMA_BUFFER_1 0x1210
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#define ARIZONA_DSP2_WDMA_BUFFER_2 0x1211
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#define ARIZONA_DSP2_WDMA_BUFFER_3 0x1212
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#define ARIZONA_DSP2_WDMA_BUFFER_4 0x1213
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#define ARIZONA_DSP2_WDMA_BUFFER_5 0x1214
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#define ARIZONA_DSP2_WDMA_BUFFER_6 0x1215
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#define ARIZONA_DSP2_WDMA_BUFFER_7 0x1216
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#define ARIZONA_DSP2_WDMA_BUFFER_8 0x1217
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#define ARIZONA_DSP2_RDMA_BUFFER_1 0x1220
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#define ARIZONA_DSP2_RDMA_BUFFER_2 0x1221
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#define ARIZONA_DSP2_RDMA_BUFFER_3 0x1222
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#define ARIZONA_DSP2_RDMA_BUFFER_4 0x1223
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#define ARIZONA_DSP2_RDMA_BUFFER_5 0x1224
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#define ARIZONA_DSP2_RDMA_BUFFER_6 0x1225
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#define ARIZONA_DSP2_WDMA_CONFIG_1 0x1230
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#define ARIZONA_DSP2_WDMA_CONFIG_2 0x1231
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#define ARIZONA_DSP2_WDMA_OFFSET_1 0x1232
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#define ARIZONA_DSP2_RDMA_CONFIG_1 0x1234
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#define ARIZONA_DSP2_RDMA_OFFSET_1 0x1235
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#define ARIZONA_DSP2_EXTERNAL_START_SELECT_1 0x1238
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#define ARIZONA_DSP2_SCRATCH_0 0x1240
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#define ARIZONA_DSP2_SCRATCH_1 0x1241
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#define ARIZONA_DSP2_SCRATCH_2 0x1242
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@@ -1052,6 +1094,27 @@
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#define ARIZONA_DSP3_STATUS_1 0x1304
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#define ARIZONA_DSP3_STATUS_2 0x1305
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#define ARIZONA_DSP3_STATUS_3 0x1306
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#define ARIZONA_DSP3_STATUS_4 0x1307
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#define ARIZONA_DSP3_WDMA_BUFFER_1 0x1310
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#define ARIZONA_DSP3_WDMA_BUFFER_2 0x1311
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#define ARIZONA_DSP3_WDMA_BUFFER_3 0x1312
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#define ARIZONA_DSP3_WDMA_BUFFER_4 0x1313
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#define ARIZONA_DSP3_WDMA_BUFFER_5 0x1314
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#define ARIZONA_DSP3_WDMA_BUFFER_6 0x1315
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#define ARIZONA_DSP3_WDMA_BUFFER_7 0x1316
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#define ARIZONA_DSP3_WDMA_BUFFER_8 0x1317
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#define ARIZONA_DSP3_RDMA_BUFFER_1 0x1320
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#define ARIZONA_DSP3_RDMA_BUFFER_2 0x1321
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#define ARIZONA_DSP3_RDMA_BUFFER_3 0x1322
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#define ARIZONA_DSP3_RDMA_BUFFER_4 0x1323
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#define ARIZONA_DSP3_RDMA_BUFFER_5 0x1324
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#define ARIZONA_DSP3_RDMA_BUFFER_6 0x1325
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#define ARIZONA_DSP3_WDMA_CONFIG_1 0x1330
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#define ARIZONA_DSP3_WDMA_CONFIG_2 0x1331
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#define ARIZONA_DSP3_WDMA_OFFSET_1 0x1332
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#define ARIZONA_DSP3_RDMA_CONFIG_1 0x1334
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#define ARIZONA_DSP3_RDMA_OFFSET_1 0x1335
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#define ARIZONA_DSP3_EXTERNAL_START_SELECT_1 0x1338
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#define ARIZONA_DSP3_SCRATCH_0 0x1340
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#define ARIZONA_DSP3_SCRATCH_1 0x1341
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#define ARIZONA_DSP3_SCRATCH_2 0x1342
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@@ -1061,6 +1124,27 @@
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#define ARIZONA_DSP4_STATUS_1 0x1404
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#define ARIZONA_DSP4_STATUS_2 0x1405
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#define ARIZONA_DSP4_STATUS_3 0x1406
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#define ARIZONA_DSP4_STATUS_4 0x1407
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#define ARIZONA_DSP4_WDMA_BUFFER_1 0x1410
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#define ARIZONA_DSP4_WDMA_BUFFER_2 0x1411
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#define ARIZONA_DSP4_WDMA_BUFFER_3 0x1412
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#define ARIZONA_DSP4_WDMA_BUFFER_4 0x1413
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#define ARIZONA_DSP4_WDMA_BUFFER_5 0x1414
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#define ARIZONA_DSP4_WDMA_BUFFER_6 0x1415
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#define ARIZONA_DSP4_WDMA_BUFFER_7 0x1416
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#define ARIZONA_DSP4_WDMA_BUFFER_8 0x1417
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#define ARIZONA_DSP4_RDMA_BUFFER_1 0x1420
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#define ARIZONA_DSP4_RDMA_BUFFER_2 0x1421
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#define ARIZONA_DSP4_RDMA_BUFFER_3 0x1422
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#define ARIZONA_DSP4_RDMA_BUFFER_4 0x1423
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#define ARIZONA_DSP4_RDMA_BUFFER_5 0x1424
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#define ARIZONA_DSP4_RDMA_BUFFER_6 0x1425
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#define ARIZONA_DSP4_WDMA_CONFIG_1 0x1430
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#define ARIZONA_DSP4_WDMA_CONFIG_2 0x1431
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#define ARIZONA_DSP4_WDMA_OFFSET_1 0x1432
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#define ARIZONA_DSP4_RDMA_CONFIG_1 0x1434
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#define ARIZONA_DSP4_RDMA_OFFSET_1 0x1435
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#define ARIZONA_DSP4_EXTERNAL_START_SELECT_1 0x1438
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#define ARIZONA_DSP4_SCRATCH_0 0x1440
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#define ARIZONA_DSP4_SCRATCH_1 0x1441
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#define ARIZONA_DSP4_SCRATCH_2 0x1442
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31
include/linux/mfd/bcm590xx.h
Normal file
31
include/linux/mfd/bcm590xx.h
Normal file
@@ -0,0 +1,31 @@
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/*
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* Broadcom BCM590xx PMU
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*
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* Copyright 2014 Linaro Limited
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* Author: Matt Porter <mporter@linaro.org>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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*/
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#ifndef __LINUX_MFD_BCM590XX_H
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#define __LINUX_MFD_BCM590XX_H
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#include <linux/device.h>
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#include <linux/i2c.h>
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#include <linux/regmap.h>
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/* max register address */
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#define BCM590XX_MAX_REGISTER 0xe7
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struct bcm590xx {
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struct device *dev;
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struct i2c_client *i2c_client;
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struct regmap *regmap;
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unsigned int id;
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};
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#endif /* __LINUX_MFD_BCM590XX_H */
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@@ -83,6 +83,7 @@ enum da9052_chip_id {
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DA9053_AA,
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DA9053_BA,
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DA9053_BB,
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DA9053_BC,
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};
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struct da9052_pdata;
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@@ -33,6 +33,10 @@ enum da9063_models {
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PMIC_DA9063 = 0x61,
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};
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enum da9063_variant_codes {
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PMIC_DA9063_BB = 0x5
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};
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/* Interrupts */
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enum da9063_irqs {
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DA9063_IRQ_ONKEY = 0,
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@@ -72,7 +76,7 @@ struct da9063 {
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/* Device */
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struct device *dev;
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unsigned short model;
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unsigned short revision;
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unsigned char variant_code;
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unsigned int flags;
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/* Control interface */
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@@ -17,11 +17,7 @@
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#define _DA9063_REG_H
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#define DA9063_I2C_PAGE_SEL_SHIFT 1
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#define DA9063_EVENT_REG_NUM 4
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#define DA9210_EVENT_REG_NUM 2
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#define DA9063_EXT_EVENT_REG_NUM (DA9063_EVENT_REG_NUM + \
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DA9210_EVENT_REG_NUM)
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/* Page selection I2C or SPI always in the begining of any page. */
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/* Page 0 : I2C access 0x000 - 0x0FF SPI access 0x000 - 0x07F */
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@@ -61,9 +57,9 @@
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#define DA9063_REG_GPIO_10_11 0x1A
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#define DA9063_REG_GPIO_12_13 0x1B
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#define DA9063_REG_GPIO_14_15 0x1C
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#define DA9063_REG_GPIO_MODE_0_7 0x1D
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#define DA9063_REG_GPIO_MODE_8_15 0x1E
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#define DA9063_REG_GPIO_SWITCH_CONT 0x1F
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#define DA9063_REG_GPIO_MODE0_7 0x1D
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#define DA9063_REG_GPIO_MODE8_15 0x1E
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#define DA9063_REG_SWITCH_CONT 0x1F
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/* Regulator Control Registers */
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#define DA9063_REG_BCORE2_CONT 0x20
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@@ -83,7 +79,7 @@
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#define DA9063_REG_LDO9_CONT 0x2E
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#define DA9063_REG_LDO10_CONT 0x2F
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#define DA9063_REG_LDO11_CONT 0x30
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#define DA9063_REG_VIB 0x31
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#define DA9063_REG_SUPPLIES 0x31
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#define DA9063_REG_DVC_1 0x32
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#define DA9063_REG_DVC_2 0x33
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@@ -97,9 +93,9 @@
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#define DA9063_REG_ADCIN1_RES 0x3A
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#define DA9063_REG_ADCIN2_RES 0x3B
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#define DA9063_REG_ADCIN3_RES 0x3C
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#define DA9063_REG_MON1_RES 0x3D
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#define DA9063_REG_MON2_RES 0x3E
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#define DA9063_REG_MON3_RES 0x3F
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#define DA9063_REG_MON_A8_RES 0x3D
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#define DA9063_REG_MON_A9_RES 0x3E
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#define DA9063_REG_MON_A10_RES 0x3F
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/* RTC Calendar and Alarm Registers */
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#define DA9063_REG_COUNT_S 0x40
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@@ -108,15 +104,16 @@
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#define DA9063_REG_COUNT_D 0x43
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#define DA9063_REG_COUNT_MO 0x44
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#define DA9063_REG_COUNT_Y 0x45
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#define DA9063_REG_ALARM_MI 0x46
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#define DA9063_REG_ALARM_H 0x47
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#define DA9063_REG_ALARM_D 0x48
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#define DA9063_REG_ALARM_MO 0x49
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#define DA9063_REG_ALARM_Y 0x4A
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#define DA9063_REG_SECOND_A 0x4B
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#define DA9063_REG_SECOND_B 0x4C
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#define DA9063_REG_SECOND_C 0x4D
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#define DA9063_REG_SECOND_D 0x4E
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#define DA9063_REG_ALARM_S 0x46
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#define DA9063_REG_ALARM_MI 0x47
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#define DA9063_REG_ALARM_H 0x48
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#define DA9063_REG_ALARM_D 0x49
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#define DA9063_REG_ALARM_MO 0x4A
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#define DA9063_REG_ALARM_Y 0x4B
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#define DA9063_REG_SECOND_A 0x4C
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#define DA9063_REG_SECOND_B 0x4D
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#define DA9063_REG_SECOND_C 0x4E
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#define DA9063_REG_SECOND_D 0x4F
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/* Sequencer Control Registers */
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#define DA9063_REG_SEQ 0x81
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@@ -226,35 +223,37 @@
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#define DA9063_REG_CONFIG_J 0x10F
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#define DA9063_REG_CONFIG_K 0x110
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#define DA9063_REG_CONFIG_L 0x111
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#define DA9063_REG_MON_REG_1 0x112
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#define DA9063_REG_MON_REG_2 0x113
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#define DA9063_REG_MON_REG_3 0x114
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#define DA9063_REG_MON_REG_4 0x115
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#define DA9063_REG_MON_REG_5 0x116
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#define DA9063_REG_MON_REG_6 0x117
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#define DA9063_REG_TRIM_CLDR 0x118
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#define DA9063_REG_CONFIG_M 0x112
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#define DA9063_REG_CONFIG_N 0x113
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#define DA9063_REG_MON_REG_1 0x114
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#define DA9063_REG_MON_REG_2 0x115
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#define DA9063_REG_MON_REG_3 0x116
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#define DA9063_REG_MON_REG_4 0x117
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#define DA9063_REG_MON_REG_5 0x11E
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#define DA9063_REG_MON_REG_6 0x11F
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#define DA9063_REG_TRIM_CLDR 0x120
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/* General Purpose Registers */
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#define DA9063_REG_GP_ID_0 0x119
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#define DA9063_REG_GP_ID_1 0x11A
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#define DA9063_REG_GP_ID_2 0x11B
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#define DA9063_REG_GP_ID_3 0x11C
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#define DA9063_REG_GP_ID_4 0x11D
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#define DA9063_REG_GP_ID_5 0x11E
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#define DA9063_REG_GP_ID_6 0x11F
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#define DA9063_REG_GP_ID_7 0x120
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#define DA9063_REG_GP_ID_8 0x121
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#define DA9063_REG_GP_ID_9 0x122
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#define DA9063_REG_GP_ID_10 0x123
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#define DA9063_REG_GP_ID_11 0x124
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#define DA9063_REG_GP_ID_12 0x125
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#define DA9063_REG_GP_ID_13 0x126
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#define DA9063_REG_GP_ID_14 0x127
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#define DA9063_REG_GP_ID_15 0x128
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#define DA9063_REG_GP_ID_16 0x129
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#define DA9063_REG_GP_ID_17 0x12A
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#define DA9063_REG_GP_ID_18 0x12B
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#define DA9063_REG_GP_ID_19 0x12C
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#define DA9063_REG_GP_ID_0 0x121
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#define DA9063_REG_GP_ID_1 0x122
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#define DA9063_REG_GP_ID_2 0x123
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#define DA9063_REG_GP_ID_3 0x124
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#define DA9063_REG_GP_ID_4 0x125
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#define DA9063_REG_GP_ID_5 0x126
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||||
#define DA9063_REG_GP_ID_6 0x127
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||||
#define DA9063_REG_GP_ID_7 0x128
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||||
#define DA9063_REG_GP_ID_8 0x129
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||||
#define DA9063_REG_GP_ID_9 0x12A
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||||
#define DA9063_REG_GP_ID_10 0x12B
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||||
#define DA9063_REG_GP_ID_11 0x12C
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#define DA9063_REG_GP_ID_12 0x12D
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||||
#define DA9063_REG_GP_ID_13 0x12E
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||||
#define DA9063_REG_GP_ID_14 0x12F
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#define DA9063_REG_GP_ID_15 0x130
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||||
#define DA9063_REG_GP_ID_16 0x131
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||||
#define DA9063_REG_GP_ID_17 0x132
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#define DA9063_REG_GP_ID_18 0x133
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||||
#define DA9063_REG_GP_ID_19 0x134
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||||
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||||
/* Chip ID and variant */
|
||||
#define DA9063_REG_CHIP_ID 0x181
|
||||
@@ -405,8 +404,10 @@
|
||||
/* DA9063_REG_CONTROL_B (addr=0x0F) */
|
||||
#define DA9063_CHG_SEL 0x01
|
||||
#define DA9063_WATCHDOG_PD 0x02
|
||||
#define DA9063_RESET_BLINKING 0x04
|
||||
#define DA9063_NRES_MODE 0x08
|
||||
#define DA9063_NONKEY_LOCK 0x10
|
||||
#define DA9063_BUCK_SLOWSTART 0x80
|
||||
|
||||
/* DA9063_REG_CONTROL_C (addr=0x10) */
|
||||
#define DA9063_DEBOUNCING_MASK 0x07
|
||||
@@ -466,6 +467,7 @@
|
||||
#define DA9063_GPADC_PAUSE 0x02
|
||||
#define DA9063_PMIF_DIS 0x04
|
||||
#define DA9063_HS2WIRE_DIS 0x08
|
||||
#define DA9063_CLDR_PAUSE 0x10
|
||||
#define DA9063_BBAT_DIS 0x20
|
||||
#define DA9063_OUT_32K_PAUSE 0x40
|
||||
#define DA9063_PMCONT_DIS 0x80
|
||||
@@ -660,7 +662,7 @@
|
||||
#define DA9063_GPIO15_TYPE_GPO 0x04
|
||||
#define DA9063_GPIO15_NO_WAKEUP 0x80
|
||||
|
||||
/* DA9063_REG_GPIO_MODE_0_7 (addr=0x1D) */
|
||||
/* DA9063_REG_GPIO_MODE0_7 (addr=0x1D) */
|
||||
#define DA9063_GPIO0_MODE 0x01
|
||||
#define DA9063_GPIO1_MODE 0x02
|
||||
#define DA9063_GPIO2_MODE 0x04
|
||||
@@ -670,7 +672,7 @@
|
||||
#define DA9063_GPIO6_MODE 0x40
|
||||
#define DA9063_GPIO7_MODE 0x80
|
||||
|
||||
/* DA9063_REG_GPIO_MODE_8_15 (addr=0x1E) */
|
||||
/* DA9063_REG_GPIO_MODE8_15 (addr=0x1E) */
|
||||
#define DA9063_GPIO8_MODE 0x01
|
||||
#define DA9063_GPIO9_MODE 0x02
|
||||
#define DA9063_GPIO10_MODE 0x04
|
||||
@@ -702,12 +704,12 @@
|
||||
#define DA9063_SWITCH_SR_5MV 0x10
|
||||
#define DA9063_SWITCH_SR_10MV 0x20
|
||||
#define DA9063_SWITCH_SR_50MV 0x30
|
||||
#define DA9063_SWITCH_SR_DIS 0x40
|
||||
#define DA9063_CORE_SW_INTERNAL 0x40
|
||||
#define DA9063_CP_EN_MODE 0x80
|
||||
|
||||
/* DA9063_REGL_Bxxxx_CONT common bits (addr=0x20-0x25) */
|
||||
#define DA9063_BUCK_EN 0x01
|
||||
#define DA9063_BUCK_GPI_MASK 0x06
|
||||
#define DA9063_BUCK_GPI_MASK 0x06
|
||||
#define DA9063_BUCK_GPI_OFF 0x00
|
||||
#define DA9063_BUCK_GPI_GPIO1 0x02
|
||||
#define DA9063_BUCK_GPI_GPIO2 0x04
|
||||
@@ -841,25 +843,27 @@
|
||||
#define DA9063_COUNT_YEAR_MASK 0x3F
|
||||
#define DA9063_MONITOR 0x40
|
||||
|
||||
/* DA9063_REG_ALARM_MI (addr=0x46) */
|
||||
/* DA9063_REG_ALARM_S (addr=0x46) */
|
||||
#define DA9063_ALARM_S_MASK 0x3F
|
||||
#define DA9063_ALARM_STATUS_ALARM 0x80
|
||||
#define DA9063_ALARM_STATUS_TICK 0x40
|
||||
/* DA9063_REG_ALARM_MI (addr=0x47) */
|
||||
#define DA9063_ALARM_MIN_MASK 0x3F
|
||||
|
||||
/* DA9063_REG_ALARM_H (addr=0x47) */
|
||||
/* DA9063_REG_ALARM_H (addr=0x48) */
|
||||
#define DA9063_ALARM_HOUR_MASK 0x1F
|
||||
|
||||
/* DA9063_REG_ALARM_D (addr=0x48) */
|
||||
/* DA9063_REG_ALARM_D (addr=0x49) */
|
||||
#define DA9063_ALARM_DAY_MASK 0x1F
|
||||
|
||||
/* DA9063_REG_ALARM_MO (addr=0x49) */
|
||||
/* DA9063_REG_ALARM_MO (addr=0x4A) */
|
||||
#define DA9063_TICK_WAKE 0x20
|
||||
#define DA9063_TICK_TYPE 0x10
|
||||
#define DA9063_TICK_TYPE_SEC 0x00
|
||||
#define DA9063_TICK_TYPE_MIN 0x10
|
||||
#define DA9063_ALARM_MONTH_MASK 0x0F
|
||||
|
||||
/* DA9063_REG_ALARM_Y (addr=0x4A) */
|
||||
/* DA9063_REG_ALARM_Y (addr=0x4B) */
|
||||
#define DA9063_TICK_ON 0x80
|
||||
#define DA9063_ALARM_ON 0x40
|
||||
#define DA9063_ALARM_YEAR_MASK 0x3F
|
||||
@@ -906,7 +910,7 @@
|
||||
|
||||
/* DA9063_REG_Bxxxx_CFG common bits (addr=0x9D-0xA2) */
|
||||
#define DA9063_BUCK_FB_MASK 0x07
|
||||
#define DA9063_BUCK_PD_DIS_SHIFT 5
|
||||
#define DA9063_BUCK_PD_DIS_MASK 0x20
|
||||
#define DA9063_BUCK_MODE_MASK 0xC0
|
||||
#define DA9063_BUCK_MODE_MANUAL 0x00
|
||||
#define DA9063_BUCK_MODE_SLEEP 0x40
|
||||
|
@@ -21,23 +21,26 @@
|
||||
#define LPC_ICH_H
|
||||
|
||||
/* Watchdog resources */
|
||||
#define ICH_RES_IO_TCO 0
|
||||
#define ICH_RES_IO_SMI 1
|
||||
#define ICH_RES_MEM_OFF 2
|
||||
#define ICH_RES_MEM_GCS 0
|
||||
#define ICH_RES_IO_TCO 0
|
||||
#define ICH_RES_IO_SMI 1
|
||||
#define ICH_RES_MEM_OFF 2
|
||||
#define ICH_RES_MEM_GCS_PMC 0
|
||||
|
||||
/* GPIO resources */
|
||||
#define ICH_RES_GPIO 0
|
||||
#define ICH_RES_GPE0 1
|
||||
|
||||
/* GPIO compatibility */
|
||||
#define ICH_I3100_GPIO 0x401
|
||||
#define ICH_V5_GPIO 0x501
|
||||
#define ICH_V6_GPIO 0x601
|
||||
#define ICH_V7_GPIO 0x701
|
||||
#define ICH_V9_GPIO 0x801
|
||||
#define ICH_V10CORP_GPIO 0xa01
|
||||
#define ICH_V10CONS_GPIO 0xa11
|
||||
enum {
|
||||
ICH_I3100_GPIO,
|
||||
ICH_V5_GPIO,
|
||||
ICH_V6_GPIO,
|
||||
ICH_V7_GPIO,
|
||||
ICH_V9_GPIO,
|
||||
ICH_V10CORP_GPIO,
|
||||
ICH_V10CONS_GPIO,
|
||||
AVOTON_GPIO,
|
||||
};
|
||||
|
||||
struct lpc_ich_info {
|
||||
char name[32];
|
||||
|
@@ -248,14 +248,6 @@ enum max14577_charger_reg {
|
||||
/* MAX14577 regulator SFOUT LDO voltage, fixed, uV */
|
||||
#define MAX14577_REGULATOR_SAFEOUT_VOLTAGE 4900000
|
||||
|
||||
enum max14577_irq_source {
|
||||
MAX14577_IRQ_INT1 = 0,
|
||||
MAX14577_IRQ_INT2,
|
||||
MAX14577_IRQ_INT3,
|
||||
|
||||
MAX14577_IRQ_REGS_NUM,
|
||||
};
|
||||
|
||||
enum max14577_irq {
|
||||
/* INT1 */
|
||||
MAX14577_IRQ_INT1_ADC,
|
||||
|
@@ -25,13 +25,8 @@
|
||||
#ifndef __MAX14577_H__
|
||||
#define __MAX14577_H__
|
||||
|
||||
#include <linux/mfd/max14577-private.h>
|
||||
#include <linux/regulator/consumer.h>
|
||||
|
||||
/*
|
||||
* MAX14577 Regulator
|
||||
*/
|
||||
|
||||
/* MAX14577 regulator IDs */
|
||||
enum max14577_regulators {
|
||||
MAX14577_SAFEOUT = 0,
|
||||
|
@@ -1,59 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
/*
|
||||
* Qualcomm PMIC irq 8xxx driver header file
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MFD_PM8XXX_IRQ_H
|
||||
#define __MFD_PM8XXX_IRQ_H
|
||||
|
||||
#include <linux/errno.h>
|
||||
#include <linux/err.h>
|
||||
|
||||
struct pm8xxx_irq_core_data {
|
||||
u32 rev;
|
||||
int nirqs;
|
||||
};
|
||||
|
||||
struct pm8xxx_irq_platform_data {
|
||||
int irq_base;
|
||||
struct pm8xxx_irq_core_data irq_cdata;
|
||||
int devirq;
|
||||
int irq_trigger_flag;
|
||||
};
|
||||
|
||||
struct pm_irq_chip;
|
||||
|
||||
#ifdef CONFIG_MFD_PM8XXX_IRQ
|
||||
int pm8xxx_get_irq_stat(struct pm_irq_chip *chip, int irq);
|
||||
struct pm_irq_chip *pm8xxx_irq_init(struct device *dev,
|
||||
const struct pm8xxx_irq_platform_data *pdata);
|
||||
int pm8xxx_irq_exit(struct pm_irq_chip *chip);
|
||||
#else
|
||||
static inline int pm8xxx_get_irq_stat(struct pm_irq_chip *chip, int irq)
|
||||
{
|
||||
return -ENXIO;
|
||||
}
|
||||
static inline struct pm_irq_chip *pm8xxx_irq_init(
|
||||
const struct device *dev,
|
||||
const struct pm8xxx_irq_platform_data *pdata)
|
||||
{
|
||||
return ERR_PTR(-ENXIO);
|
||||
}
|
||||
static inline int pm8xxx_irq_exit(struct pm_irq_chip *chip)
|
||||
{
|
||||
return -ENXIO;
|
||||
}
|
||||
#endif /* CONFIG_MFD_PM8XXX_IRQ */
|
||||
#endif /* __MFD_PM8XXX_IRQ_H */
|
@@ -1,30 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
/*
|
||||
* Qualcomm PMIC 8921 driver header file
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MFD_PM8921_H
|
||||
#define __MFD_PM8921_H
|
||||
|
||||
#include <linux/mfd/pm8xxx/irq.h>
|
||||
|
||||
#define PM8921_NR_IRQS 256
|
||||
|
||||
struct pm8921_platform_data {
|
||||
int irq_base;
|
||||
struct pm8xxx_irq_platform_data *irq_pdata;
|
||||
};
|
||||
|
||||
#endif
|
628
include/linux/mfd/rtsx_usb.h
Normal file
628
include/linux/mfd/rtsx_usb.h
Normal file
@@ -0,0 +1,628 @@
|
||||
/* Driver for Realtek RTS5139 USB card reader
|
||||
*
|
||||
* Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2
|
||||
* as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
* Author:
|
||||
* Roger Tseng <rogerable@realtek.com>
|
||||
*/
|
||||
|
||||
#ifndef __RTSX_USB_H
|
||||
#define __RTSX_USB_H
|
||||
|
||||
#include <linux/usb.h>
|
||||
|
||||
/* related module names */
|
||||
#define RTSX_USB_SD_CARD 0
|
||||
#define RTSX_USB_MS_CARD 1
|
||||
|
||||
/* endpoint numbers */
|
||||
#define EP_BULK_OUT 1
|
||||
#define EP_BULK_IN 2
|
||||
#define EP_INTR_IN 3
|
||||
|
||||
/* USB vendor requests */
|
||||
#define RTSX_USB_REQ_REG_OP 0x00
|
||||
#define RTSX_USB_REQ_POLL 0x02
|
||||
|
||||
/* miscellaneous parameters */
|
||||
#define MIN_DIV_N 60
|
||||
#define MAX_DIV_N 120
|
||||
|
||||
#define MAX_PHASE 15
|
||||
#define RX_TUNING_CNT 3
|
||||
|
||||
#define QFN24 0
|
||||
#define LQFP48 1
|
||||
#define CHECK_PKG(ucr, pkg) ((ucr)->package == (pkg))
|
||||
|
||||
/* data structures */
|
||||
struct rtsx_ucr {
|
||||
u16 vendor_id;
|
||||
u16 product_id;
|
||||
|
||||
int package;
|
||||
u8 ic_version;
|
||||
bool is_rts5179;
|
||||
|
||||
unsigned int cur_clk;
|
||||
|
||||
u8 *cmd_buf;
|
||||
unsigned int cmd_idx;
|
||||
u8 *rsp_buf;
|
||||
|
||||
struct usb_device *pusb_dev;
|
||||
struct usb_interface *pusb_intf;
|
||||
struct usb_sg_request current_sg;
|
||||
unsigned char *iobuf;
|
||||
dma_addr_t iobuf_dma;
|
||||
|
||||
struct timer_list sg_timer;
|
||||
struct mutex dev_mutex;
|
||||
};
|
||||
|
||||
/* buffer size */
|
||||
#define IOBUF_SIZE 1024
|
||||
|
||||
/* prototypes of exported functions */
|
||||
extern int rtsx_usb_get_card_status(struct rtsx_ucr *ucr, u16 *status);
|
||||
|
||||
extern int rtsx_usb_read_register(struct rtsx_ucr *ucr, u16 addr, u8 *data);
|
||||
extern int rtsx_usb_write_register(struct rtsx_ucr *ucr, u16 addr, u8 mask,
|
||||
u8 data);
|
||||
|
||||
extern int rtsx_usb_ep0_write_register(struct rtsx_ucr *ucr, u16 addr, u8 mask,
|
||||
u8 data);
|
||||
extern int rtsx_usb_ep0_read_register(struct rtsx_ucr *ucr, u16 addr,
|
||||
u8 *data);
|
||||
|
||||
extern void rtsx_usb_add_cmd(struct rtsx_ucr *ucr, u8 cmd_type,
|
||||
u16 reg_addr, u8 mask, u8 data);
|
||||
extern int rtsx_usb_send_cmd(struct rtsx_ucr *ucr, u8 flag, int timeout);
|
||||
extern int rtsx_usb_get_rsp(struct rtsx_ucr *ucr, int rsp_len, int timeout);
|
||||
extern int rtsx_usb_transfer_data(struct rtsx_ucr *ucr, unsigned int pipe,
|
||||
void *buf, unsigned int len, int use_sg,
|
||||
unsigned int *act_len, int timeout);
|
||||
|
||||
extern int rtsx_usb_read_ppbuf(struct rtsx_ucr *ucr, u8 *buf, int buf_len);
|
||||
extern int rtsx_usb_write_ppbuf(struct rtsx_ucr *ucr, u8 *buf, int buf_len);
|
||||
extern int rtsx_usb_switch_clock(struct rtsx_ucr *ucr, unsigned int card_clock,
|
||||
u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk);
|
||||
extern int rtsx_usb_card_exclusive_check(struct rtsx_ucr *ucr, int card);
|
||||
|
||||
/* card status */
|
||||
#define SD_CD 0x01
|
||||
#define MS_CD 0x02
|
||||
#define XD_CD 0x04
|
||||
#define CD_MASK (SD_CD | MS_CD | XD_CD)
|
||||
#define SD_WP 0x08
|
||||
|
||||
/* reader command field offset & parameters */
|
||||
#define READ_REG_CMD 0
|
||||
#define WRITE_REG_CMD 1
|
||||
#define CHECK_REG_CMD 2
|
||||
|
||||
#define PACKET_TYPE 4
|
||||
#define CNT_H 5
|
||||
#define CNT_L 6
|
||||
#define STAGE_FLAG 7
|
||||
#define CMD_OFFSET 8
|
||||
#define SEQ_WRITE_DATA_OFFSET 12
|
||||
|
||||
#define BATCH_CMD 0
|
||||
#define SEQ_READ 1
|
||||
#define SEQ_WRITE 2
|
||||
|
||||
#define STAGE_R 0x01
|
||||
#define STAGE_DI 0x02
|
||||
#define STAGE_DO 0x04
|
||||
#define STAGE_MS_STATUS 0x08
|
||||
#define STAGE_XD_STATUS 0x10
|
||||
#define MODE_C 0x00
|
||||
#define MODE_CR (STAGE_R)
|
||||
#define MODE_CDIR (STAGE_R | STAGE_DI)
|
||||
#define MODE_CDOR (STAGE_R | STAGE_DO)
|
||||
|
||||
#define EP0_OP_SHIFT 14
|
||||
#define EP0_READ_REG_CMD 2
|
||||
#define EP0_WRITE_REG_CMD 3
|
||||
|
||||
#define rtsx_usb_cmd_hdr_tag(ucr) \
|
||||
do { \
|
||||
ucr->cmd_buf[0] = 'R'; \
|
||||
ucr->cmd_buf[1] = 'T'; \
|
||||
ucr->cmd_buf[2] = 'C'; \
|
||||
ucr->cmd_buf[3] = 'R'; \
|
||||
} while (0)
|
||||
|
||||
static inline void rtsx_usb_init_cmd(struct rtsx_ucr *ucr)
|
||||
{
|
||||
rtsx_usb_cmd_hdr_tag(ucr);
|
||||
ucr->cmd_idx = 0;
|
||||
ucr->cmd_buf[PACKET_TYPE] = BATCH_CMD;
|
||||
}
|
||||
|
||||
/* internal register address */
|
||||
#define FPDCTL 0xFC00
|
||||
#define SSC_DIV_N_0 0xFC07
|
||||
#define SSC_CTL1 0xFC09
|
||||
#define SSC_CTL2 0xFC0A
|
||||
#define CFG_MODE 0xFC0E
|
||||
#define CFG_MODE_1 0xFC0F
|
||||
#define RCCTL 0xFC14
|
||||
#define SOF_WDOG 0xFC28
|
||||
#define SYS_DUMMY0 0xFC30
|
||||
|
||||
#define MS_BLKEND 0xFD30
|
||||
#define MS_READ_START 0xFD31
|
||||
#define MS_READ_COUNT 0xFD32
|
||||
#define MS_WRITE_START 0xFD33
|
||||
#define MS_WRITE_COUNT 0xFD34
|
||||
#define MS_COMMAND 0xFD35
|
||||
#define MS_OLD_BLOCK_0 0xFD36
|
||||
#define MS_OLD_BLOCK_1 0xFD37
|
||||
#define MS_NEW_BLOCK_0 0xFD38
|
||||
#define MS_NEW_BLOCK_1 0xFD39
|
||||
#define MS_LOG_BLOCK_0 0xFD3A
|
||||
#define MS_LOG_BLOCK_1 0xFD3B
|
||||
#define MS_BUS_WIDTH 0xFD3C
|
||||
#define MS_PAGE_START 0xFD3D
|
||||
#define MS_PAGE_LENGTH 0xFD3E
|
||||
#define MS_CFG 0xFD40
|
||||
#define MS_TPC 0xFD41
|
||||
#define MS_TRANS_CFG 0xFD42
|
||||
#define MS_TRANSFER 0xFD43
|
||||
#define MS_INT_REG 0xFD44
|
||||
#define MS_BYTE_CNT 0xFD45
|
||||
#define MS_SECTOR_CNT_L 0xFD46
|
||||
#define MS_SECTOR_CNT_H 0xFD47
|
||||
#define MS_DBUS_H 0xFD48
|
||||
|
||||
#define CARD_DMA1_CTL 0xFD5C
|
||||
#define CARD_PULL_CTL1 0xFD60
|
||||
#define CARD_PULL_CTL2 0xFD61
|
||||
#define CARD_PULL_CTL3 0xFD62
|
||||
#define CARD_PULL_CTL4 0xFD63
|
||||
#define CARD_PULL_CTL5 0xFD64
|
||||
#define CARD_PULL_CTL6 0xFD65
|
||||
#define CARD_EXIST 0xFD6F
|
||||
#define CARD_INT_PEND 0xFD71
|
||||
|
||||
#define LDO_POWER_CFG 0xFD7B
|
||||
|
||||
#define SD_CFG1 0xFDA0
|
||||
#define SD_CFG2 0xFDA1
|
||||
#define SD_CFG3 0xFDA2
|
||||
#define SD_STAT1 0xFDA3
|
||||
#define SD_STAT2 0xFDA4
|
||||
#define SD_BUS_STAT 0xFDA5
|
||||
#define SD_PAD_CTL 0xFDA6
|
||||
#define SD_SAMPLE_POINT_CTL 0xFDA7
|
||||
#define SD_PUSH_POINT_CTL 0xFDA8
|
||||
#define SD_CMD0 0xFDA9
|
||||
#define SD_CMD1 0xFDAA
|
||||
#define SD_CMD2 0xFDAB
|
||||
#define SD_CMD3 0xFDAC
|
||||
#define SD_CMD4 0xFDAD
|
||||
#define SD_CMD5 0xFDAE
|
||||
#define SD_BYTE_CNT_L 0xFDAF
|
||||
#define SD_BYTE_CNT_H 0xFDB0
|
||||
#define SD_BLOCK_CNT_L 0xFDB1
|
||||
#define SD_BLOCK_CNT_H 0xFDB2
|
||||
#define SD_TRANSFER 0xFDB3
|
||||
#define SD_CMD_STATE 0xFDB5
|
||||
#define SD_DATA_STATE 0xFDB6
|
||||
#define SD_VPCLK0_CTL 0xFC2A
|
||||
#define SD_VPCLK1_CTL 0xFC2B
|
||||
#define SD_DCMPS0_CTL 0xFC2C
|
||||
#define SD_DCMPS1_CTL 0xFC2D
|
||||
|
||||
#define CARD_DMA1_CTL 0xFD5C
|
||||
|
||||
#define HW_VERSION 0xFC01
|
||||
|
||||
#define SSC_CLK_FPGA_SEL 0xFC02
|
||||
#define CLK_DIV 0xFC03
|
||||
#define SFSM_ED 0xFC04
|
||||
|
||||
#define CD_DEGLITCH_WIDTH 0xFC20
|
||||
#define CD_DEGLITCH_EN 0xFC21
|
||||
#define AUTO_DELINK_EN 0xFC23
|
||||
|
||||
#define FPGA_PULL_CTL 0xFC1D
|
||||
#define CARD_CLK_SOURCE 0xFC2E
|
||||
|
||||
#define CARD_SHARE_MODE 0xFD51
|
||||
#define CARD_DRIVE_SEL 0xFD52
|
||||
#define CARD_STOP 0xFD53
|
||||
#define CARD_OE 0xFD54
|
||||
#define CARD_AUTO_BLINK 0xFD55
|
||||
#define CARD_GPIO 0xFD56
|
||||
#define SD30_DRIVE_SEL 0xFD57
|
||||
|
||||
#define CARD_DATA_SOURCE 0xFD5D
|
||||
#define CARD_SELECT 0xFD5E
|
||||
|
||||
#define CARD_CLK_EN 0xFD79
|
||||
#define CARD_PWR_CTL 0xFD7A
|
||||
|
||||
#define OCPCTL 0xFD80
|
||||
#define OCPPARA1 0xFD81
|
||||
#define OCPPARA2 0xFD82
|
||||
#define OCPSTAT 0xFD83
|
||||
|
||||
#define HS_USB_STAT 0xFE01
|
||||
#define HS_VCONTROL 0xFE26
|
||||
#define HS_VSTAIN 0xFE27
|
||||
#define HS_VLOADM 0xFE28
|
||||
#define HS_VSTAOUT 0xFE29
|
||||
|
||||
#define MC_IRQ 0xFF00
|
||||
#define MC_IRQEN 0xFF01
|
||||
#define MC_FIFO_CTL 0xFF02
|
||||
#define MC_FIFO_BC0 0xFF03
|
||||
#define MC_FIFO_BC1 0xFF04
|
||||
#define MC_FIFO_STAT 0xFF05
|
||||
#define MC_FIFO_MODE 0xFF06
|
||||
#define MC_FIFO_RD_PTR0 0xFF07
|
||||
#define MC_FIFO_RD_PTR1 0xFF08
|
||||
#define MC_DMA_CTL 0xFF10
|
||||
#define MC_DMA_TC0 0xFF11
|
||||
#define MC_DMA_TC1 0xFF12
|
||||
#define MC_DMA_TC2 0xFF13
|
||||
#define MC_DMA_TC3 0xFF14
|
||||
#define MC_DMA_RST 0xFF15
|
||||
|
||||
#define RBUF_SIZE_MASK 0xFBFF
|
||||
#define RBUF_BASE 0xF000
|
||||
#define PPBUF_BASE1 0xF800
|
||||
#define PPBUF_BASE2 0xFA00
|
||||
|
||||
/* internal register value macros */
|
||||
#define POWER_OFF 0x03
|
||||
#define PARTIAL_POWER_ON 0x02
|
||||
#define POWER_ON 0x00
|
||||
#define POWER_MASK 0x03
|
||||
#define LDO3318_PWR_MASK 0x0C
|
||||
#define LDO_ON 0x00
|
||||
#define LDO_SUSPEND 0x08
|
||||
#define LDO_OFF 0x0C
|
||||
#define DV3318_AUTO_PWR_OFF 0x10
|
||||
#define FORCE_LDO_POWERB 0x60
|
||||
|
||||
/* LDO_POWER_CFG */
|
||||
#define TUNE_SD18_MASK 0x1C
|
||||
#define TUNE_SD18_1V7 0x00
|
||||
#define TUNE_SD18_1V8 (0x01 << 2)
|
||||
#define TUNE_SD18_1V9 (0x02 << 2)
|
||||
#define TUNE_SD18_2V0 (0x03 << 2)
|
||||
#define TUNE_SD18_2V7 (0x04 << 2)
|
||||
#define TUNE_SD18_2V8 (0x05 << 2)
|
||||
#define TUNE_SD18_2V9 (0x06 << 2)
|
||||
#define TUNE_SD18_3V3 (0x07 << 2)
|
||||
|
||||
/* CLK_DIV */
|
||||
#define CLK_CHANGE 0x80
|
||||
#define CLK_DIV_1 0x00
|
||||
#define CLK_DIV_2 0x01
|
||||
#define CLK_DIV_4 0x02
|
||||
#define CLK_DIV_8 0x03
|
||||
|
||||
#define SSC_POWER_MASK 0x01
|
||||
#define SSC_POWER_DOWN 0x01
|
||||
#define SSC_POWER_ON 0x00
|
||||
|
||||
#define FPGA_VER 0x80
|
||||
#define HW_VER_MASK 0x0F
|
||||
|
||||
#define EXTEND_DMA1_ASYNC_SIGNAL 0x02
|
||||
|
||||
/* CFG_MODE*/
|
||||
#define XTAL_FREE 0x80
|
||||
#define CLK_MODE_MASK 0x03
|
||||
#define CLK_MODE_12M_XTAL 0x00
|
||||
#define CLK_MODE_NON_XTAL 0x01
|
||||
#define CLK_MODE_24M_OSC 0x02
|
||||
#define CLK_MODE_48M_OSC 0x03
|
||||
|
||||
/* CFG_MODE_1*/
|
||||
#define RTS5179 0x02
|
||||
|
||||
#define NYET_EN 0x01
|
||||
#define NYET_MSAK 0x01
|
||||
|
||||
#define SD30_DRIVE_MASK 0x07
|
||||
#define SD20_DRIVE_MASK 0x03
|
||||
|
||||
#define DISABLE_SD_CD 0x08
|
||||
#define DISABLE_MS_CD 0x10
|
||||
#define DISABLE_XD_CD 0x20
|
||||
#define SD_CD_DEGLITCH_EN 0x01
|
||||
#define MS_CD_DEGLITCH_EN 0x02
|
||||
#define XD_CD_DEGLITCH_EN 0x04
|
||||
|
||||
#define CARD_SHARE_LQFP48 0x04
|
||||
#define CARD_SHARE_QFN24 0x00
|
||||
#define CARD_SHARE_LQFP_SEL 0x04
|
||||
#define CARD_SHARE_XD 0x00
|
||||
#define CARD_SHARE_SD 0x01
|
||||
#define CARD_SHARE_MS 0x02
|
||||
#define CARD_SHARE_MASK 0x03
|
||||
|
||||
|
||||
/* SD30_DRIVE_SEL */
|
||||
#define DRIVER_TYPE_A 0x05
|
||||
#define DRIVER_TYPE_B 0x03
|
||||
#define DRIVER_TYPE_C 0x02
|
||||
#define DRIVER_TYPE_D 0x01
|
||||
|
||||
/* SD_BUS_STAT */
|
||||
#define SD_CLK_TOGGLE_EN 0x80
|
||||
#define SD_CLK_FORCE_STOP 0x40
|
||||
#define SD_DAT3_STATUS 0x10
|
||||
#define SD_DAT2_STATUS 0x08
|
||||
#define SD_DAT1_STATUS 0x04
|
||||
#define SD_DAT0_STATUS 0x02
|
||||
#define SD_CMD_STATUS 0x01
|
||||
|
||||
/* SD_PAD_CTL */
|
||||
#define SD_IO_USING_1V8 0x80
|
||||
#define SD_IO_USING_3V3 0x7F
|
||||
#define TYPE_A_DRIVING 0x00
|
||||
#define TYPE_B_DRIVING 0x01
|
||||
#define TYPE_C_DRIVING 0x02
|
||||
#define TYPE_D_DRIVING 0x03
|
||||
|
||||
/* CARD_CLK_EN */
|
||||
#define SD_CLK_EN 0x04
|
||||
#define MS_CLK_EN 0x08
|
||||
|
||||
/* CARD_SELECT */
|
||||
#define SD_MOD_SEL 2
|
||||
#define MS_MOD_SEL 3
|
||||
|
||||
/* CARD_SHARE_MODE */
|
||||
#define CARD_SHARE_LQFP48 0x04
|
||||
#define CARD_SHARE_QFN24 0x00
|
||||
#define CARD_SHARE_LQFP_SEL 0x04
|
||||
#define CARD_SHARE_XD 0x00
|
||||
#define CARD_SHARE_SD 0x01
|
||||
#define CARD_SHARE_MS 0x02
|
||||
#define CARD_SHARE_MASK 0x03
|
||||
|
||||
/* SSC_CTL1 */
|
||||
#define SSC_RSTB 0x80
|
||||
#define SSC_8X_EN 0x40
|
||||
#define SSC_FIX_FRAC 0x20
|
||||
#define SSC_SEL_1M 0x00
|
||||
#define SSC_SEL_2M 0x08
|
||||
#define SSC_SEL_4M 0x10
|
||||
#define SSC_SEL_8M 0x18
|
||||
|
||||
/* SSC_CTL2 */
|
||||
#define SSC_DEPTH_MASK 0x03
|
||||
#define SSC_DEPTH_DISALBE 0x00
|
||||
#define SSC_DEPTH_2M 0x01
|
||||
#define SSC_DEPTH_1M 0x02
|
||||
#define SSC_DEPTH_512K 0x03
|
||||
|
||||
/* SD_VPCLK0_CTL */
|
||||
#define PHASE_CHANGE 0x80
|
||||
#define PHASE_NOT_RESET 0x40
|
||||
|
||||
/* SD_TRANSFER */
|
||||
#define SD_TRANSFER_START 0x80
|
||||
#define SD_TRANSFER_END 0x40
|
||||
#define SD_STAT_IDLE 0x20
|
||||
#define SD_TRANSFER_ERR 0x10
|
||||
#define SD_TM_NORMAL_WRITE 0x00
|
||||
#define SD_TM_AUTO_WRITE_3 0x01
|
||||
#define SD_TM_AUTO_WRITE_4 0x02
|
||||
#define SD_TM_AUTO_READ_3 0x05
|
||||
#define SD_TM_AUTO_READ_4 0x06
|
||||
#define SD_TM_CMD_RSP 0x08
|
||||
#define SD_TM_AUTO_WRITE_1 0x09
|
||||
#define SD_TM_AUTO_WRITE_2 0x0A
|
||||
#define SD_TM_NORMAL_READ 0x0C
|
||||
#define SD_TM_AUTO_READ_1 0x0D
|
||||
#define SD_TM_AUTO_READ_2 0x0E
|
||||
#define SD_TM_AUTO_TUNING 0x0F
|
||||
|
||||
/* SD_CFG1 */
|
||||
#define SD_CLK_DIVIDE_0 0x00
|
||||
#define SD_CLK_DIVIDE_256 0xC0
|
||||
#define SD_CLK_DIVIDE_128 0x80
|
||||
#define SD_CLK_DIVIDE_MASK 0xC0
|
||||
#define SD_BUS_WIDTH_1BIT 0x00
|
||||
#define SD_BUS_WIDTH_4BIT 0x01
|
||||
#define SD_BUS_WIDTH_8BIT 0x02
|
||||
#define SD_ASYNC_FIFO_RST 0x10
|
||||
#define SD_20_MODE 0x00
|
||||
#define SD_DDR_MODE 0x04
|
||||
#define SD_30_MODE 0x08
|
||||
|
||||
/* SD_CFG2 */
|
||||
#define SD_CALCULATE_CRC7 0x00
|
||||
#define SD_NO_CALCULATE_CRC7 0x80
|
||||
#define SD_CHECK_CRC16 0x00
|
||||
#define SD_NO_CHECK_CRC16 0x40
|
||||
#define SD_WAIT_CRC_TO_EN 0x20
|
||||
#define SD_WAIT_BUSY_END 0x08
|
||||
#define SD_NO_WAIT_BUSY_END 0x00
|
||||
#define SD_CHECK_CRC7 0x00
|
||||
#define SD_NO_CHECK_CRC7 0x04
|
||||
#define SD_RSP_LEN_0 0x00
|
||||
#define SD_RSP_LEN_6 0x01
|
||||
#define SD_RSP_LEN_17 0x02
|
||||
#define SD_RSP_TYPE_R0 0x04
|
||||
#define SD_RSP_TYPE_R1 0x01
|
||||
#define SD_RSP_TYPE_R1b 0x09
|
||||
#define SD_RSP_TYPE_R2 0x02
|
||||
#define SD_RSP_TYPE_R3 0x05
|
||||
#define SD_RSP_TYPE_R4 0x05
|
||||
#define SD_RSP_TYPE_R5 0x01
|
||||
#define SD_RSP_TYPE_R6 0x01
|
||||
#define SD_RSP_TYPE_R7 0x01
|
||||
|
||||
/* SD_STAT1 */
|
||||
#define SD_CRC7_ERR 0x80
|
||||
#define SD_CRC16_ERR 0x40
|
||||
#define SD_CRC_WRITE_ERR 0x20
|
||||
#define SD_CRC_WRITE_ERR_MASK 0x1C
|
||||
#define GET_CRC_TIME_OUT 0x02
|
||||
#define SD_TUNING_COMPARE_ERR 0x01
|
||||
|
||||
/* SD_DATA_STATE */
|
||||
#define SD_DATA_IDLE 0x80
|
||||
|
||||
/* CARD_DATA_SOURCE */
|
||||
#define PINGPONG_BUFFER 0x01
|
||||
#define RING_BUFFER 0x00
|
||||
|
||||
/* CARD_OE */
|
||||
#define SD_OUTPUT_EN 0x04
|
||||
#define MS_OUTPUT_EN 0x08
|
||||
|
||||
/* CARD_STOP */
|
||||
#define SD_STOP 0x04
|
||||
#define MS_STOP 0x08
|
||||
#define SD_CLR_ERR 0x40
|
||||
#define MS_CLR_ERR 0x80
|
||||
|
||||
/* CARD_CLK_SOURCE */
|
||||
#define CRC_FIX_CLK (0x00 << 0)
|
||||
#define CRC_VAR_CLK0 (0x01 << 0)
|
||||
#define CRC_VAR_CLK1 (0x02 << 0)
|
||||
#define SD30_FIX_CLK (0x00 << 2)
|
||||
#define SD30_VAR_CLK0 (0x01 << 2)
|
||||
#define SD30_VAR_CLK1 (0x02 << 2)
|
||||
#define SAMPLE_FIX_CLK (0x00 << 4)
|
||||
#define SAMPLE_VAR_CLK0 (0x01 << 4)
|
||||
#define SAMPLE_VAR_CLK1 (0x02 << 4)
|
||||
|
||||
/* SD_SAMPLE_POINT_CTL */
|
||||
#define DDR_FIX_RX_DAT 0x00
|
||||
#define DDR_VAR_RX_DAT 0x80
|
||||
#define DDR_FIX_RX_DAT_EDGE 0x00
|
||||
#define DDR_FIX_RX_DAT_14_DELAY 0x40
|
||||
#define DDR_FIX_RX_CMD 0x00
|
||||
#define DDR_VAR_RX_CMD 0x20
|
||||
#define DDR_FIX_RX_CMD_POS_EDGE 0x00
|
||||
#define DDR_FIX_RX_CMD_14_DELAY 0x10
|
||||
#define SD20_RX_POS_EDGE 0x00
|
||||
#define SD20_RX_14_DELAY 0x08
|
||||
#define SD20_RX_SEL_MASK 0x08
|
||||
|
||||
/* SD_PUSH_POINT_CTL */
|
||||
#define DDR_FIX_TX_CMD_DAT 0x00
|
||||
#define DDR_VAR_TX_CMD_DAT 0x80
|
||||
#define DDR_FIX_TX_DAT_14_TSU 0x00
|
||||
#define DDR_FIX_TX_DAT_12_TSU 0x40
|
||||
#define DDR_FIX_TX_CMD_NEG_EDGE 0x00
|
||||
#define DDR_FIX_TX_CMD_14_AHEAD 0x20
|
||||
#define SD20_TX_NEG_EDGE 0x00
|
||||
#define SD20_TX_14_AHEAD 0x10
|
||||
#define SD20_TX_SEL_MASK 0x10
|
||||
#define DDR_VAR_SDCLK_POL_SWAP 0x01
|
||||
|
||||
/* MS_CFG */
|
||||
#define SAMPLE_TIME_RISING 0x00
|
||||
#define SAMPLE_TIME_FALLING 0x80
|
||||
#define PUSH_TIME_DEFAULT 0x00
|
||||
#define PUSH_TIME_ODD 0x40
|
||||
#define NO_EXTEND_TOGGLE 0x00
|
||||
#define EXTEND_TOGGLE_CHK 0x20
|
||||
#define MS_BUS_WIDTH_1 0x00
|
||||
#define MS_BUS_WIDTH_4 0x10
|
||||
#define MS_BUS_WIDTH_8 0x18
|
||||
#define MS_2K_SECTOR_MODE 0x04
|
||||
#define MS_512_SECTOR_MODE 0x00
|
||||
#define MS_TOGGLE_TIMEOUT_EN 0x00
|
||||
#define MS_TOGGLE_TIMEOUT_DISEN 0x01
|
||||
#define MS_NO_CHECK_INT 0x02
|
||||
|
||||
/* MS_TRANS_CFG */
|
||||
#define WAIT_INT 0x80
|
||||
#define NO_WAIT_INT 0x00
|
||||
#define NO_AUTO_READ_INT_REG 0x00
|
||||
#define AUTO_READ_INT_REG 0x40
|
||||
#define MS_CRC16_ERR 0x20
|
||||
#define MS_RDY_TIMEOUT 0x10
|
||||
#define MS_INT_CMDNK 0x08
|
||||
#define MS_INT_BREQ 0x04
|
||||
#define MS_INT_ERR 0x02
|
||||
#define MS_INT_CED 0x01
|
||||
|
||||
/* MS_TRANSFER */
|
||||
#define MS_TRANSFER_START 0x80
|
||||
#define MS_TRANSFER_END 0x40
|
||||
#define MS_TRANSFER_ERR 0x20
|
||||
#define MS_BS_STATE 0x10
|
||||
#define MS_TM_READ_BYTES 0x00
|
||||
#define MS_TM_NORMAL_READ 0x01
|
||||
#define MS_TM_WRITE_BYTES 0x04
|
||||
#define MS_TM_NORMAL_WRITE 0x05
|
||||
#define MS_TM_AUTO_READ 0x08
|
||||
#define MS_TM_AUTO_WRITE 0x0C
|
||||
#define MS_TM_SET_CMD 0x06
|
||||
#define MS_TM_COPY_PAGE 0x07
|
||||
#define MS_TM_MULTI_READ 0x02
|
||||
#define MS_TM_MULTI_WRITE 0x03
|
||||
|
||||
/* MC_FIFO_CTL */
|
||||
#define FIFO_FLUSH 0x01
|
||||
|
||||
/* MC_DMA_RST */
|
||||
#define DMA_RESET 0x01
|
||||
|
||||
/* MC_DMA_CTL */
|
||||
#define DMA_TC_EQ_0 0x80
|
||||
#define DMA_DIR_TO_CARD 0x00
|
||||
#define DMA_DIR_FROM_CARD 0x02
|
||||
#define DMA_EN 0x01
|
||||
#define DMA_128 (0 << 2)
|
||||
#define DMA_256 (1 << 2)
|
||||
#define DMA_512 (2 << 2)
|
||||
#define DMA_1024 (3 << 2)
|
||||
#define DMA_PACK_SIZE_MASK 0x0C
|
||||
|
||||
/* CARD_INT_PEND */
|
||||
#define XD_INT 0x10
|
||||
#define MS_INT 0x08
|
||||
#define SD_INT 0x04
|
||||
|
||||
/* LED operations*/
|
||||
static inline int rtsx_usb_turn_on_led(struct rtsx_ucr *ucr)
|
||||
{
|
||||
return rtsx_usb_ep0_write_register(ucr, CARD_GPIO, 0x03, 0x02);
|
||||
}
|
||||
|
||||
static inline int rtsx_usb_turn_off_led(struct rtsx_ucr *ucr)
|
||||
{
|
||||
return rtsx_usb_ep0_write_register(ucr, CARD_GPIO, 0x03, 0x03);
|
||||
}
|
||||
|
||||
/* HW error clearing */
|
||||
static inline void rtsx_usb_clear_fsm_err(struct rtsx_ucr *ucr)
|
||||
{
|
||||
rtsx_usb_ep0_write_register(ucr, SFSM_ED, 0xf8, 0xf8);
|
||||
}
|
||||
|
||||
static inline void rtsx_usb_clear_dma_err(struct rtsx_ucr *ucr)
|
||||
{
|
||||
rtsx_usb_ep0_write_register(ucr, MC_FIFO_CTL,
|
||||
FIFO_FLUSH, FIFO_FLUSH);
|
||||
rtsx_usb_ep0_write_register(ucr, MC_DMA_RST, DMA_RESET, DMA_RESET);
|
||||
}
|
||||
#endif /* __RTS51139_H */
|
284
include/linux/mfd/tps65218.h
Normal file
284
include/linux/mfd/tps65218.h
Normal file
@@ -0,0 +1,284 @@
|
||||
/*
|
||||
* linux/mfd/tps65218.h
|
||||
*
|
||||
* Functions to access TPS65219 power management chip.
|
||||
*
|
||||
* Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
||||
* kind, whether expressed or implied; without even the implied warranty
|
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License version 2 for more details.
|
||||
*/
|
||||
|
||||
#ifndef __LINUX_MFD_TPS65218_H
|
||||
#define __LINUX_MFD_TPS65218_H
|
||||
|
||||
#include <linux/i2c.h>
|
||||
#include <linux/regulator/driver.h>
|
||||
#include <linux/regulator/machine.h>
|
||||
#include <linux/bitops.h>
|
||||
|
||||
/* TPS chip id list */
|
||||
#define TPS65218 0xF0
|
||||
|
||||
/* I2C ID for TPS65218 part */
|
||||
#define TPS65218_I2C_ID 0x24
|
||||
|
||||
/* All register addresses */
|
||||
#define TPS65218_REG_CHIPID 0x00
|
||||
#define TPS65218_REG_INT1 0x01
|
||||
#define TPS65218_REG_INT2 0x02
|
||||
#define TPS65218_REG_INT_MASK1 0x03
|
||||
#define TPS65218_REG_INT_MASK2 0x04
|
||||
#define TPS65218_REG_STATUS 0x05
|
||||
#define TPS65218_REG_CONTROL 0x06
|
||||
#define TPS65218_REG_FLAG 0x07
|
||||
|
||||
#define TPS65218_REG_PASSWORD 0x10
|
||||
#define TPS65218_REG_ENABLE1 0x11
|
||||
#define TPS65218_REG_ENABLE2 0x12
|
||||
#define TPS65218_REG_CONFIG1 0x13
|
||||
#define TPS65218_REG_CONFIG2 0x14
|
||||
#define TPS65218_REG_CONFIG3 0x15
|
||||
#define TPS65218_REG_CONTROL_DCDC1 0x16
|
||||
#define TPS65218_REG_CONTROL_DCDC2 0x17
|
||||
#define TPS65218_REG_CONTROL_DCDC3 0x18
|
||||
#define TPS65218_REG_CONTROL_DCDC4 0x19
|
||||
#define TPS65218_REG_CONTRL_SLEW_RATE 0x1A
|
||||
#define TPS65218_REG_CONTROL_LDO1 0x1B
|
||||
#define TPS65218_REG_SEQ1 0x20
|
||||
#define TPS65218_REG_SEQ2 0x21
|
||||
#define TPS65218_REG_SEQ3 0x22
|
||||
#define TPS65218_REG_SEQ4 0x23
|
||||
#define TPS65218_REG_SEQ5 0x24
|
||||
#define TPS65218_REG_SEQ6 0x25
|
||||
#define TPS65218_REG_SEQ7 0x26
|
||||
|
||||
/* Register field definitions */
|
||||
#define TPS65218_CHIPID_CHIP_MASK 0xF8
|
||||
#define TPS65218_CHIPID_REV_MASK 0x07
|
||||
|
||||
#define TPS65218_INT1_VPRG BIT(5)
|
||||
#define TPS65218_INT1_AC BIT(4)
|
||||
#define TPS65218_INT1_PB BIT(3)
|
||||
#define TPS65218_INT1_HOT BIT(2)
|
||||
#define TPS65218_INT1_CC_AQC BIT(1)
|
||||
#define TPS65218_INT1_PRGC BIT(0)
|
||||
|
||||
#define TPS65218_INT2_LS3_F BIT(5)
|
||||
#define TPS65218_INT2_LS2_F BIT(4)
|
||||
#define TPS65218_INT2_LS1_F BIT(3)
|
||||
#define TPS65218_INT2_LS3_I BIT(2)
|
||||
#define TPS65218_INT2_LS2_I BIT(1)
|
||||
#define TPS65218_INT2_LS1_I BIT(0)
|
||||
|
||||
#define TPS65218_INT_MASK1_VPRG BIT(5)
|
||||
#define TPS65218_INT_MASK1_AC BIT(4)
|
||||
#define TPS65218_INT_MASK1_PB BIT(3)
|
||||
#define TPS65218_INT_MASK1_HOT BIT(2)
|
||||
#define TPS65218_INT_MASK1_CC_AQC BIT(1)
|
||||
#define TPS65218_INT_MASK1_PRGC BIT(0)
|
||||
|
||||
#define TPS65218_INT_MASK2_LS3_F BIT(5)
|
||||
#define TPS65218_INT_MASK2_LS2_F BIT(4)
|
||||
#define TPS65218_INT_MASK2_LS1_F BIT(3)
|
||||
#define TPS65218_INT_MASK2_LS3_I BIT(2)
|
||||
#define TPS65218_INT_MASK2_LS2_I BIT(1)
|
||||
#define TPS65218_INT_MASK2_LS1_I BIT(0)
|
||||
|
||||
#define TPS65218_STATUS_FSEAL BIT(7)
|
||||
#define TPS65218_STATUS_EE BIT(6)
|
||||
#define TPS65218_STATUS_AC_STATE BIT(5)
|
||||
#define TPS65218_STATUS_PB_STATE BIT(4)
|
||||
#define TPS65218_STATUS_STATE_MASK 0xC
|
||||
#define TPS65218_STATUS_CC_STAT 0x3
|
||||
|
||||
#define TPS65218_CONTROL_OFFNPFO BIT(1)
|
||||
#define TPS65218_CONTROL_CC_AQ BIT(0)
|
||||
|
||||
#define TPS65218_FLAG_GPO3_FLG BIT(7)
|
||||
#define TPS65218_FLAG_GPO2_FLG BIT(6)
|
||||
#define TPS65218_FLAG_GPO1_FLG BIT(5)
|
||||
#define TPS65218_FLAG_LDO1_FLG BIT(4)
|
||||
#define TPS65218_FLAG_DC4_FLG BIT(3)
|
||||
#define TPS65218_FLAG_DC3_FLG BIT(2)
|
||||
#define TPS65218_FLAG_DC2_FLG BIT(1)
|
||||
#define TPS65218_FLAG_DC1_FLG BIT(0)
|
||||
|
||||
#define TPS65218_ENABLE1_DC6_EN BIT(5)
|
||||
#define TPS65218_ENABLE1_DC5_EN BIT(4)
|
||||
#define TPS65218_ENABLE1_DC4_EN BIT(3)
|
||||
#define TPS65218_ENABLE1_DC3_EN BIT(2)
|
||||
#define TPS65218_ENABLE1_DC2_EN BIT(1)
|
||||
#define TPS65218_ENABLE1_DC1_EN BIT(0)
|
||||
|
||||
#define TPS65218_ENABLE2_GPIO3 BIT(6)
|
||||
#define TPS65218_ENABLE2_GPIO2 BIT(5)
|
||||
#define TPS65218_ENABLE2_GPIO1 BIT(4)
|
||||
#define TPS65218_ENABLE2_LS3_EN BIT(3)
|
||||
#define TPS65218_ENABLE2_LS2_EN BIT(2)
|
||||
#define TPS65218_ENABLE2_LS1_EN BIT(1)
|
||||
#define TPS65218_ENABLE2_LDO1_EN BIT(0)
|
||||
|
||||
|
||||
#define TPS65218_CONFIG1_TRST BIT(7)
|
||||
#define TPS65218_CONFIG1_GPO2_BUF BIT(6)
|
||||
#define TPS65218_CONFIG1_IO1_SEL BIT(5)
|
||||
#define TPS65218_CONFIG1_PGDLY_MASK 0x18
|
||||
#define TPS65218_CONFIG1_STRICT BIT(2)
|
||||
#define TPS65218_CONFIG1_UVLO_MASK 0x3
|
||||
|
||||
#define TPS65218_CONFIG2_DC12_RST BIT(7)
|
||||
#define TPS65218_CONFIG2_UVLOHYS BIT(6)
|
||||
#define TPS65218_CONFIG2_LS3ILIM_MASK 0xC
|
||||
#define TPS65218_CONFIG2_LS2ILIM_MASK 0x3
|
||||
|
||||
#define TPS65218_CONFIG3_LS3NPFO BIT(5)
|
||||
#define TPS65218_CONFIG3_LS2NPFO BIT(4)
|
||||
#define TPS65218_CONFIG3_LS1NPFO BIT(3)
|
||||
#define TPS65218_CONFIG3_LS3DCHRG BIT(2)
|
||||
#define TPS65218_CONFIG3_LS2DCHRG BIT(1)
|
||||
#define TPS65218_CONFIG3_LS1DCHRG BIT(0)
|
||||
|
||||
#define TPS65218_CONTROL_DCDC1_PFM BIT(7)
|
||||
#define TPS65218_CONTROL_DCDC1_MASK 0x7F
|
||||
|
||||
#define TPS65218_CONTROL_DCDC2_PFM BIT(7)
|
||||
#define TPS65218_CONTROL_DCDC2_MASK 0x3F
|
||||
|
||||
#define TPS65218_CONTROL_DCDC3_PFM BIT(7)
|
||||
#define TPS65218_CONTROL_DCDC3_MASK 0x3F
|
||||
|
||||
#define TPS65218_CONTROL_DCDC4_PFM BIT(7)
|
||||
#define TPS65218_CONTROL_DCDC4_MASK 0x3F
|
||||
|
||||
#define TPS65218_SLEW_RATE_GO BIT(7)
|
||||
#define TPS65218_SLEW_RATE_GODSBL BIT(6)
|
||||
#define TPS65218_SLEW_RATE_SLEW_MASK 0x7
|
||||
|
||||
#define TPS65218_CONTROL_LDO1_MASK 0x3F
|
||||
|
||||
#define TPS65218_SEQ1_DLY8 BIT(7)
|
||||
#define TPS65218_SEQ1_DLY7 BIT(6)
|
||||
#define TPS65218_SEQ1_DLY6 BIT(5)
|
||||
#define TPS65218_SEQ1_DLY5 BIT(4)
|
||||
#define TPS65218_SEQ1_DLY4 BIT(3)
|
||||
#define TPS65218_SEQ1_DLY3 BIT(2)
|
||||
#define TPS65218_SEQ1_DLY2 BIT(1)
|
||||
#define TPS65218_SEQ1_DLY1 BIT(0)
|
||||
|
||||
#define TPS65218_SEQ2_DLYFCTR BIT(7)
|
||||
#define TPS65218_SEQ2_DLY9 BIT(0)
|
||||
|
||||
#define TPS65218_SEQ3_DC2_SEQ_MASK 0xF0
|
||||
#define TPS65218_SEQ3_DC1_SEQ_MASK 0xF
|
||||
|
||||
#define TPS65218_SEQ4_DC4_SEQ_MASK 0xF0
|
||||
#define TPS65218_SEQ4_DC3_SEQ_MASK 0xF
|
||||
|
||||
#define TPS65218_SEQ5_DC6_SEQ_MASK 0xF0
|
||||
#define TPS65218_SEQ5_DC5_SEQ_MASK 0xF
|
||||
|
||||
#define TPS65218_SEQ6_LS1_SEQ_MASK 0xF0
|
||||
#define TPS65218_SEQ6_LDO1_SEQ_MASK 0xF
|
||||
|
||||
#define TPS65218_SEQ7_GPO3_SEQ_MASK 0xF0
|
||||
#define TPS65218_SEQ7_GPO1_SEQ_MASK 0xF
|
||||
#define TPS65218_PROTECT_NONE 0
|
||||
#define TPS65218_PROTECT_L1 1
|
||||
|
||||
enum tps65218_regulator_id {
|
||||
/* DCDC's */
|
||||
TPS65218_DCDC_1,
|
||||
TPS65218_DCDC_2,
|
||||
TPS65218_DCDC_3,
|
||||
TPS65218_DCDC_4,
|
||||
TPS65218_DCDC_5,
|
||||
TPS65218_DCDC_6,
|
||||
/* LDOs */
|
||||
TPS65218_LDO_1,
|
||||
};
|
||||
|
||||
#define TPS65218_MAX_REG_ID TPS65218_LDO_1
|
||||
|
||||
/* Number of step-down converters available */
|
||||
#define TPS65218_NUM_DCDC 6
|
||||
/* Number of LDO voltage regulators available */
|
||||
#define TPS65218_NUM_LDO 1
|
||||
/* Number of total regulators available */
|
||||
#define TPS65218_NUM_REGULATOR (TPS65218_NUM_DCDC + TPS65218_NUM_LDO)
|
||||
|
||||
/* Define the TPS65218 IRQ numbers */
|
||||
enum tps65218_irqs {
|
||||
/* INT1 registers */
|
||||
TPS65218_PRGC_IRQ,
|
||||
TPS65218_CC_AQC_IRQ,
|
||||
TPS65218_HOT_IRQ,
|
||||
TPS65218_PB_IRQ,
|
||||
TPS65218_AC_IRQ,
|
||||
TPS65218_VPRG_IRQ,
|
||||
TPS65218_INVALID1_IRQ,
|
||||
TPS65218_INVALID2_IRQ,
|
||||
/* INT2 registers */
|
||||
TPS65218_LS1_I_IRQ,
|
||||
TPS65218_LS2_I_IRQ,
|
||||
TPS65218_LS3_I_IRQ,
|
||||
TPS65218_LS1_F_IRQ,
|
||||
TPS65218_LS2_F_IRQ,
|
||||
TPS65218_LS3_F_IRQ,
|
||||
TPS65218_INVALID3_IRQ,
|
||||
TPS65218_INVALID4_IRQ,
|
||||
};
|
||||
|
||||
/**
|
||||
* struct tps_info - packages regulator constraints
|
||||
* @id: Id of the regulator
|
||||
* @name: Voltage regulator name
|
||||
* @min_uV: minimum micro volts
|
||||
* @max_uV: minimum micro volts
|
||||
*
|
||||
* This data is used to check the regualtor voltage limits while setting.
|
||||
*/
|
||||
struct tps_info {
|
||||
int id;
|
||||
const char *name;
|
||||
int min_uV;
|
||||
int max_uV;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct tps65218 - tps65218 sub-driver chip access routines
|
||||
*
|
||||
* Device data may be used to access the TPS65218 chip
|
||||
*/
|
||||
|
||||
struct tps65218 {
|
||||
struct device *dev;
|
||||
unsigned int id;
|
||||
|
||||
struct mutex tps_lock; /* lock guarding the data structure */
|
||||
/* IRQ Data */
|
||||
int irq;
|
||||
u32 irq_mask;
|
||||
struct regmap_irq_chip_data *irq_data;
|
||||
struct regulator_desc desc[TPS65218_NUM_REGULATOR];
|
||||
struct regulator_dev *rdev[TPS65218_NUM_REGULATOR];
|
||||
struct tps_info *info[TPS65218_NUM_REGULATOR];
|
||||
struct regmap *regmap;
|
||||
};
|
||||
|
||||
int tps65218_reg_read(struct tps65218 *tps, unsigned int reg,
|
||||
unsigned int *val);
|
||||
int tps65218_reg_write(struct tps65218 *tps, unsigned int reg,
|
||||
unsigned int val, unsigned int level);
|
||||
int tps65218_set_bits(struct tps65218 *tps, unsigned int reg,
|
||||
unsigned int mask, unsigned int val, unsigned int level);
|
||||
int tps65218_clear_bits(struct tps65218 *tps, unsigned int reg,
|
||||
unsigned int mask, unsigned int level);
|
||||
|
||||
#endif /* __LINUX_MFD_TPS65218_H */
|
Reference in New Issue
Block a user