Merge tag 'mmc-v4.6' of git://git.linaro.org/people/ulf.hansson/mmc

Pull MMC updates from Ulf Hansson:
 "MMC core:
      - Fix ABI regression of MMC BLK ioctl
      - Remove the unused MMC_DATA_STREAM flag
      - Enable asynchronous system PM for the host device
      - Minor fixes and clean-ups

  SDHCI host:
     Throughout the years, the numbers of SDHCI variants have increased
     and so has also the numbers of SDHCI callbacks/quirks.  The purpose
     of these callbacks/quirks were to enable SDHCI to deal with variant
     specific requirements, but unfortunate this method didn't scale.
     Instead we have ended up with a mess.  Not only did the code become
     suboptimal but also highly fragile.

     Lately many discussions of how to move forward with SDHCI has taken
     place at the MMC mailing list.  Step by step, we aim to turn
     SDHCI's common code into a set of library functions.  This will
     enable for optimizations and allow some of the existing callbacks
     and quirks to be removed, which also should help to make the code
     less fragile.

     Therefore I am also really pleased to announce that Adrian Hunter
     (Intel) has volunteered to step in as the maintainer for SDHCI.

     Future wise, I hope the community around SDHCI will continue to
     grow and that this release cycle can be the starting point of
     moving SDHCI into a better shape.  As a matter of fact, already in
     this cycle the re-factoring has begun, but of course there are also
     fixes and new features included.  Some highlights:

      - sdhci-iproc: Add support for Broadcom's BCM2835 eMMC IP
      - sdhci-acpi: Add support for QCOM controllers
      - sdhci-pic32: Add new SDHCI variant for PIC32MZDA

  Other hosts:
      - atmel-mci: Fix a NULL pointer dereference
      - mediatek: Add SD write-protect support
      - mmc_spi: Fix card detect in GPIO case
      - tmio/sdhi: Add r8a7795 support
      - tmio/sdhi: Some fixes and clean-ups
      - dw_mmc: Add HW reset support
      - dw_mmc: Some fixes and clean-ups
      - sunxi: Add support for MMC DDR52 mode"

* tag 'mmc-v4.6' of git://git.linaro.org/people/ulf.hansson/mmc: (123 commits)
  mmc: sdhci-of-at91: fix wake-up issue when using runtime pm
  mmc: sdhci-pci: Do not set DMA mask in enable_dma()
  mmc: sdhci-acpi: Remove enable_dma() hook
  mmc: sdhci: Set DMA mask when adding host
  mmc: block: fix ABI regression of mmc_blk_ioctl
  mmc: atmel-mci: Check pdata for NULL before dereferencing it at DMA config
  mmc: core: remove redundant memset of sdio_read_cccr
  mmc: core: remove redundant memset of mmc_decode_cid
  mmc: of_mmc_spi: fix unused warning
  mmc: sdhci-of-arasan: add phy support for sdhci-of-arasan
  mmc: sdhci-of-arasan: fix missing sdhci_pltfm_free for err handling
  mmc: sdhci-of-arasan: remove disable clk_ahb from sdhci_arasan_resume
  Documentation: bindings: add description of phy for sdhci-of-arasan
  mmc: sdhci: Fix override of timeout clk wrt max_busy_timeout
  mmc: mmci: Remove unnecessary header file
  mmc: sdhci-acpi: add QCOM controllers
  mmc: tegra: implement memcomp pad calibration
  mmc: mediatek: Use mmc_regulator_set_vqmmc in start_signal_voltage_switch
  mmc: mediatek: Change signal voltage error to dev_dbg()
  mmc: sh_mmcif, tmio: Use ARCH_RENESAS
  ...

Documentation/devicetree/bindings/mmc/arasan,sdhci.txt

@@ -1,11 +1,12 @@
 Device Tree Bindings for the Arasan SDHCI Controller
 
-  The bindings follow the mmc[1], clock[2] and interrupt[3] bindings. Only
-  deviations are documented here.
+  The bindings follow the mmc[1], clock[2], interrupt[3] and phy[4] bindings.
+  Only deviations are documented here.
 
   [1] Documentation/devicetree/bindings/mmc/mmc.txt
   [2] Documentation/devicetree/bindings/clock/clock-bindings.txt
   [3] Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
+  [4] Documentation/devicetree/bindings/phy/phy-bindings.txt
 
 Required Properties:
   - compatible: Compatibility string. Must be 'arasan,sdhci-8.9a' or
@@ -17,6 +18,10 @@ Required Properties:
   - interrupt-parent: Phandle for the interrupt controller that services
 		      interrupts for this device.
 
+Required Properties for "arasan,sdhci-5.1":
+  - phys: From PHY bindings: Phandle for the Generic PHY for arasan.
+  - phy-names:  MUST be "phy_arasan".
+
 Example:
 	sdhci@e0100000 {
 		compatible = "arasan,sdhci-8.9a";
@@ -26,3 +31,14 @@ Example:
 		interrupt-parent = <&gic>;
 		interrupts = <0 24 4>;
 	} ;
+
+	sdhci@e2800000 {
+		compatible = "arasan,sdhci-5.1";
+		reg = <0xe2800000 0x1000>;
+		clock-names = "clk_xin", "clk_ahb";
+		clocks = <&cru 8>, <&cru 18>;
+		interrupt-parent = <&gic>;
+		interrupts = <0 24 4>;
+		phys = <&emmc_phy>;
+		phy-names = "phy_arasan";
+	} ;

Documentation/devicetree/bindings/mmc/brcm,sdhci-iproc.txt

@@ -4,7 +4,10 @@ This file documents differences between the core properties described
 by mmc.txt and the properties that represent the IPROC SDHCI controller.
 
 Required properties:
-- compatible : Should be "brcm,sdhci-iproc-cygnus".
+- compatible : Should be one of the following
+	       "brcm,bcm2835-sdhci"
+	       "brcm,sdhci-iproc-cygnus"
+
 - clocks : The clock feeding the SDHCI controller.
 
 Optional properties:

Documentation/devicetree/bindings/mmc/microchip,sdhci-pic32.txt

@@ -0,0 +1,29 @@
+* Microchip PIC32 SDHCI Controller
+
+This file documents differences between the core properties in mmc.txt
+and the properties used by the sdhci-pic32 driver.
+
+Required properties:
+- compatible: Should be "microchip,pic32mzda-sdhci"
+- interrupts: Should contain interrupt
+- clock-names: Should be "base_clk", "sys_clk".
+               See: Documentation/devicetree/bindings/resource-names.txt
+- clocks: Phandle to the clock.
+          See: Documentation/devicetree/bindings/clock/clock-bindings.txt
+- pinctrl-names: A pinctrl state names "default" must be defined.
+- pinctrl-0: Phandle referencing pin configuration of the SDHCI controller.
+             See: Documentation/devicetree/bindings/pinctrl/pinctrl-binding.txt
+
+Example:
+
+	sdhci@1f8ec000 {
+		compatible = "microchip,pic32mzda-sdhci";
+		reg = <0x1f8ec000 0x100>;
+		interrupts = <191 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&REFCLKO4>, <&PBCLK5>;
+		clock-names = "base_clk", "sys_clk";
+		bus-width = <4>;
+		cap-sd-highspeed;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_sdhc1>;
+	};

Documentation/devicetree/bindings/mmc/tmio_mmc.txt

@@ -22,6 +22,7 @@ Required properties:
 		"renesas,sdhi-r8a7792" - SDHI IP on R8A7792 SoC
 		"renesas,sdhi-r8a7793" - SDHI IP on R8A7793 SoC
 		"renesas,sdhi-r8a7794" - SDHI IP on R8A7794 SoC
+		"renesas,sdhi-r8a7795" - SDHI IP on R8A7795 SoC
 
 Optional properties:
 - toshiba,mmc-wrprotect-disable: write-protect detection is unavailable