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Merge remote-tracking branch 'airlied/drm-next' into drm-intel-next-queued

Browse Source 
Backmerge drm-next - I need to backmerge drm-intel-fixes patches
touching the error capture code to be able to merge Ben's cleanup
patches.

Conflicts:
	drivers/gpu/drm/i915/i915_gpu_error.c

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Daniel Vetter
2014-01-30 12:56:51 +01:00
parent c2c1d4912c ef64cf9d06
commit e515b47e56
241 changed files with 13480 additions and 6319 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
View File

@@ -118,6 +118,9 @@ of the following host1x client modules:
See ../reset/reset.txt for details. See ../reset/reset.txt for details.
- reset-names: Must include the following entries: - reset-names: Must include the following entries:
- dc - dc
- nvidia,head: The number of the display controller head. This is used to
setup the various types of output to receive video data from the given
head.
Each display controller node has a child node, named "rgb", that represents Each display controller node has a child node, named "rgb", that represents
the RGB output associated with the controller. It can take the following the RGB output associated with the controller. It can take the following

7
Documentation/devicetree/bindings/panel/chunghwa,claa101wa01a.txt Normal file
View File

@@ -0,0 +1,7 @@
Chunghwa Picture Tubes Ltd. 10.1" WXGA TFT LCD panel
Required properties:
- compatible: should be "chunghwa,claa101wa01a"
This binding is compatible with the simple-panel binding, which is specified
in simple-panel.txt in this directory.

7
Documentation/devicetree/bindings/panel/samsung,ltn101nt05.txt Normal file
View File

@@ -0,0 +1,7 @@
Samsung Electronics 10.1" WSVGA TFT LCD panel
Required properties:
- compatible: should be "samsung,ltn101nt05"
This binding is compatible with the simple-panel binding, which is specified
in simple-panel.txt in this directory.

3
MAINTAINERS
View File

@@ -9231,6 +9231,7 @@ F: include/media/videobuf2-*
VIRTIO CONSOLE DRIVER VIRTIO CONSOLE DRIVER
M: Amit Shah <amit.shah@redhat.com> M: Amit Shah <amit.shah@redhat.com>
L: virtio-dev@lists.oasis-open.org
L: virtualization@lists.linux-foundation.org L: virtualization@lists.linux-foundation.org
S: Maintained S: Maintained
F: drivers/char/virtio_console.c F: drivers/char/virtio_console.c
@@ -9240,6 +9241,7 @@ F: include/uapi/linux/virtio_console.h
VIRTIO CORE, NET AND BLOCK DRIVERS VIRTIO CORE, NET AND BLOCK DRIVERS
M: Rusty Russell <rusty@rustcorp.com.au> M: Rusty Russell <rusty@rustcorp.com.au>
M: "Michael S. Tsirkin" <mst@redhat.com> M: "Michael S. Tsirkin" <mst@redhat.com>
L: virtio-dev@lists.oasis-open.org
L: virtualization@lists.linux-foundation.org L: virtualization@lists.linux-foundation.org
S: Maintained S: Maintained
F: drivers/virtio/ F: drivers/virtio/
@@ -9252,6 +9254,7 @@ F: include/uapi/linux/virtio_*.h
VIRTIO HOST (VHOST) VIRTIO HOST (VHOST)
M: "Michael S. Tsirkin" <mst@redhat.com> M: "Michael S. Tsirkin" <mst@redhat.com>
L: kvm@vger.kernel.org L: kvm@vger.kernel.org
L: virtio-dev@lists.oasis-open.org
L: virtualization@lists.linux-foundation.org L: virtualization@lists.linux-foundation.org
L: netdev@vger.kernel.org L: netdev@vger.kernel.org
S: Maintained S: Maintained

2
Makefile
View File

@@ -1,7 +1,7 @@
VERSION = 3 VERSION = 3
PATCHLEVEL = 13 PATCHLEVEL = 13
SUBLEVEL = 0 SUBLEVEL = 0
EXTRAVERSION = -rc8 EXTRAVERSION =
NAME = One Giant Leap for Frogkind NAME = One Giant Leap for Frogkind
# *DOCUMENTATION* # *DOCUMENTATION*

2
arch/arm/kernel/devtree.c
View File

@@ -171,7 +171,7 @@ void __init arm_dt_init_cpu_maps(void)
bool arch_match_cpu_phys_id(int cpu, u64 phys_id) bool arch_match_cpu_phys_id(int cpu, u64 phys_id)
{ {
return (phys_id & MPIDR_HWID_BITMASK) == cpu_logical_map(cpu); return phys_id == cpu_logical_map(cpu);
} }
static const void * __init arch_get_next_mach(const char *const **match) static const void * __init arch_get_next_mach(const char *const **match)

2
arch/arm/kernel/perf_event_cpu.c
View File

@@ -254,7 +254,7 @@ static int probe_current_pmu(struct arm_pmu *pmu)
static int cpu_pmu_device_probe(struct platform_device *pdev) static int cpu_pmu_device_probe(struct platform_device *pdev)
{ {
const struct of_device_id *of_id; const struct of_device_id *of_id;
int (*init_fn)(struct arm_pmu *); const int (*init_fn)(struct arm_pmu *);
struct device_node *node = pdev->dev.of_node; struct device_node *node = pdev->dev.of_node;
struct arm_pmu *pmu; struct arm_pmu *pmu;
int ret = -ENODEV; int ret = -ENODEV;

5
arch/arm/kernel/traps.c
View File

@@ -431,9 +431,10 @@ asmlinkage void __exception do_undefinstr(struct pt_regs *regs)
instr2 = __mem_to_opcode_thumb16(instr2); instr2 = __mem_to_opcode_thumb16(instr2);
instr = __opcode_thumb32_compose(instr, instr2); instr = __opcode_thumb32_compose(instr, instr2);
} }
} else if (get_user(instr, (u32 __user *)pc)) { } else {
if (get_user(instr, (u32 __user *)pc))
goto die_sig;
instr = __mem_to_opcode_arm(instr); instr = __mem_to_opcode_arm(instr);
goto die_sig;
} }
if (call_undef_hook(regs, instr) == 0) if (call_undef_hook(regs, instr) == 0)

1
arch/arm/mach-highbank/highbank.c
View File

@@ -53,6 +53,7 @@ static void __init highbank_scu_map_io(void)
static void highbank_l2x0_disable(void) static void highbank_l2x0_disable(void)
{ {
outer_flush_all();
/* Disable PL310 L2 Cache controller */ /* Disable PL310 L2 Cache controller */
highbank_smc1(0x102, 0x0); highbank_smc1(0x102, 0x0);
} }

1
arch/arm/mach-omap2/omap4-common.c
View File

@@ -162,6 +162,7 @@ void __iomem *omap4_get_l2cache_base(void)
static void omap4_l2x0_disable(void) static void omap4_l2x0_disable(void)
{ {
outer_flush_all();
/* Disable PL310 L2 Cache controller */ /* Disable PL310 L2 Cache controller */
omap_smc1(0x102, 0x0); omap_smc1(0x102, 0x0);
} }

2
arch/arm/mm/init.c
View File

@@ -229,7 +229,7 @@ void __init setup_dma_zone(const struct machine_desc *mdesc)
#ifdef CONFIG_ZONE_DMA #ifdef CONFIG_ZONE_DMA
if (mdesc->dma_zone_size) { if (mdesc->dma_zone_size) {
arm_dma_zone_size = mdesc->dma_zone_size; arm_dma_zone_size = mdesc->dma_zone_size;
arm_dma_limit = __pv_phys_offset + arm_dma_zone_size - 1; arm_dma_limit = PHYS_OFFSET + arm_dma_zone_size - 1;
} else } else
arm_dma_limit = 0xffffffff; arm_dma_limit = 0xffffffff;
arm_dma_pfn_limit = arm_dma_limit >> PAGE_SHIFT; arm_dma_pfn_limit = arm_dma_limit >> PAGE_SHIFT;

6
arch/arm/net/bpf_jit_32.c
View File

@@ -641,10 +641,10 @@ load_ind:
emit(ARM_MUL(r_A, r_A, r_X), ctx); emit(ARM_MUL(r_A, r_A, r_X), ctx);
break; break;
case BPF_S_ALU_DIV_K: case BPF_S_ALU_DIV_K:
/* current k == reciprocal_value(userspace k) */ if (k == 1)
break;
emit_mov_i(r_scratch, k, ctx); emit_mov_i(r_scratch, k, ctx);
/* A = top 32 bits of the product */ emit_udiv(r_A, r_A, r_scratch, ctx);
emit(ARM_UMULL(r_scratch, r_A, r_A, r_scratch), ctx);
break; break;
case BPF_S_ALU_DIV_X: case BPF_S_ALU_DIV_X:
update_on_xread(ctx); update_on_xread(ctx);

2
arch/arm64/include/asm/io.h
View File

@@ -229,7 +229,7 @@ extern void __iomem *__ioremap(phys_addr_t phys_addr, size_t size, pgprot_t prot
extern void __iounmap(volatile void __iomem *addr); extern void __iounmap(volatile void __iomem *addr);
extern void __iomem *ioremap_cache(phys_addr_t phys_addr, size_t size); extern void __iomem *ioremap_cache(phys_addr_t phys_addr, size_t size);
#define PROT_DEFAULT (pgprot_default | PTE_DIRTY) #define PROT_DEFAULT (PTE_TYPE_PAGE | PTE_AF | PTE_DIRTY)
#define PROT_DEVICE_nGnRE (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_ATTRINDX(MT_DEVICE_nGnRE)) #define PROT_DEVICE_nGnRE (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_ATTRINDX(MT_DEVICE_nGnRE))
#define PROT_NORMAL_NC (PROT_DEFAULT | PTE_ATTRINDX(MT_NORMAL_NC)) #define PROT_NORMAL_NC (PROT_DEFAULT | PTE_ATTRINDX(MT_NORMAL_NC))
#define PROT_NORMAL (PROT_DEFAULT | PTE_ATTRINDX(MT_NORMAL)) #define PROT_NORMAL (PROT_DEFAULT | PTE_ATTRINDX(MT_NORMAL))

2
arch/mips/include/asm/cacheops.h
View File

@@ -83,6 +83,6 @@
/* /*
* Loongson2-specific cacheops * Loongson2-specific cacheops
*/ */
#define Hit_Invalidate_I_Loongson23 0x00 #define Hit_Invalidate_I_Loongson2 0x00
#endif /* __ASM_CACHEOPS_H */ #endif /* __ASM_CACHEOPS_H */

49
arch/mips/include/asm/r4kcache.h
View File

@@ -165,7 +165,7 @@ static inline void flush_icache_line(unsigned long addr)
__iflush_prologue __iflush_prologue
switch (boot_cpu_type()) { switch (boot_cpu_type()) {
case CPU_LOONGSON2: case CPU_LOONGSON2:
cache_op(Hit_Invalidate_I_Loongson23, addr); cache_op(Hit_Invalidate_I_Loongson2, addr);
break; break;
default: default:
@@ -219,7 +219,7 @@ static inline void protected_flush_icache_line(unsigned long addr)
{ {
switch (boot_cpu_type()) { switch (boot_cpu_type()) {
case CPU_LOONGSON2: case CPU_LOONGSON2:
protected_cache_op(Hit_Invalidate_I_Loongson23, addr); protected_cache_op(Hit_Invalidate_I_Loongson2, addr);
break; break;
default: default:
@@ -357,8 +357,8 @@ static inline void invalidate_tcache_page(unsigned long addr)
"i" (op)); "i" (op));
/* build blast_xxx, blast_xxx_page, blast_xxx_page_indexed */ /* build blast_xxx, blast_xxx_page, blast_xxx_page_indexed */
#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize) \ #define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize, extra) \
static inline void blast_##pfx##cache##lsize(void) \ static inline void extra##blast_##pfx##cache##lsize(void) \
{ \ { \
unsigned long start = INDEX_BASE; \ unsigned long start = INDEX_BASE; \
unsigned long end = start + current_cpu_data.desc.waysize; \ unsigned long end = start + current_cpu_data.desc.waysize; \
@@ -376,7 +376,7 @@ static inline void blast_##pfx##cache##lsize(void) \
__##pfx##flush_epilogue \ __##pfx##flush_epilogue \
} \ } \
\ \
static inline void blast_##pfx##cache##lsize##_page(unsigned long page) \ static inline void extra##blast_##pfx##cache##lsize##_page(unsigned long page) \
{ \ { \
unsigned long start = page; \ unsigned long start = page; \
unsigned long end = page + PAGE_SIZE; \ unsigned long end = page + PAGE_SIZE; \
@@ -391,7 +391,7 @@ static inline void blast_##pfx##cache##lsize##_page(unsigned long page) \
__##pfx##flush_epilogue \ __##pfx##flush_epilogue \
} \ } \
\ \
static inline void blast_##pfx##cache##lsize##_page_indexed(unsigned long page) \ static inline void extra##blast_##pfx##cache##lsize##_page_indexed(unsigned long page) \
{ \ { \
unsigned long indexmask = current_cpu_data.desc.waysize - 1; \ unsigned long indexmask = current_cpu_data.desc.waysize - 1; \
unsigned long start = INDEX_BASE + (page & indexmask); \ unsigned long start = INDEX_BASE + (page & indexmask); \
@@ -410,23 +410,24 @@ static inline void blast_##pfx##cache##lsize##_page_indexed(unsigned long page)
__##pfx##flush_epilogue \ __##pfx##flush_epilogue \
} }
__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16) __BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16, )
__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16) __BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16, )
__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16) __BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16, )
__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32) __BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32, )
__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32) __BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32, )
__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32) __BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I_Loongson2, 32, loongson2_)
__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 64) __BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32, )
__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64) __BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 64, )
__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64) __BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64, )
__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128) __BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64, )
__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128, )
__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16) __BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16, )
__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32) __BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32, )
__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 16) __BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 16, )
__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 32) __BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 32, )
__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64) __BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64, )
__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128) __BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128, )
/* build blast_xxx_range, protected_blast_xxx_range */ /* build blast_xxx_range, protected_blast_xxx_range */
#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot, extra) \ #define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot, extra) \
@@ -452,8 +453,8 @@ static inline void prot##extra##blast_##pfx##cache##_range(unsigned long start,
__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, ) __BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, )
__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_, ) __BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_, )
__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_, ) __BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_, )
__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I_Loongson23, \ __BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I_Loongson2, \
protected_, loongson23_) protected_, loongson2_)
__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, , ) __BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, , )
__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, , ) __BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, , )
/* blast_inv_dcache_range */ /* blast_inv_dcache_range */

11
arch/mips/mm/c-r4k.c
View File

@@ -237,6 +237,8 @@ static void r4k_blast_icache_page_setup(void)
r4k_blast_icache_page = (void *)cache_noop; r4k_blast_icache_page = (void *)cache_noop;
else if (ic_lsize == 16) else if (ic_lsize == 16)
r4k_blast_icache_page = blast_icache16_page; r4k_blast_icache_page = blast_icache16_page;
else if (ic_lsize == 32 && current_cpu_type() == CPU_LOONGSON2)
r4k_blast_icache_page = loongson2_blast_icache32_page;
else if (ic_lsize == 32) else if (ic_lsize == 32)
r4k_blast_icache_page = blast_icache32_page; r4k_blast_icache_page = blast_icache32_page;
else if (ic_lsize == 64) else if (ic_lsize == 64)
@@ -261,6 +263,9 @@ static void r4k_blast_icache_page_indexed_setup(void)
else if (TX49XX_ICACHE_INDEX_INV_WAR) else if (TX49XX_ICACHE_INDEX_INV_WAR)
r4k_blast_icache_page_indexed = r4k_blast_icache_page_indexed =
tx49_blast_icache32_page_indexed; tx49_blast_icache32_page_indexed;
else if (current_cpu_type() == CPU_LOONGSON2)
r4k_blast_icache_page_indexed =
loongson2_blast_icache32_page_indexed;
else else
r4k_blast_icache_page_indexed = r4k_blast_icache_page_indexed =
blast_icache32_page_indexed; blast_icache32_page_indexed;
@@ -284,6 +289,8 @@ static void r4k_blast_icache_setup(void)
r4k_blast_icache = blast_r4600_v1_icache32; r4k_blast_icache = blast_r4600_v1_icache32;
else if (TX49XX_ICACHE_INDEX_INV_WAR) else if (TX49XX_ICACHE_INDEX_INV_WAR)
r4k_blast_icache = tx49_blast_icache32; r4k_blast_icache = tx49_blast_icache32;
else if (current_cpu_type() == CPU_LOONGSON2)
r4k_blast_icache = loongson2_blast_icache32;
else else
r4k_blast_icache = blast_icache32; r4k_blast_icache = blast_icache32;
} else if (ic_lsize == 64) } else if (ic_lsize == 64)
@@ -580,11 +587,11 @@ static inline void local_r4k_flush_icache_range(unsigned long start, unsigned lo
else { else {
switch (boot_cpu_type()) { switch (boot_cpu_type()) {
case CPU_LOONGSON2: case CPU_LOONGSON2:
protected_blast_icache_range(start, end); protected_loongson2_blast_icache_range(start, end);
break; break;
default: default:
protected_loongson23_blast_icache_range(start, end); protected_blast_icache_range(start, end);
break; break;
} }
} }

2
arch/parisc/include/uapi/asm/socket.h
View File

@@ -75,6 +75,6 @@
#define SO_BUSY_POLL 0x4027 #define SO_BUSY_POLL 0x4027
#define SO_MAX_PACING_RATE 0x4048 #define SO_MAX_PACING_RATE 0x4028
#endif /* _UAPI_ASM_SOCKET_H */ #endif /* _UAPI_ASM_SOCKET_H */

7
arch/powerpc/net/bpf_jit_comp.c
View File

@@ -223,10 +223,11 @@ static int bpf_jit_build_body(struct sk_filter *fp, u32 *image,
} }
PPC_DIVWU(r_A, r_A, r_X); PPC_DIVWU(r_A, r_A, r_X);
break; break;
case BPF_S_ALU_DIV_K: /* A = reciprocal_divide(A, K); */ case BPF_S_ALU_DIV_K: /* A /= K */
if (K == 1)
break;
PPC_LI32(r_scratch1, K); PPC_LI32(r_scratch1, K);
/* Top 32 bits of 64bit result -> A */ PPC_DIVWU(r_A, r_A, r_scratch1);
PPC_MULHWU(r_A, r_A, r_scratch1);
break; break;
case BPF_S_ALU_AND_X: case BPF_S_ALU_AND_X:
ctx->seen |= SEEN_XREG; ctx->seen |= SEEN_XREG;

29
arch/s390/net/bpf_jit_comp.c
View File

@@ -368,14 +368,16 @@ static int bpf_jit_insn(struct bpf_jit *jit, struct sock_filter *filter,
EMIT4_PCREL(0xa7840000, (jit->ret0_ip - jit->prg)); EMIT4_PCREL(0xa7840000, (jit->ret0_ip - jit->prg));
/* lhi %r4,0 */ /* lhi %r4,0 */
EMIT4(0xa7480000); EMIT4(0xa7480000);
/* dr %r4,%r12 */ /* dlr %r4,%r12 */
EMIT2(0x1d4c); EMIT4(0xb997004c);
break; break;
case BPF_S_ALU_DIV_K: /* A = reciprocal_divide(A, K) */ case BPF_S_ALU_DIV_K: /* A /= K */
/* m %r4,<d(K)>(%r13) */ if (K == 1)
EMIT4_DISP(0x5c40d000, EMIT_CONST(K)); break;
/* lr %r5,%r4 */ /* lhi %r4,0 */
EMIT2(0x1854); EMIT4(0xa7480000);
/* dl %r4,<d(K)>(%r13) */
EMIT6_DISP(0xe340d000, 0x0097, EMIT_CONST(K));
break; break;
case BPF_S_ALU_MOD_X: /* A %= X */ case BPF_S_ALU_MOD_X: /* A %= X */
jit->seen |= SEEN_XREG | SEEN_RET0; jit->seen |= SEEN_XREG | SEEN_RET0;
@@ -385,16 +387,21 @@ static int bpf_jit_insn(struct bpf_jit *jit, struct sock_filter *filter,
EMIT4_PCREL(0xa7840000, (jit->ret0_ip - jit->prg)); EMIT4_PCREL(0xa7840000, (jit->ret0_ip - jit->prg));
/* lhi %r4,0 */ /* lhi %r4,0 */
EMIT4(0xa7480000); EMIT4(0xa7480000);
/* dr %r4,%r12 */ /* dlr %r4,%r12 */
EMIT2(0x1d4c); EMIT4(0xb997004c);
/* lr %r5,%r4 */ /* lr %r5,%r4 */
EMIT2(0x1854); EMIT2(0x1854);
break; break;
case BPF_S_ALU_MOD_K: /* A %= K */ case BPF_S_ALU_MOD_K: /* A %= K */
if (K == 1) {
/* lhi %r5,0 */
EMIT4(0xa7580000);
break;
}
/* lhi %r4,0 */ /* lhi %r4,0 */
EMIT4(0xa7480000); EMIT4(0xa7480000);
/* d %r4,<d(K)>(%r13) */ /* dl %r4,<d(K)>(%r13) */
EMIT4_DISP(0x5d40d000, EMIT_CONST(K)); EMIT6_DISP(0xe340d000, 0x0097, EMIT_CONST(K));
/* lr %r5,%r4 */ /* lr %r5,%r4 */
EMIT2(0x1854); EMIT2(0x1854);
break; break;

17
arch/sparc/net/bpf_jit_comp.c
View File

@@ -497,9 +497,20 @@ void bpf_jit_compile(struct sk_filter *fp)
case BPF_S_ALU_MUL_K: /* A *= K */ case BPF_S_ALU_MUL_K: /* A *= K */
emit_alu_K(MUL, K); emit_alu_K(MUL, K);
break; break;
case BPF_S_ALU_DIV_K: /* A /= K */ case BPF_S_ALU_DIV_K: /* A /= K with K != 0*/
emit_alu_K(MUL, K); if (K == 1)
emit_read_y(r_A); break;
emit_write_y(G0);
#ifdef CONFIG_SPARC32
/* The Sparc v8 architecture requires
* three instructions between a %y
* register write and the first use.
*/
emit_nop();
emit_nop();
emit_nop();
#endif
emit_alu_K(DIV, K);
break; break;
case BPF_S_ALU_DIV_X: /* A /= X; */ case BPF_S_ALU_DIV_X: /* A /= X; */
emit_cmpi(r_X, 0); emit_cmpi(r_X, 0);

53
arch/x86/kernel/cpu/perf_event_amd_ibs.c
View File

@@ -10,6 +10,7 @@
#include <linux/module.h> #include <linux/module.h>
#include <linux/pci.h> #include <linux/pci.h>
#include <linux/ptrace.h> #include <linux/ptrace.h>
#include <linux/syscore_ops.h>
#include <asm/apic.h> #include <asm/apic.h>
@@ -816,6 +817,18 @@ out:
return ret; return ret;
} }
static void ibs_eilvt_setup(void)
{
/*
* Force LVT offset assignment for family 10h: The offsets are
* not assigned by the BIOS for this family, so the OS is
* responsible for doing it. If the OS assignment fails, fall
* back to BIOS settings and try to setup this.
*/
if (boot_cpu_data.x86 == 0x10)
force_ibs_eilvt_setup();
}
static inline int get_ibs_lvt_offset(void) static inline int get_ibs_lvt_offset(void)
{ {
u64 val; u64 val;
@@ -851,6 +864,36 @@ static void clear_APIC_ibs(void *dummy)
setup_APIC_eilvt(offset, 0, APIC_EILVT_MSG_FIX, 1); setup_APIC_eilvt(offset, 0, APIC_EILVT_MSG_FIX, 1);
} }
#ifdef CONFIG_PM
static int perf_ibs_suspend(void)
{
clear_APIC_ibs(NULL);
return 0;
}
static void perf_ibs_resume(void)
{
ibs_eilvt_setup();
setup_APIC_ibs(NULL);
}
static struct syscore_ops perf_ibs_syscore_ops = {
.resume = perf_ibs_resume,
.suspend = perf_ibs_suspend,
};
static void perf_ibs_pm_init(void)
{
register_syscore_ops(&perf_ibs_syscore_ops);
}
#else
static inline void perf_ibs_pm_init(void) { }
#endif
static int static int
perf_ibs_cpu_notifier(struct notifier_block *self, unsigned long action, void *hcpu) perf_ibs_cpu_notifier(struct notifier_block *self, unsigned long action, void *hcpu)
{ {
@@ -877,18 +920,12 @@ static __init int amd_ibs_init(void)
if (!caps) if (!caps)
return -ENODEV; /* ibs not supported by the cpu */ return -ENODEV; /* ibs not supported by the cpu */
/* ibs_eilvt_setup();
* Force LVT offset assignment for family 10h: The offsets are
* not assigned by the BIOS for this family, so the OS is
* responsible for doing it. If the OS assignment fails, fall
* back to BIOS settings and try to setup this.
*/
if (boot_cpu_data.x86 == 0x10)
force_ibs_eilvt_setup();
if (!ibs_eilvt_valid()) if (!ibs_eilvt_valid())
goto out; goto out;
perf_ibs_pm_init();
get_online_cpus(); get_online_cpus();
ibs_caps = caps; ibs_caps = caps;
/* make ibs_caps visible to other cpus: */ /* make ibs_caps visible to other cpus: */

2
arch/x86/kvm/lapic.c
View File

@@ -1355,7 +1355,7 @@ void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
vcpu->arch.apic_base = value; vcpu->arch.apic_base = value;
/* update jump label if enable bit changes */ /* update jump label if enable bit changes */
if ((vcpu->arch.apic_base ^ value) & MSR_IA32_APICBASE_ENABLE) { if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE) {
if (value & MSR_IA32_APICBASE_ENABLE) if (value & MSR_IA32_APICBASE_ENABLE)
static_key_slow_dec_deferred(&apic_hw_disabled); static_key_slow_dec_deferred(&apic_hw_disabled);
else else

18
arch/x86/mm/fault.c
View File

@@ -641,6 +641,20 @@ no_context(struct pt_regs *regs, unsigned long error_code,
/* Are we prepared to handle this kernel fault? */ /* Are we prepared to handle this kernel fault? */
if (fixup_exception(regs)) { if (fixup_exception(regs)) {
/*
* Any interrupt that takes a fault gets the fixup. This makes
* the below recursive fault logic only apply to a faults from
* task context.
*/
if (in_interrupt())
return;
/*
* Per the above we're !in_interrupt(), aka. task context.
*
* In this case we need to make sure we're not recursively
* faulting through the emulate_vsyscall() logic.
*/
if (current_thread_info()->sig_on_uaccess_error && signal) { if (current_thread_info()->sig_on_uaccess_error && signal) {
tsk->thread.trap_nr = X86_TRAP_PF; tsk->thread.trap_nr = X86_TRAP_PF;
tsk->thread.error_code = error_code | PF_USER; tsk->thread.error_code = error_code | PF_USER;
@@ -649,6 +663,10 @@ no_context(struct pt_regs *regs, unsigned long error_code,
/* XXX: hwpoison faults will set the wrong code. */ /* XXX: hwpoison faults will set the wrong code. */
force_sig_info_fault(signal, si_code, address, tsk, 0); force_sig_info_fault(signal, si_code, address, tsk, 0);
} }
/*
* Barring that, we can do the fixup and be happy.
*/
return; return;
} }

14
arch/x86/net/bpf_jit_comp.c
View File

@@ -359,15 +359,21 @@ void bpf_jit_compile(struct sk_filter *fp)
EMIT2(0x89, 0xd0); /* mov %edx,%eax */ EMIT2(0x89, 0xd0); /* mov %edx,%eax */
break; break;
case BPF_S_ALU_MOD_K: /* A %= K; */ case BPF_S_ALU_MOD_K: /* A %= K; */
if (K == 1) {
CLEAR_A();
break;
}
EMIT2(0x31, 0xd2); /* xor %edx,%edx */ EMIT2(0x31, 0xd2); /* xor %edx,%edx */
EMIT1(0xb9);EMIT(K, 4); /* mov imm32,%ecx */ EMIT1(0xb9);EMIT(K, 4); /* mov imm32,%ecx */
EMIT2(0xf7, 0xf1); /* div %ecx */ EMIT2(0xf7, 0xf1); /* div %ecx */
EMIT2(0x89, 0xd0); /* mov %edx,%eax */ EMIT2(0x89, 0xd0); /* mov %edx,%eax */
break; break;
case BPF_S_ALU_DIV_K: /* A = reciprocal_divide(A, K); */ case BPF_S_ALU_DIV_K: /* A /= K */
EMIT3(0x48, 0x69, 0xc0); /* imul imm32,%rax,%rax */ if (K == 1)
EMIT(K, 4); break;
EMIT4(0x48, 0xc1, 0xe8, 0x20); /* shr $0x20,%rax */ EMIT2(0x31, 0xd2); /* xor %edx,%edx */
EMIT1(0xb9);EMIT(K, 4); /* mov imm32,%ecx */
EMIT2(0xf7, 0xf1); /* div %ecx */
break; break;
case BPF_S_ALU_AND_X: case BPF_S_ALU_AND_X:
seen |= SEEN_XREG; seen |= SEEN_XREG;

8
arch/x86/vdso/vclock_gettime.c
View File

@@ -178,7 +178,7 @@ notrace static int __always_inline do_realtime(struct timespec *ts)
ts->tv_nsec = 0; ts->tv_nsec = 0;
do { do {
seq = read_seqcount_begin_no_lockdep(&gtod->seq); seq = raw_read_seqcount_begin(&gtod->seq);
mode = gtod->clock.vclock_mode; mode = gtod->clock.vclock_mode;
ts->tv_sec = gtod->wall_time_sec; ts->tv_sec = gtod->wall_time_sec;
ns = gtod->wall_time_snsec; ns = gtod->wall_time_snsec;
@@ -198,7 +198,7 @@ notrace static int do_monotonic(struct timespec *ts)
ts->tv_nsec = 0; ts->tv_nsec = 0;
do { do {
seq = read_seqcount_begin_no_lockdep(&gtod->seq); seq = raw_read_seqcount_begin(&gtod->seq);
mode = gtod->clock.vclock_mode; mode = gtod->clock.vclock_mode;
ts->tv_sec = gtod->monotonic_time_sec; ts->tv_sec = gtod->monotonic_time_sec;
ns = gtod->monotonic_time_snsec; ns = gtod->monotonic_time_snsec;
@@ -214,7 +214,7 @@ notrace static int do_realtime_coarse(struct timespec *ts)
{ {
unsigned long seq; unsigned long seq;
do { do {
seq = read_seqcount_begin_no_lockdep(&gtod->seq); seq = raw_read_seqcount_begin(&gtod->seq);
ts->tv_sec = gtod->wall_time_coarse.tv_sec; ts->tv_sec = gtod->wall_time_coarse.tv_sec;
ts->tv_nsec = gtod->wall_time_coarse.tv_nsec; ts->tv_nsec = gtod->wall_time_coarse.tv_nsec;
} while (unlikely(read_seqcount_retry(&gtod->seq, seq))); } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
@@ -225,7 +225,7 @@ notrace static int do_monotonic_coarse(struct timespec *ts)
{ {
unsigned long seq; unsigned long seq;
do { do {
seq = read_seqcount_begin_no_lockdep(&gtod->seq); seq = raw_read_seqcount_begin(&gtod->seq);
ts->tv_sec = gtod->monotonic_time_coarse.tv_sec; ts->tv_sec = gtod->monotonic_time_coarse.tv_sec;
ts->tv_nsec = gtod->monotonic_time_coarse.tv_nsec; ts->tv_nsec = gtod->monotonic_time_coarse.tv_nsec;
} while (unlikely(read_seqcount_retry(&gtod->seq, seq))); } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));

1
drivers/acpi/acpi_lpss.c
View File

@@ -162,7 +162,6 @@ static const struct acpi_device_id acpi_lpss_device_ids[] = {
{ "80860F14", (unsigned long)&byt_sdio_dev_desc }, { "80860F14", (unsigned long)&byt_sdio_dev_desc },
{ "80860F41", (unsigned long)&byt_i2c_dev_desc }, { "80860F41", (unsigned long)&byt_i2c_dev_desc },
{ "INT33B2", }, { "INT33B2", },
{ "INT33FC", },
{ "INT3430", (unsigned long)&lpt_dev_desc }, { "INT3430", (unsigned long)&lpt_dev_desc },
{ "INT3431", (unsigned long)&lpt_dev_desc }, { "INT3431", (unsigned long)&lpt_dev_desc },

21
drivers/clocksource/cadence_ttc_timer.c
View File

@@ -67,11 +67,13 @@
* struct ttc_timer - This definition defines local timer structure * struct ttc_timer - This definition defines local timer structure
* *
* @base_addr: Base address of timer * @base_addr: Base address of timer
* @freq: Timer input clock frequency
* @clk: Associated clock source * @clk: Associated clock source
* @clk_rate_change_nb Notifier block for clock rate changes * @clk_rate_change_nb Notifier block for clock rate changes
*/ */
struct ttc_timer { struct ttc_timer {
void __iomem *base_addr; void __iomem *base_addr;
unsigned long freq;
struct clk *clk; struct clk *clk;
struct notifier_block clk_rate_change_nb; struct notifier_block clk_rate_change_nb;
}; };
@@ -196,9 +198,8 @@ static void ttc_set_mode(enum clock_event_mode mode,
switch (mode) { switch (mode) {
case CLOCK_EVT_MODE_PERIODIC: case CLOCK_EVT_MODE_PERIODIC:
ttc_set_interval(timer, ttc_set_interval(timer, DIV_ROUND_CLOSEST(ttce->ttc.freq,
DIV_ROUND_CLOSEST(clk_get_rate(ttce->ttc.clk), PRESCALE * HZ));
PRESCALE * HZ));
break; break;
case CLOCK_EVT_MODE_ONESHOT: case CLOCK_EVT_MODE_ONESHOT:
case CLOCK_EVT_MODE_UNUSED: case CLOCK_EVT_MODE_UNUSED:
@@ -273,6 +274,8 @@ static void __init ttc_setup_clocksource(struct clk *clk, void __iomem *base)
return; return;
} }
ttccs->ttc.freq = clk_get_rate(ttccs->ttc.clk);
ttccs->ttc.clk_rate_change_nb.notifier_call = ttccs->ttc.clk_rate_change_nb.notifier_call =
ttc_rate_change_clocksource_cb; ttc_rate_change_clocksource_cb;
ttccs->ttc.clk_rate_change_nb.next = NULL; ttccs->ttc.clk_rate_change_nb.next = NULL;
@@ -298,16 +301,14 @@ static void __init ttc_setup_clocksource(struct clk *clk, void __iomem *base)
__raw_writel(CNT_CNTRL_RESET, __raw_writel(CNT_CNTRL_RESET,
ttccs->ttc.base_addr + TTC_CNT_CNTRL_OFFSET); ttccs->ttc.base_addr + TTC_CNT_CNTRL_OFFSET);
err = clocksource_register_hz(&ttccs->cs, err = clocksource_register_hz(&ttccs->cs, ttccs->ttc.freq / PRESCALE);
clk_get_rate(ttccs->ttc.clk) / PRESCALE);
if (WARN_ON(err)) { if (WARN_ON(err)) {
kfree(ttccs); kfree(ttccs);
return; return;
} }
ttc_sched_clock_val_reg = base + TTC_COUNT_VAL_OFFSET; ttc_sched_clock_val_reg = base + TTC_COUNT_VAL_OFFSET;
setup_sched_clock(ttc_sched_clock_read, 16, setup_sched_clock(ttc_sched_clock_read, 16, ttccs->ttc.freq / PRESCALE);
clk_get_rate(ttccs->ttc.clk) / PRESCALE);
} }
static int ttc_rate_change_clockevent_cb(struct notifier_block *nb, static int ttc_rate_change_clockevent_cb(struct notifier_block *nb,
@@ -334,6 +335,9 @@ static int ttc_rate_change_clockevent_cb(struct notifier_block *nb,
ndata->new_rate / PRESCALE); ndata->new_rate / PRESCALE);
local_irq_restore(flags); local_irq_restore(flags);
/* update cached frequency */
ttc->freq = ndata->new_rate;
/* fall through */ /* fall through */
} }
case PRE_RATE_CHANGE: case PRE_RATE_CHANGE:
@@ -367,6 +371,7 @@ static void __init ttc_setup_clockevent(struct clk *clk,
if (clk_notifier_register(ttcce->ttc.clk, if (clk_notifier_register(ttcce->ttc.clk,
&ttcce->ttc.clk_rate_change_nb)) &ttcce->ttc.clk_rate_change_nb))
pr_warn("Unable to register clock notifier.\n"); pr_warn("Unable to register clock notifier.\n");
ttcce->ttc.freq = clk_get_rate(ttcce->ttc.clk);
ttcce->ttc.base_addr = base; ttcce->ttc.base_addr = base;
ttcce->ce.name = "ttc_clockevent"; ttcce->ce.name = "ttc_clockevent";
@@ -396,7 +401,7 @@ static void __init ttc_setup_clockevent(struct clk *clk,
} }
clockevents_config_and_register(&ttcce->ce, clockevents_config_and_register(&ttcce->ce,
clk_get_rate(ttcce->ttc.clk) / PRESCALE, 1, 0xfffe); ttcce->ttc.freq / PRESCALE, 1, 0xfffe);
} }
/** /**

1
drivers/gpu/drm/armada/Kconfig
View File

@@ -5,6 +5,7 @@ config DRM_ARMADA
select FB_CFB_COPYAREA select FB_CFB_COPYAREA
select FB_CFB_IMAGEBLIT select FB_CFB_IMAGEBLIT
select DRM_KMS_HELPER select DRM_KMS_HELPER
select DRM_KMS_FB_HELPER
help help
Support the "LCD" controllers found on the Marvell Armada 510 Support the "LCD" controllers found on the Marvell Armada 510
devices. There are two controllers on the device, each controller devices. There are two controllers on the device, each controller

2
drivers/gpu/drm/ast/ast_fb.c
View File

@@ -65,7 +65,7 @@ static void ast_dirty_update(struct ast_fbdev *afbdev,
* then the BO is being moved and we should * then the BO is being moved and we should
* store up the damage until later. * store up the damage until later.
*/ */
if (!in_interrupt()) if (!drm_can_sleep())
ret = ast_bo_reserve(bo, true); ret = ast_bo_reserve(bo, true);
if (ret) { if (ret) {
if (ret != -EBUSY) if (ret != -EBUSY)

2
drivers/gpu/drm/cirrus/cirrus_fbdev.c
View File

@@ -39,7 +39,7 @@ static void cirrus_dirty_update(struct cirrus_fbdev *afbdev,
* then the BO is being moved and we should * then the BO is being moved and we should
* store up the damage until later. * store up the damage until later.
*/ */
if (!in_interrupt()) if (!drm_can_sleep())
ret = cirrus_bo_reserve(bo, true); ret = cirrus_bo_reserve(bo, true);
if (ret) { if (ret) {
if (ret != -EBUSY) if (ret != -EBUSY)

4
drivers/gpu/drm/cirrus/cirrus_mode.c
View File

@@ -273,8 +273,8 @@ static int cirrus_crtc_mode_set(struct drm_crtc *crtc,
sr07 |= 0x11; sr07 |= 0x11;
break; break;
case 16: case 16:
sr07 |= 0xc1; sr07 |= 0x17;
hdr = 0xc0; hdr = 0xc1;
break; break;
case 24: case 24:
sr07 |= 0x15; sr07 |= 0x15;

23
drivers/gpu/drm/drm_crtc.c
View File

@@ -674,6 +674,29 @@ void drm_crtc_cleanup(struct drm_crtc *crtc)
} }
EXPORT_SYMBOL(drm_crtc_cleanup); EXPORT_SYMBOL(drm_crtc_cleanup);
/**
* drm_crtc_index - find the index of a registered CRTC
* @crtc: CRTC to find index for
*
* Given a registered CRTC, return the index of that CRTC within a DRM
* device's list of CRTCs.
*/
unsigned int drm_crtc_index(struct drm_crtc *crtc)
{
unsigned int index = 0;
struct drm_crtc *tmp;
list_for_each_entry(tmp, &crtc->dev->mode_config.crtc_list, head) {
if (tmp == crtc)
return index;
index++;
}
BUG();
}
EXPORT_SYMBOL(drm_crtc_index);
/** /**
* drm_mode_probed_add - add a mode to a connector's probed mode list * drm_mode_probed_add - add a mode to a connector's probed mode list
* @connector: connector the new mode * @connector: connector the new mode

29
drivers/gpu/drm/drm_crtc_helper.c
View File

@@ -324,35 +324,6 @@ void drm_helper_disable_unused_functions(struct drm_device *dev)
} }
EXPORT_SYMBOL(drm_helper_disable_unused_functions); EXPORT_SYMBOL(drm_helper_disable_unused_functions);
/**
* drm_encoder_crtc_ok - can a given crtc drive a given encoder?
* @encoder: encoder to test
* @crtc: crtc to test
*
* Return false if @encoder can't be driven by @crtc, true otherwise.
*/
static bool drm_encoder_crtc_ok(struct drm_encoder *encoder,
struct drm_crtc *crtc)
{
struct drm_device *dev;
struct drm_crtc *tmp;
int crtc_mask = 1;
WARN(!crtc, "checking null crtc?\n");
dev = crtc->dev;
list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
if (tmp == crtc)
break;
crtc_mask <<= 1;
}
if (encoder->possible_crtcs & crtc_mask)
return true;
return false;
}
/* /*
* Check the CRTC we're going to map each output to vs. its current * Check the CRTC we're going to map each output to vs. its current
* CRTC. If they don't match, we have to disable the output and the CRTC * CRTC. If they don't match, we have to disable the output and the CRTC

2
drivers/gpu/drm/gma500/cdv_intel_dp.c
View File

@@ -678,7 +678,7 @@ cdv_intel_dp_i2c_init(struct gma_connector *connector,
return ret; return ret;
} }
void cdv_intel_fixed_panel_mode(struct drm_display_mode *fixed_mode, static void cdv_intel_fixed_panel_mode(struct drm_display_mode *fixed_mode,
struct drm_display_mode *adjusted_mode) struct drm_display_mode *adjusted_mode)
{ {
adjusted_mode->hdisplay = fixed_mode->hdisplay; adjusted_mode->hdisplay = fixed_mode->hdisplay;

12
drivers/gpu/drm/gma500/gma_display.c
View File

@@ -349,6 +349,7 @@ int gma_crtc_cursor_set(struct drm_crtc *crtc,
/* If we didn't get a handle then turn the cursor off */ /* If we didn't get a handle then turn the cursor off */
if (!handle) { if (!handle) {
temp = CURSOR_MODE_DISABLE; temp = CURSOR_MODE_DISABLE;
mutex_lock(&dev->struct_mutex);
if (gma_power_begin(dev, false)) { if (gma_power_begin(dev, false)) {
REG_WRITE(control, temp); REG_WRITE(control, temp);
@@ -365,6 +366,7 @@ int gma_crtc_cursor_set(struct drm_crtc *crtc,
gma_crtc->cursor_obj = NULL; gma_crtc->cursor_obj = NULL;
} }
mutex_unlock(&dev->struct_mutex);
return 0; return 0;
} }
@@ -374,9 +376,12 @@ int gma_crtc_cursor_set(struct drm_crtc *crtc,
return -EINVAL; return -EINVAL;
} }
mutex_lock(&dev->struct_mutex);
obj = drm_gem_object_lookup(dev, file_priv, handle); obj = drm_gem_object_lookup(dev, file_priv, handle);
if (!obj) if (!obj) {
return -ENOENT; ret = -ENOENT;
goto unlock;
}
if (obj->size < width * height * 4) { if (obj->size < width * height * 4) {
dev_dbg(dev->dev, "Buffer is too small\n"); dev_dbg(dev->dev, "Buffer is too small\n");
@@ -440,10 +445,13 @@ int gma_crtc_cursor_set(struct drm_crtc *crtc,
} }
gma_crtc->cursor_obj = obj; gma_crtc->cursor_obj = obj;
unlock:
mutex_unlock(&dev->struct_mutex);
return ret; return ret;
unref_cursor: unref_cursor:
drm_gem_object_unreference(obj); drm_gem_object_unreference(obj);
mutex_unlock(&dev->struct_mutex);
return ret; return ret;
} }

1
drivers/gpu/drm/i915/i915_dma.c
View File

@@ -1685,6 +1685,7 @@ out_gem_unload:
intel_teardown_gmbus(dev); intel_teardown_gmbus(dev);
intel_teardown_mchbar(dev); intel_teardown_mchbar(dev);
pm_qos_remove_request(&dev_priv->pm_qos);
destroy_workqueue(dev_priv->wq); destroy_workqueue(dev_priv->wq);
out_mtrrfree: out_mtrrfree:
arch_phys_wc_del(dev_priv->gtt.mtrr); arch_phys_wc_del(dev_priv->gtt.mtrr);

1
drivers/gpu/drm/i915/i915_drv.h
View File

@@ -331,6 +331,7 @@ struct drm_i915_error_state {
u64 fence[I915_MAX_NUM_FENCES]; u64 fence[I915_MAX_NUM_FENCES];
struct timeval time; struct timeval time;
struct drm_i915_error_ring { struct drm_i915_error_ring {
bool valid;
struct drm_i915_error_object { struct drm_i915_error_object {
int page_count; int page_count;
u32 gtt_offset; u32 gtt_offset;

2
drivers/gpu/drm/i915/i915_gem_stolen.c
View File

@@ -250,7 +250,7 @@ i915_pages_create_for_stolen(struct drm_device *dev,
} }
sg = st->sgl; sg = st->sgl;
sg->offset = offset; sg->offset = 0;
sg->length = size; sg->length = size;
sg_dma_address(sg) = (dma_addr_t)dev_priv->mm.stolen_base + offset; sg_dma_address(sg) = (dma_addr_t)dev_priv->mm.stolen_base + offset;

22
drivers/gpu/drm/i915/i915_gpu_error.c
View File

@@ -239,6 +239,9 @@ static void i915_ring_error_state(struct drm_i915_error_state_buf *m,
unsigned ring) unsigned ring)
{ {
BUG_ON(ring >= I915_NUM_RINGS); /* shut up confused gcc */ BUG_ON(ring >= I915_NUM_RINGS); /* shut up confused gcc */
if (!error->ring[ring].valid)
return;
err_printf(m, "%s command stream:\n", ring_str(ring)); err_printf(m, "%s command stream:\n", ring_str(ring));
err_printf(m, " HEAD: 0x%08x\n", error->head[ring]); err_printf(m, " HEAD: 0x%08x\n", error->head[ring]);
err_printf(m, " TAIL: 0x%08x\n", error->tail[ring]); err_printf(m, " TAIL: 0x%08x\n", error->tail[ring]);
@@ -294,7 +297,6 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
struct drm_device *dev = error_priv->dev; struct drm_device *dev = error_priv->dev;
drm_i915_private_t *dev_priv = dev->dev_private; drm_i915_private_t *dev_priv = dev->dev_private;
struct drm_i915_error_state *error = error_priv->error; struct drm_i915_error_state *error = error_priv->error;
struct intel_ring_buffer *ring;
int i, j, page, offset, elt; int i, j, page, offset, elt;
if (!error) { if (!error) {
@@ -329,7 +331,7 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
if (INTEL_INFO(dev)->gen == 7) if (INTEL_INFO(dev)->gen == 7)
err_printf(m, "ERR_INT: 0x%08x\n", error->err_int); err_printf(m, "ERR_INT: 0x%08x\n", error->err_int);
for_each_ring(ring, dev_priv, i) for (i = 0; i < ARRAY_SIZE(error->ring); i++)
i915_ring_error_state(m, dev, error, i); i915_ring_error_state(m, dev, error, i);
if (error->active_bo) if (error->active_bo)
@@ -402,8 +404,7 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
} }
} }
obj = error->ring[i].ctx; if ((obj = error->ring[i].ctx)) {
if (obj) {
err_printf(m, "%s --- HW Context = 0x%08x\n", err_printf(m, "%s --- HW Context = 0x%08x\n",
dev_priv->ring[i].name, dev_priv->ring[i].name,
obj->gtt_offset); obj->gtt_offset);
@@ -718,7 +719,8 @@ i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
return NULL; return NULL;
obj = ring->scratch.obj; obj = ring->scratch.obj;
if (acthd >= i915_gem_obj_ggtt_offset(obj) && if (obj != NULL &&
acthd >= i915_gem_obj_ggtt_offset(obj) &&
acthd < i915_gem_obj_ggtt_offset(obj) + obj->base.size) acthd < i915_gem_obj_ggtt_offset(obj) + obj->base.size)
return i915_error_ggtt_object_create(dev_priv, obj); return i915_error_ggtt_object_create(dev_priv, obj);
} }
@@ -863,11 +865,17 @@ static void i915_gem_record_rings(struct drm_device *dev,
struct drm_i915_error_state *error) struct drm_i915_error_state *error)
{ {
struct drm_i915_private *dev_priv = dev->dev_private; struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_ring_buffer *ring;
struct drm_i915_gem_request *request; struct drm_i915_gem_request *request;
int i, count; int i, count;
for_each_ring(ring, dev_priv, i) { for (i = 0; i < I915_NUM_RINGS; i++) {
struct intel_ring_buffer *ring = &dev_priv->ring[i];
if (ring->dev == NULL)
continue;
error->ring[i].valid = true;
i915_record_ring_state(dev, error, ring); i915_record_ring_state(dev, error, ring);
error->ring[i].batchbuffer = error->ring[i].batchbuffer =

26
drivers/gpu/drm/i915/intel_display.c
View File

@@ -8753,28 +8753,6 @@ static struct drm_crtc_helper_funcs intel_helper_funcs = {
.load_lut = intel_crtc_load_lut, .load_lut = intel_crtc_load_lut,
}; };
static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
struct drm_crtc *crtc)
{
struct drm_device *dev;
struct drm_crtc *tmp;
int crtc_mask = 1;
WARN(!crtc, "checking null crtc?\n");
dev = crtc->dev;
list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
if (tmp == crtc)
break;
crtc_mask <<= 1;
}
if (encoder->possible_crtcs & crtc_mask)
return true;
return false;
}
/** /**
* intel_modeset_update_staged_output_state * intel_modeset_update_staged_output_state
* *
@@ -9987,8 +9965,8 @@ intel_modeset_stage_output_state(struct drm_device *dev,
} }
/* Make sure the new CRTC will work with the encoder */ /* Make sure the new CRTC will work with the encoder */
if (!intel_encoder_crtc_ok(&connector->new_encoder->base, if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
new_crtc)) { new_crtc)) {
return -EINVAL; return -EINVAL;
} }
connector->encoder->new_crtc = to_intel_crtc(new_crtc); connector->encoder->new_crtc = to_intel_crtc(new_crtc);

9
drivers/gpu/drm/mgag200/mgag200_fb.c
View File

@@ -41,7 +41,7 @@ static void mga_dirty_update(struct mga_fbdev *mfbdev,
* then the BO is being moved and we should * then the BO is being moved and we should
* store up the damage until later. * store up the damage until later.
*/ */
if (!in_interrupt()) if (!drm_can_sleep())
ret = mgag200_bo_reserve(bo, true); ret = mgag200_bo_reserve(bo, true);
if (ret) { if (ret) {
if (ret != -EBUSY) if (ret != -EBUSY)
@@ -282,6 +282,11 @@ int mgag200_fbdev_init(struct mga_device *mdev)
{ {
struct mga_fbdev *mfbdev; struct mga_fbdev *mfbdev;
int ret; int ret;
int bpp_sel = 32;
/* prefer 16bpp on low end gpus with limited VRAM */
if (IS_G200_SE(mdev) && mdev->mc.vram_size < (2048*1024))
bpp_sel = 16;
mfbdev = devm_kzalloc(mdev->dev->dev, sizeof(struct mga_fbdev), GFP_KERNEL); mfbdev = devm_kzalloc(mdev->dev->dev, sizeof(struct mga_fbdev), GFP_KERNEL);
if (!mfbdev) if (!mfbdev)
@@ -301,7 +306,7 @@ int mgag200_fbdev_init(struct mga_device *mdev)
/* disable all the possible outputs/crtcs before entering KMS mode */ /* disable all the possible outputs/crtcs before entering KMS mode */
drm_helper_disable_unused_functions(mdev->dev); drm_helper_disable_unused_functions(mdev->dev);
drm_fb_helper_initial_config(&mfbdev->helper, 32); drm_fb_helper_initial_config(&mfbdev->helper, bpp_sel);
return 0; return 0;
} }

5
drivers/gpu/drm/mgag200/mgag200_main.c
View File

@@ -217,7 +217,10 @@ int mgag200_driver_load(struct drm_device *dev, unsigned long flags)
drm_mode_config_init(dev); drm_mode_config_init(dev);
dev->mode_config.funcs = (void *)&mga_mode_funcs; dev->mode_config.funcs = (void *)&mga_mode_funcs;
dev->mode_config.preferred_depth = 24; if (IS_G200_SE(mdev) && mdev->mc.vram_size < (2048*1024))
dev->mode_config.preferred_depth = 16;
else
dev->mode_config.preferred_depth = 24;
dev->mode_config.prefer_shadow = 1; dev->mode_config.prefer_shadow = 1;
r = mgag200_modeset_init(mdev); r = mgag200_modeset_init(mdev);

7
drivers/gpu/drm/nouveau/Makefile
View File

@@ -41,6 +41,7 @@ nouveau-y += core/subdev/bios/init.o
nouveau-y += core/subdev/bios/mxm.o nouveau-y += core/subdev/bios/mxm.o
nouveau-y += core/subdev/bios/perf.o nouveau-y += core/subdev/bios/perf.o
nouveau-y += core/subdev/bios/pll.o nouveau-y += core/subdev/bios/pll.o
nouveau-y += core/subdev/bios/ramcfg.o
nouveau-y += core/subdev/bios/rammap.o nouveau-y += core/subdev/bios/rammap.o
nouveau-y += core/subdev/bios/timing.o nouveau-y += core/subdev/bios/timing.o
nouveau-y += core/subdev/bios/therm.o nouveau-y += core/subdev/bios/therm.o
@@ -71,7 +72,10 @@ nouveau-y += core/subdev/devinit/nv10.o
nouveau-y += core/subdev/devinit/nv1a.o nouveau-y += core/subdev/devinit/nv1a.o
nouveau-y += core/subdev/devinit/nv20.o nouveau-y += core/subdev/devinit/nv20.o
nouveau-y += core/subdev/devinit/nv50.o nouveau-y += core/subdev/devinit/nv50.o
nouveau-y += core/subdev/devinit/nv84.o
nouveau-y += core/subdev/devinit/nv98.o
nouveau-y += core/subdev/devinit/nva3.o nouveau-y += core/subdev/devinit/nva3.o
nouveau-y += core/subdev/devinit/nvaf.o
nouveau-y += core/subdev/devinit/nvc0.o nouveau-y += core/subdev/devinit/nvc0.o
nouveau-y += core/subdev/fb/base.o nouveau-y += core/subdev/fb/base.o
nouveau-y += core/subdev/fb/nv04.o nouveau-y += core/subdev/fb/nv04.o
@@ -232,6 +236,7 @@ nouveau-y += core/engine/fifo/nv50.o
nouveau-y += core/engine/fifo/nv84.o nouveau-y += core/engine/fifo/nv84.o
nouveau-y += core/engine/fifo/nvc0.o nouveau-y += core/engine/fifo/nvc0.o
nouveau-y += core/engine/fifo/nve0.o nouveau-y += core/engine/fifo/nve0.o
nouveau-y += core/engine/fifo/nv108.o
nouveau-y += core/engine/graph/ctxnv40.o nouveau-y += core/engine/graph/ctxnv40.o
nouveau-y += core/engine/graph/ctxnv50.o nouveau-y += core/engine/graph/ctxnv50.o
nouveau-y += core/engine/graph/ctxnvc0.o nouveau-y += core/engine/graph/ctxnvc0.o
@@ -242,6 +247,7 @@ nouveau-y += core/engine/graph/ctxnvd7.o
nouveau-y += core/engine/graph/ctxnvd9.o nouveau-y += core/engine/graph/ctxnvd9.o
nouveau-y += core/engine/graph/ctxnve4.o nouveau-y += core/engine/graph/ctxnve4.o
nouveau-y += core/engine/graph/ctxnvf0.o nouveau-y += core/engine/graph/ctxnvf0.o
nouveau-y += core/engine/graph/ctxnv108.o
nouveau-y += core/engine/graph/nv04.o nouveau-y += core/engine/graph/nv04.o
nouveau-y += core/engine/graph/nv10.o nouveau-y += core/engine/graph/nv10.o
nouveau-y += core/engine/graph/nv20.o nouveau-y += core/engine/graph/nv20.o
@@ -260,6 +266,7 @@ nouveau-y += core/engine/graph/nvd7.o
nouveau-y += core/engine/graph/nvd9.o nouveau-y += core/engine/graph/nvd9.o
nouveau-y += core/engine/graph/nve4.o nouveau-y += core/engine/graph/nve4.o
nouveau-y += core/engine/graph/nvf0.o nouveau-y += core/engine/graph/nvf0.o
nouveau-y += core/engine/graph/nv108.o
nouveau-y += core/engine/mpeg/nv31.o nouveau-y += core/engine/mpeg/nv31.o
nouveau-y += core/engine/mpeg/nv40.o nouveau-y += core/engine/mpeg/nv40.o
nouveau-y += core/engine/mpeg/nv44.o nouveau-y += core/engine/mpeg/nv44.o

23
drivers/gpu/drm/nouveau/core/core/engine.c
View File

@@ -42,11 +42,24 @@ nouveau_engine_create_(struct nouveau_object *parent,
if (ret) if (ret)
return ret; return ret;
if ( parent && if (parent) {
!nouveau_boolopt(nv_device(parent)->cfgopt, iname, enable)) { struct nouveau_device *device = nv_device(parent);
if (!enable) int engidx = nv_engidx(nv_object(engine));
nv_warn(engine, "disabled, %s=1 to enable\n", iname);
return -ENODEV; if (device->disable_mask & (1ULL << engidx)) {
if (!nouveau_boolopt(device->cfgopt, iname, false)) {
nv_debug(engine, "engine disabled by hw/fw\n");
return -ENODEV;
}
nv_warn(engine, "ignoring hw/fw engine disable\n");
}
if (!nouveau_boolopt(device->cfgopt, iname, enable)) {
if (!enable)
nv_warn(engine, "disabled, %s=1 to enable\n", iname);
return -ENODEV;
}
} }
INIT_LIST_HEAD(&engine->contexts); INIT_LIST_HEAD(&engine->contexts);

6
drivers/gpu/drm/nouveau/core/engine/copy/nvc0.c
View File

@@ -105,9 +105,6 @@ nvc0_copy0_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nvc0_copy_priv *priv; struct nvc0_copy_priv *priv;
int ret; int ret;
if (nv_rd32(parent, 0x022500) & 0x00000100)
return -ENODEV;
ret = nouveau_falcon_create(parent, engine, oclass, 0x104000, true, ret = nouveau_falcon_create(parent, engine, oclass, 0x104000, true,
"PCE0", "copy0", &priv); "PCE0", "copy0", &priv);
*pobject = nv_object(priv); *pobject = nv_object(priv);
@@ -133,9 +130,6 @@ nvc0_copy1_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nvc0_copy_priv *priv; struct nvc0_copy_priv *priv;
int ret; int ret;
if (nv_rd32(parent, 0x022500) & 0x00000200)
return -ENODEV;
ret = nouveau_falcon_create(parent, engine, oclass, 0x105000, true, ret = nouveau_falcon_create(parent, engine, oclass, 0x105000, true,
"PCE1", "copy1", &priv); "PCE1", "copy1", &priv);
*pobject = nv_object(priv); *pobject = nv_object(priv);

6
drivers/gpu/drm/nouveau/core/engine/copy/nve0.c
View File

@@ -88,9 +88,6 @@ nve0_copy0_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nve0_copy_priv *priv; struct nve0_copy_priv *priv;
int ret; int ret;
if (nv_rd32(parent, 0x022500) & 0x00000100)
return -ENODEV;
ret = nouveau_engine_create(parent, engine, oclass, true, ret = nouveau_engine_create(parent, engine, oclass, true,
"PCE0", "copy0", &priv); "PCE0", "copy0", &priv);
*pobject = nv_object(priv); *pobject = nv_object(priv);
@@ -112,9 +109,6 @@ nve0_copy1_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nve0_copy_priv *priv; struct nve0_copy_priv *priv;
int ret; int ret;
if (nv_rd32(parent, 0x022500) & 0x00000200)
return -ENODEV;
ret = nouveau_engine_create(parent, engine, oclass, true, ret = nouveau_engine_create(parent, engine, oclass, true,
"PCE1", "copy1", &priv); "PCE1", "copy1", &priv);
*pobject = nv_object(priv); *pobject = nv_object(priv);

8
drivers/gpu/drm/nouveau/core/engine/device/nv04.c
View File

@@ -49,12 +49,12 @@ nv04_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv04_devinit_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv04_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv04_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv04_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv04_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv04_fifo_oclass;
@@ -67,12 +67,12 @@ nv04_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv05_devinit_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv05_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv04_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv04_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv04_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv04_fifo_oclass;

32
drivers/gpu/drm/nouveau/core/engine/device/nv10.c
View File

@@ -51,12 +51,12 @@ nv10_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv10_devinit_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass;
@@ -68,12 +68,12 @@ nv10_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv10_devinit_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass;
@@ -87,12 +87,12 @@ nv10_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv10_devinit_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass;
@@ -106,12 +106,12 @@ nv10_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv1a_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv1a_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass;
@@ -125,12 +125,12 @@ nv10_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv10_devinit_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass;
@@ -144,12 +144,12 @@ nv10_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv10_devinit_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
@@ -163,12 +163,12 @@ nv10_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv1a_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv1a_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
@@ -182,12 +182,12 @@ nv10_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv10_devinit_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;

16
drivers/gpu/drm/nouveau/core/engine/device/nv20.c
View File

@@ -52,12 +52,12 @@ nv20_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv20_devinit_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv20_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv20_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
@@ -71,12 +71,12 @@ nv20_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv20_devinit_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv25_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv25_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
@@ -90,12 +90,12 @@ nv20_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv20_devinit_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv25_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv25_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
@@ -109,12 +109,12 @@ nv20_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv20_devinit_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv25_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv25_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;

20
drivers/gpu/drm/nouveau/core/engine/device/nv30.c
View File

@@ -52,12 +52,12 @@ nv30_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv20_devinit_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv30_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv30_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
@@ -71,12 +71,12 @@ nv30_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv20_devinit_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv35_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv35_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
@@ -90,12 +90,12 @@ nv30_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv20_devinit_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv30_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv30_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
@@ -110,12 +110,12 @@ nv30_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv20_devinit_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv36_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv36_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
@@ -130,12 +130,12 @@ nv30_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv10_devinit_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;

64
drivers/gpu/drm/nouveau/core/engine/device/nv40.c
View File

@@ -57,12 +57,12 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv40_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv40_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
@@ -80,12 +80,12 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv41_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv41_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass; device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
@@ -103,12 +103,12 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv41_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv41_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass; device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
@@ -126,12 +126,12 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv41_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv41_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass; device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
@@ -149,12 +149,12 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv40_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv40_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
@@ -172,12 +172,12 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv47_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv47_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass; device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
@@ -195,12 +195,12 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv49_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv49_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass; device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
@@ -218,12 +218,12 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv49_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv49_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass; device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
@@ -241,12 +241,12 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv44_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv44_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
@@ -264,12 +264,12 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
@@ -287,12 +287,12 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv44_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv44_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
@@ -310,12 +310,12 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
@@ -333,12 +333,12 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = &nv4e_i2c_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = &nv4e_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv4e_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv4e_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
@@ -356,12 +356,12 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
@@ -379,12 +379,12 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
@@ -402,12 +402,12 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;

56
drivers/gpu/drm/nouveau/core/engine/device/nv50.c
View File

@@ -65,12 +65,12 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_CLOCK ] = nv50_clock_oclass; device->oclass[NVDEV_SUBDEV_CLOCK ] = nv50_clock_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv50_therm_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nv50_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv50_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv50_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv50_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@@ -90,12 +90,12 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass; device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@@ -118,12 +118,12 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass; device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@@ -146,12 +146,12 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass; device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@@ -174,12 +174,12 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass; device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv94_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv94_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@@ -202,12 +202,12 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass; device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv94_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv94_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@@ -230,12 +230,12 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass; device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv98_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@@ -258,12 +258,12 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass; device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@@ -286,12 +286,12 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_CLOCK ] = nvaa_clock_oclass; device->oclass[NVDEV_SUBDEV_CLOCK ] = nvaa_clock_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv98_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nvaa_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nvaa_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@@ -314,12 +314,12 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_CLOCK ] = nvaa_clock_oclass; device->oclass[NVDEV_SUBDEV_CLOCK ] = nvaa_clock_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv98_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nvaa_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nvaa_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@@ -342,12 +342,12 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nva3_clock_oclass; device->oclass[NVDEV_SUBDEV_CLOCK ] = &nva3_clock_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nva3_devinit_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nva3_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nva3_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nva3_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
device->oclass[NVDEV_SUBDEV_PWR ] = &nva3_pwr_oclass; device->oclass[NVDEV_SUBDEV_PWR ] = &nva3_pwr_oclass;
@@ -372,12 +372,12 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nva3_clock_oclass; device->oclass[NVDEV_SUBDEV_CLOCK ] = &nva3_clock_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nva3_devinit_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nva3_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nva3_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nva3_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
device->oclass[NVDEV_SUBDEV_PWR ] = &nva3_pwr_oclass; device->oclass[NVDEV_SUBDEV_PWR ] = &nva3_pwr_oclass;
@@ -401,12 +401,12 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nva3_clock_oclass; device->oclass[NVDEV_SUBDEV_CLOCK ] = &nva3_clock_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nva3_devinit_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nva3_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nva3_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nva3_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
device->oclass[NVDEV_SUBDEV_PWR ] = &nva3_pwr_oclass; device->oclass[NVDEV_SUBDEV_PWR ] = &nva3_pwr_oclass;
@@ -430,12 +430,12 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nva3_clock_oclass; device->oclass[NVDEV_SUBDEV_CLOCK ] = &nva3_clock_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nva3_devinit_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nvaf_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nvaf_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nvaf_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
device->oclass[NVDEV_SUBDEV_PWR ] = &nva3_pwr_oclass; device->oclass[NVDEV_SUBDEV_PWR ] = &nva3_pwr_oclass;

36
drivers/gpu/drm/nouveau/core/engine/device/nvc0.c
View File

@@ -65,14 +65,14 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nvc0_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nvc0_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
device->oclass[NVDEV_SUBDEV_PWR ] = &nvc0_pwr_oclass; device->oclass[NVDEV_SUBDEV_PWR ] = &nvc0_pwr_oclass;
@@ -97,14 +97,14 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nvc0_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nvc0_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
device->oclass[NVDEV_SUBDEV_PWR ] = &nvc0_pwr_oclass; device->oclass[NVDEV_SUBDEV_PWR ] = &nvc0_pwr_oclass;
@@ -129,14 +129,14 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
device->oclass[NVDEV_SUBDEV_PWR ] = &nvc0_pwr_oclass; device->oclass[NVDEV_SUBDEV_PWR ] = &nvc0_pwr_oclass;
@@ -160,14 +160,14 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nvc0_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nvc0_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
device->oclass[NVDEV_SUBDEV_PWR ] = &nvc0_pwr_oclass; device->oclass[NVDEV_SUBDEV_PWR ] = &nvc0_pwr_oclass;
@@ -192,14 +192,14 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
device->oclass[NVDEV_SUBDEV_PWR ] = &nvc0_pwr_oclass; device->oclass[NVDEV_SUBDEV_PWR ] = &nvc0_pwr_oclass;
@@ -224,14 +224,14 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
device->oclass[NVDEV_SUBDEV_PWR ] = &nvc0_pwr_oclass; device->oclass[NVDEV_SUBDEV_PWR ] = &nvc0_pwr_oclass;
@@ -255,14 +255,14 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nvc0_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nvc0_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
device->oclass[NVDEV_SUBDEV_PWR ] = &nvc0_pwr_oclass; device->oclass[NVDEV_SUBDEV_PWR ] = &nvc0_pwr_oclass;
@@ -287,14 +287,14 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
device->oclass[NVDEV_SUBDEV_PWR ] = &nvd0_pwr_oclass; device->oclass[NVDEV_SUBDEV_PWR ] = &nvd0_pwr_oclass;
@@ -318,14 +318,14 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;

28
drivers/gpu/drm/nouveau/core/engine/device/nve0.c
View File

@@ -65,14 +65,14 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass; device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
device->oclass[NVDEV_SUBDEV_PWR ] = &nvd0_pwr_oclass; device->oclass[NVDEV_SUBDEV_PWR ] = &nvd0_pwr_oclass;
@@ -98,14 +98,14 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass; device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
device->oclass[NVDEV_SUBDEV_PWR ] = &nvd0_pwr_oclass; device->oclass[NVDEV_SUBDEV_PWR ] = &nvd0_pwr_oclass;
@@ -131,14 +131,14 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass; device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
device->oclass[NVDEV_SUBDEV_PWR ] = &nvd0_pwr_oclass; device->oclass[NVDEV_SUBDEV_PWR ] = &nvd0_pwr_oclass;
@@ -164,14 +164,14 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass; device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
device->oclass[NVDEV_SUBDEV_PWR ] = &nvd0_pwr_oclass; device->oclass[NVDEV_SUBDEV_PWR ] = &nvd0_pwr_oclass;
@@ -199,29 +199,27 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass; device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
device->oclass[NVDEV_SUBDEV_PWR ] = &nv108_pwr_oclass; device->oclass[NVDEV_SUBDEV_PWR ] = &nv108_pwr_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;
#if 0 device->oclass[NVDEV_ENGINE_FIFO ] = nv108_fifo_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nvf0_graph_oclass; device->oclass[NVDEV_ENGINE_GR ] = nv108_graph_oclass;
#endif
device->oclass[NVDEV_ENGINE_DISP ] = &nvf0_disp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = &nvf0_disp_oclass;
#if 0
device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass; device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass;
device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass; device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass;
device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass; device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass;
#if 0
device->oclass[NVDEV_ENGINE_BSP ] = &nve0_bsp_oclass; device->oclass[NVDEV_ENGINE_BSP ] = &nve0_bsp_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;

38
drivers/gpu/drm/nouveau/core/engine/disp/nv04.c
View File

@@ -31,9 +31,45 @@ struct nv04_disp_priv {
struct nouveau_disp base; struct nouveau_disp base;
}; };
static int
nv04_disp_scanoutpos(struct nouveau_object *object, u32 mthd,
void *data, u32 size)
{
struct nv04_disp_priv *priv = (void *)object->engine;
struct nv04_display_scanoutpos *args = data;
const int head = (mthd & NV04_DISP_MTHD_HEAD);
u32 line;
if (size < sizeof(*args))
return -EINVAL;
args->vblanks = nv_rd32(priv, 0x680800 + (head * 0x2000)) & 0xffff;
args->vtotal = nv_rd32(priv, 0x680804 + (head * 0x2000)) & 0xffff;
args->vblanke = args->vtotal - 1;
args->hblanks = nv_rd32(priv, 0x680820 + (head * 0x2000)) & 0xffff;
args->htotal = nv_rd32(priv, 0x680824 + (head * 0x2000)) & 0xffff;
args->hblanke = args->htotal - 1;
args->time[0] = ktime_to_ns(ktime_get());
line = nv_rd32(priv, 0x600868 + (head * 0x2000));
args->time[1] = ktime_to_ns(ktime_get());
args->hline = (line & 0xffff0000) >> 16;
args->vline = (line & 0x0000ffff);
return 0;
}
#define HEAD_MTHD(n) (n), (n) + 0x01
static struct nouveau_omthds
nv04_disp_omthds[] = {
{ HEAD_MTHD(NV04_DISP_SCANOUTPOS), nv04_disp_scanoutpos },
{}
};
static struct nouveau_oclass static struct nouveau_oclass
nv04_disp_sclass[] = { nv04_disp_sclass[] = {
{ NV04_DISP_CLASS, &nouveau_object_ofuncs }, { NV04_DISP_CLASS, &nouveau_object_ofuncs, nv04_disp_omthds },
{}, {},
}; };

30
drivers/gpu/drm/nouveau/core/engine/disp/nv50.c
View File

@@ -541,6 +541,35 @@ nv50_disp_curs_ofuncs = {
* Base display object * Base display object
******************************************************************************/ ******************************************************************************/
int
nv50_disp_base_scanoutpos(struct nouveau_object *object, u32 mthd,
void *data, u32 size)
{
struct nv50_disp_priv *priv = (void *)object->engine;
struct nv04_display_scanoutpos *args = data;
const int head = (mthd & NV50_DISP_MTHD_HEAD);
u32 blanke, blanks, total;
if (size < sizeof(*args) || head >= priv->head.nr)
return -EINVAL;
blanke = nv_rd32(priv, 0x610aec + (head * 0x540));
blanks = nv_rd32(priv, 0x610af4 + (head * 0x540));
total = nv_rd32(priv, 0x610afc + (head * 0x540));
args->vblanke = (blanke & 0xffff0000) >> 16;
args->hblanke = (blanke & 0x0000ffff);
args->vblanks = (blanks & 0xffff0000) >> 16;
args->hblanks = (blanks & 0x0000ffff);
args->vtotal = ( total & 0xffff0000) >> 16;
args->htotal = ( total & 0x0000ffff);
args->time[0] = ktime_to_ns(ktime_get());
args->vline = nv_rd32(priv, 0x616340 + (head * 0x800)) & 0xffff;
args->time[1] = ktime_to_ns(ktime_get()); /* vline read locks hline */
args->hline = nv_rd32(priv, 0x616344 + (head * 0x800)) & 0xffff;
return 0;
}
static void static void
nv50_disp_base_vblank_enable(struct nouveau_event *event, int head) nv50_disp_base_vblank_enable(struct nouveau_event *event, int head)
{ {
@@ -675,6 +704,7 @@ nv50_disp_base_ofuncs = {
static struct nouveau_omthds static struct nouveau_omthds
nv50_disp_base_omthds[] = { nv50_disp_base_omthds[] = {
{ HEAD_MTHD(NV50_DISP_SCANOUTPOS) , nv50_disp_base_scanoutpos },
{ SOR_MTHD(NV50_DISP_SOR_PWR) , nv50_sor_mthd }, { SOR_MTHD(NV50_DISP_SOR_PWR) , nv50_sor_mthd },
{ SOR_MTHD(NV50_DISP_SOR_LVDS_SCRIPT) , nv50_sor_mthd }, { SOR_MTHD(NV50_DISP_SOR_LVDS_SCRIPT) , nv50_sor_mthd },
{ DAC_MTHD(NV50_DISP_DAC_PWR) , nv50_dac_mthd }, { DAC_MTHD(NV50_DISP_DAC_PWR) , nv50_dac_mthd },

7
drivers/gpu/drm/nouveau/core/engine/disp/nv50.h
View File

@@ -43,6 +43,10 @@ struct nv50_disp_priv {
} pior; } pior;
}; };
#define HEAD_MTHD(n) (n), (n) + 0x03
int nv50_disp_base_scanoutpos(struct nouveau_object *, u32, void *, u32);
#define DAC_MTHD(n) (n), (n) + 0x03 #define DAC_MTHD(n) (n), (n) + 0x03
int nv50_dac_mthd(struct nouveau_object *, u32, void *, u32); int nv50_dac_mthd(struct nouveau_object *, u32, void *, u32);
@@ -132,13 +136,12 @@ void nv50_disp_intr(struct nouveau_subdev *);
extern struct nouveau_omthds nv84_disp_base_omthds[]; extern struct nouveau_omthds nv84_disp_base_omthds[];
extern struct nouveau_omthds nva3_disp_base_omthds[];
extern struct nouveau_ofuncs nvd0_disp_mast_ofuncs; extern struct nouveau_ofuncs nvd0_disp_mast_ofuncs;
extern struct nouveau_ofuncs nvd0_disp_sync_ofuncs; extern struct nouveau_ofuncs nvd0_disp_sync_ofuncs;
extern struct nouveau_ofuncs nvd0_disp_ovly_ofuncs; extern struct nouveau_ofuncs nvd0_disp_ovly_ofuncs;
extern struct nouveau_ofuncs nvd0_disp_oimm_ofuncs; extern struct nouveau_ofuncs nvd0_disp_oimm_ofuncs;
extern struct nouveau_ofuncs nvd0_disp_curs_ofuncs; extern struct nouveau_ofuncs nvd0_disp_curs_ofuncs;
extern struct nouveau_omthds nvd0_disp_base_omthds[];
extern struct nouveau_ofuncs nvd0_disp_base_ofuncs; extern struct nouveau_ofuncs nvd0_disp_base_ofuncs;
extern struct nouveau_oclass nvd0_disp_cclass; extern struct nouveau_oclass nvd0_disp_cclass;
void nvd0_disp_intr_supervisor(struct work_struct *); void nvd0_disp_intr_supervisor(struct work_struct *);

1
drivers/gpu/drm/nouveau/core/engine/disp/nv84.c
View File

@@ -41,6 +41,7 @@ nv84_disp_sclass[] = {
struct nouveau_omthds struct nouveau_omthds
nv84_disp_base_omthds[] = { nv84_disp_base_omthds[] = {
{ HEAD_MTHD(NV50_DISP_SCANOUTPOS) , nv50_disp_base_scanoutpos },
{ SOR_MTHD(NV50_DISP_SOR_PWR) , nv50_sor_mthd }, { SOR_MTHD(NV50_DISP_SOR_PWR) , nv50_sor_mthd },
{ SOR_MTHD(NV84_DISP_SOR_HDMI_PWR) , nv50_sor_mthd }, { SOR_MTHD(NV84_DISP_SOR_HDMI_PWR) , nv50_sor_mthd },
{ SOR_MTHD(NV50_DISP_SOR_LVDS_SCRIPT) , nv50_sor_mthd }, { SOR_MTHD(NV50_DISP_SOR_LVDS_SCRIPT) , nv50_sor_mthd },

1
drivers/gpu/drm/nouveau/core/engine/disp/nv94.c
View File

@@ -41,6 +41,7 @@ nv94_disp_sclass[] = {
static struct nouveau_omthds static struct nouveau_omthds
nv94_disp_base_omthds[] = { nv94_disp_base_omthds[] = {
{ HEAD_MTHD(NV50_DISP_SCANOUTPOS) , nv50_disp_base_scanoutpos },
{ SOR_MTHD(NV50_DISP_SOR_PWR) , nv50_sor_mthd }, { SOR_MTHD(NV50_DISP_SOR_PWR) , nv50_sor_mthd },
{ SOR_MTHD(NV84_DISP_SOR_HDMI_PWR) , nv50_sor_mthd }, { SOR_MTHD(NV84_DISP_SOR_HDMI_PWR) , nv50_sor_mthd },
{ SOR_MTHD(NV50_DISP_SOR_LVDS_SCRIPT) , nv50_sor_mthd }, { SOR_MTHD(NV50_DISP_SOR_LVDS_SCRIPT) , nv50_sor_mthd },

3
drivers/gpu/drm/nouveau/core/engine/disp/nva3.c
View File

@@ -39,8 +39,9 @@ nva3_disp_sclass[] = {
{} {}
}; };
struct nouveau_omthds static struct nouveau_omthds
nva3_disp_base_omthds[] = { nva3_disp_base_omthds[] = {
{ HEAD_MTHD(NV50_DISP_SCANOUTPOS) , nv50_disp_base_scanoutpos },
{ SOR_MTHD(NV50_DISP_SOR_PWR) , nv50_sor_mthd }, { SOR_MTHD(NV50_DISP_SOR_PWR) , nv50_sor_mthd },
{ SOR_MTHD(NVA3_DISP_SOR_HDA_ELD) , nv50_sor_mthd }, { SOR_MTHD(NVA3_DISP_SOR_HDA_ELD) , nv50_sor_mthd },
{ SOR_MTHD(NV84_DISP_SOR_HDMI_PWR) , nv50_sor_mthd }, { SOR_MTHD(NV84_DISP_SOR_HDMI_PWR) , nv50_sor_mthd },

50
drivers/gpu/drm/nouveau/core/engine/disp/nvd0.c
View File

@@ -440,6 +440,36 @@ nvd0_disp_curs_ofuncs = {
* Base display object * Base display object
******************************************************************************/ ******************************************************************************/
static int
nvd0_disp_base_scanoutpos(struct nouveau_object *object, u32 mthd,
void *data, u32 size)
{
struct nv50_disp_priv *priv = (void *)object->engine;
struct nv04_display_scanoutpos *args = data;
const int head = (mthd & NV50_DISP_MTHD_HEAD);
u32 blanke, blanks, total;
if (size < sizeof(*args) || head >= priv->head.nr)
return -EINVAL;
total = nv_rd32(priv, 0x640414 + (head * 0x300));
blanke = nv_rd32(priv, 0x64041c + (head * 0x300));
blanks = nv_rd32(priv, 0x640420 + (head * 0x300));
args->vblanke = (blanke & 0xffff0000) >> 16;
args->hblanke = (blanke & 0x0000ffff);
args->vblanks = (blanks & 0xffff0000) >> 16;
args->hblanks = (blanks & 0x0000ffff);
args->vtotal = ( total & 0xffff0000) >> 16;
args->htotal = ( total & 0x0000ffff);
args->time[0] = ktime_to_ns(ktime_get());
args->vline = nv_rd32(priv, 0x616340 + (head * 0x800)) & 0xffff;
args->time[1] = ktime_to_ns(ktime_get()); /* vline read locks hline */
args->hline = nv_rd32(priv, 0x616344 + (head * 0x800)) & 0xffff;
return 0;
}
static void static void
nvd0_disp_base_vblank_enable(struct nouveau_event *event, int head) nvd0_disp_base_vblank_enable(struct nouveau_event *event, int head)
{ {
@@ -573,9 +603,24 @@ nvd0_disp_base_ofuncs = {
.fini = nvd0_disp_base_fini, .fini = nvd0_disp_base_fini,
}; };
struct nouveau_omthds
nvd0_disp_base_omthds[] = {
{ HEAD_MTHD(NV50_DISP_SCANOUTPOS) , nvd0_disp_base_scanoutpos },
{ SOR_MTHD(NV50_DISP_SOR_PWR) , nv50_sor_mthd },
{ SOR_MTHD(NVA3_DISP_SOR_HDA_ELD) , nv50_sor_mthd },
{ SOR_MTHD(NV84_DISP_SOR_HDMI_PWR) , nv50_sor_mthd },
{ SOR_MTHD(NV50_DISP_SOR_LVDS_SCRIPT) , nv50_sor_mthd },
{ DAC_MTHD(NV50_DISP_DAC_PWR) , nv50_dac_mthd },
{ DAC_MTHD(NV50_DISP_DAC_LOAD) , nv50_dac_mthd },
{ PIOR_MTHD(NV50_DISP_PIOR_PWR) , nv50_pior_mthd },
{ PIOR_MTHD(NV50_DISP_PIOR_TMDS_PWR) , nv50_pior_mthd },
{ PIOR_MTHD(NV50_DISP_PIOR_DP_PWR) , nv50_pior_mthd },
{},
};
static struct nouveau_oclass static struct nouveau_oclass
nvd0_disp_base_oclass[] = { nvd0_disp_base_oclass[] = {
{ NVD0_DISP_CLASS, &nvd0_disp_base_ofuncs, nva3_disp_base_omthds }, { NVD0_DISP_CLASS, &nvd0_disp_base_ofuncs, nvd0_disp_base_omthds },
{} {}
}; };
@@ -967,9 +1012,6 @@ nvd0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
int heads = nv_rd32(parent, 0x022448); int heads = nv_rd32(parent, 0x022448);
int ret; int ret;
if (nv_rd32(parent, 0x022500) & 0x00000001)
return -ENODEV;
ret = nouveau_disp_create(parent, engine, oclass, heads, ret = nouveau_disp_create(parent, engine, oclass, heads,
"PDISP", "display", &priv); "PDISP", "display", &priv);
*pobject = nv_object(priv); *pobject = nv_object(priv);

5
drivers/gpu/drm/nouveau/core/engine/disp/nve0.c
View File

@@ -41,7 +41,7 @@ nve0_disp_sclass[] = {
static struct nouveau_oclass static struct nouveau_oclass
nve0_disp_base_oclass[] = { nve0_disp_base_oclass[] = {
{ NVE0_DISP_CLASS, &nvd0_disp_base_ofuncs, nva3_disp_base_omthds }, { NVE0_DISP_CLASS, &nvd0_disp_base_ofuncs, nvd0_disp_base_omthds },
{} {}
}; };
@@ -54,9 +54,6 @@ nve0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
int heads = nv_rd32(parent, 0x022448); int heads = nv_rd32(parent, 0x022448);
int ret; int ret;
if (nv_rd32(parent, 0x022500) & 0x00000001)
return -ENODEV;
ret = nouveau_disp_create(parent, engine, oclass, heads, ret = nouveau_disp_create(parent, engine, oclass, heads,
"PDISP", "display", &priv); "PDISP", "display", &priv);
*pobject = nv_object(priv); *pobject = nv_object(priv);

5
drivers/gpu/drm/nouveau/core/engine/disp/nvf0.c
View File

@@ -41,7 +41,7 @@ nvf0_disp_sclass[] = {
static struct nouveau_oclass static struct nouveau_oclass
nvf0_disp_base_oclass[] = { nvf0_disp_base_oclass[] = {
{ NVF0_DISP_CLASS, &nvd0_disp_base_ofuncs, nva3_disp_base_omthds }, { NVF0_DISP_CLASS, &nvd0_disp_base_ofuncs, nvd0_disp_base_omthds },
{} {}
}; };
@@ -54,9 +54,6 @@ nvf0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
int heads = nv_rd32(parent, 0x022448); int heads = nv_rd32(parent, 0x022448);
int ret; int ret;
if (nv_rd32(parent, 0x022500) & 0x00000001)
return -ENODEV;
ret = nouveau_disp_create(parent, engine, oclass, heads, ret = nouveau_disp_create(parent, engine, oclass, heads,
"PDISP", "display", &priv); "PDISP", "display", &priv);
*pobject = nv_object(priv); *pobject = nv_object(priv);

9
drivers/gpu/drm/nouveau/core/engine/disp/vga.c
View File

@@ -138,10 +138,15 @@ nv_wrvgai(void *obj, int head, u16 port, u8 index, u8 value)
bool bool
nv_lockvgac(void *obj, bool lock) nv_lockvgac(void *obj, bool lock)
{ {
struct nouveau_device *dev = nv_device(obj);
bool locked = !nv_rdvgac(obj, 0, 0x1f); bool locked = !nv_rdvgac(obj, 0, 0x1f);
u8 data = lock ? 0x99 : 0x57; u8 data = lock ? 0x99 : 0x57;
nv_wrvgac(obj, 0, 0x1f, data); if (dev->card_type < NV_50)
if (nv_device(obj)->chipset == 0x11) { nv_wrvgac(obj, 0, 0x1f, data);
else
nv_wrvgac(obj, 0, 0x3f, data);
if (dev->chipset == 0x11) {
if (!(nv_rd32(obj, 0x001084) & 0x10000000)) if (!(nv_rd32(obj, 0x001084) & 0x10000000))
nv_wrvgac(obj, 1, 0x1f, data); nv_wrvgac(obj, 1, 0x1f, data);
} }

20
drivers/gpu/drm/nouveau/core/engine/falcon.c
View File

@@ -56,6 +56,16 @@ _nouveau_falcon_wr32(struct nouveau_object *object, u64 addr, u32 data)
nv_wr32(falcon, falcon->addr + addr, data); nv_wr32(falcon, falcon->addr + addr, data);
} }
static void *
vmemdup(const void *src, size_t len)
{
void *p = vmalloc(len);
if (p)
memcpy(p, src, len);
return p;
}
int int
_nouveau_falcon_init(struct nouveau_object *object) _nouveau_falcon_init(struct nouveau_object *object)
{ {
@@ -111,7 +121,7 @@ _nouveau_falcon_init(struct nouveau_object *object)
ret = request_firmware(&fw, name, &device->pdev->dev); ret = request_firmware(&fw, name, &device->pdev->dev);
if (ret == 0) { if (ret == 0) {
falcon->code.data = kmemdup(fw->data, fw->size, GFP_KERNEL); falcon->code.data = vmemdup(fw->data, fw->size);
falcon->code.size = fw->size; falcon->code.size = fw->size;
falcon->data.data = NULL; falcon->data.data = NULL;
falcon->data.size = 0; falcon->data.size = 0;
@@ -134,7 +144,7 @@ _nouveau_falcon_init(struct nouveau_object *object)
return ret; return ret;
} }
falcon->data.data = kmemdup(fw->data, fw->size, GFP_KERNEL); falcon->data.data = vmemdup(fw->data, fw->size);
falcon->data.size = fw->size; falcon->data.size = fw->size;
release_firmware(fw); release_firmware(fw);
if (!falcon->data.data) if (!falcon->data.data)
@@ -149,7 +159,7 @@ _nouveau_falcon_init(struct nouveau_object *object)
return ret; return ret;
} }
falcon->code.data = kmemdup(fw->data, fw->size, GFP_KERNEL); falcon->code.data = vmemdup(fw->data, fw->size);
falcon->code.size = fw->size; falcon->code.size = fw->size;
release_firmware(fw); release_firmware(fw);
if (!falcon->code.data) if (!falcon->code.data)
@@ -235,8 +245,8 @@ _nouveau_falcon_fini(struct nouveau_object *object, bool suspend)
if (!suspend) { if (!suspend) {
nouveau_gpuobj_ref(NULL, &falcon->core); nouveau_gpuobj_ref(NULL, &falcon->core);
if (falcon->external) { if (falcon->external) {
kfree(falcon->data.data); vfree(falcon->data.data);
kfree(falcon->code.data); vfree(falcon->code.data);
falcon->code.data = NULL; falcon->code.data = NULL;
} }
} }

37
drivers/gpu/drm/nouveau/core/engine/fifo/nv108.c Normal file
View File

@@ -0,0 +1,37 @@
/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include "nve0.h"
struct nouveau_oclass *
nv108_fifo_oclass = &(struct nve0_fifo_impl) {
.base.handle = NV_ENGINE(FIFO, 0x08),
.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nve0_fifo_ctor,
.dtor = nve0_fifo_dtor,
.init = nve0_fifo_init,
.fini = _nouveau_fifo_fini,
},
.channels = 1024,
}.base;

1
drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c
View File

@@ -33,6 +33,7 @@
#include <subdev/timer.h> #include <subdev/timer.h>
#include <subdev/bar.h> #include <subdev/bar.h>
#include <subdev/fb.h>
#include <subdev/vm.h> #include <subdev/vm.h>
#include <engine/dmaobj.h> #include <engine/dmaobj.h>

414
drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c
View File

@@ -33,10 +33,12 @@
#include <subdev/timer.h> #include <subdev/timer.h>
#include <subdev/bar.h> #include <subdev/bar.h>
#include <subdev/fb.h>
#include <subdev/vm.h> #include <subdev/vm.h>
#include <engine/dmaobj.h> #include <engine/dmaobj.h>
#include <engine/fifo.h>
#include "nve0.h"
#define _(a,b) { (a), ((1ULL << (a)) | (b)) } #define _(a,b) { (a), ((1ULL << (a)) | (b)) }
static const struct { static const struct {
@@ -56,8 +58,8 @@ static const struct {
#define FIFO_ENGINE_NR ARRAY_SIZE(fifo_engine) #define FIFO_ENGINE_NR ARRAY_SIZE(fifo_engine)
struct nve0_fifo_engn { struct nve0_fifo_engn {
struct nouveau_gpuobj *playlist[2]; struct nouveau_gpuobj *runlist[2];
int cur_playlist; int cur_runlist;
}; };
struct nve0_fifo_priv { struct nve0_fifo_priv {
@@ -86,7 +88,7 @@ struct nve0_fifo_chan {
******************************************************************************/ ******************************************************************************/
static void static void
nve0_fifo_playlist_update(struct nve0_fifo_priv *priv, u32 engine) nve0_fifo_runlist_update(struct nve0_fifo_priv *priv, u32 engine)
{ {
struct nouveau_bar *bar = nouveau_bar(priv); struct nouveau_bar *bar = nouveau_bar(priv);
struct nve0_fifo_engn *engn = &priv->engine[engine]; struct nve0_fifo_engn *engn = &priv->engine[engine];
@@ -95,8 +97,8 @@ nve0_fifo_playlist_update(struct nve0_fifo_priv *priv, u32 engine)
int i, p; int i, p;
mutex_lock(&nv_subdev(priv)->mutex); mutex_lock(&nv_subdev(priv)->mutex);
cur = engn->playlist[engn->cur_playlist]; cur = engn->runlist[engn->cur_runlist];
engn->cur_playlist = !engn->cur_playlist; engn->cur_runlist = !engn->cur_runlist;
for (i = 0, p = 0; i < priv->base.max; i++) { for (i = 0, p = 0; i < priv->base.max; i++) {
u32 ctrl = nv_rd32(priv, 0x800004 + (i * 8)) & 0x001f0001; u32 ctrl = nv_rd32(priv, 0x800004 + (i * 8)) & 0x001f0001;
@@ -111,7 +113,7 @@ nve0_fifo_playlist_update(struct nve0_fifo_priv *priv, u32 engine)
nv_wr32(priv, 0x002270, cur->addr >> 12); nv_wr32(priv, 0x002270, cur->addr >> 12);
nv_wr32(priv, 0x002274, (engine << 20) | (p >> 3)); nv_wr32(priv, 0x002274, (engine << 20) | (p >> 3));
if (!nv_wait(priv, 0x002284 + (engine * 4), 0x00100000, 0x00000000)) if (!nv_wait(priv, 0x002284 + (engine * 4), 0x00100000, 0x00000000))
nv_error(priv, "playlist %d update timeout\n", engine); nv_error(priv, "runlist %d update timeout\n", engine);
mutex_unlock(&nv_subdev(priv)->mutex); mutex_unlock(&nv_subdev(priv)->mutex);
} }
@@ -278,7 +280,7 @@ nve0_fifo_chan_init(struct nouveau_object *object)
nv_mask(priv, 0x800004 + (chid * 8), 0x000f0000, chan->engine << 16); nv_mask(priv, 0x800004 + (chid * 8), 0x000f0000, chan->engine << 16);
nv_wr32(priv, 0x800000 + (chid * 8), 0x80000000 | base->addr >> 12); nv_wr32(priv, 0x800000 + (chid * 8), 0x80000000 | base->addr >> 12);
nv_mask(priv, 0x800004 + (chid * 8), 0x00000400, 0x00000400); nv_mask(priv, 0x800004 + (chid * 8), 0x00000400, 0x00000400);
nve0_fifo_playlist_update(priv, chan->engine); nve0_fifo_runlist_update(priv, chan->engine);
nv_mask(priv, 0x800004 + (chid * 8), 0x00000400, 0x00000400); nv_mask(priv, 0x800004 + (chid * 8), 0x00000400, 0x00000400);
return 0; return 0;
} }
@@ -291,7 +293,7 @@ nve0_fifo_chan_fini(struct nouveau_object *object, bool suspend)
u32 chid = chan->base.chid; u32 chid = chan->base.chid;
nv_mask(priv, 0x800004 + (chid * 8), 0x00000800, 0x00000800); nv_mask(priv, 0x800004 + (chid * 8), 0x00000800, 0x00000800);
nve0_fifo_playlist_update(priv, chan->engine); nve0_fifo_runlist_update(priv, chan->engine);
nv_wr32(priv, 0x800000 + (chid * 8), 0x00000000); nv_wr32(priv, 0x800000 + (chid * 8), 0x00000000);
return nouveau_fifo_channel_fini(&chan->base, suspend); return nouveau_fifo_channel_fini(&chan->base, suspend);
@@ -375,54 +377,189 @@ nve0_fifo_cclass = {
* PFIFO engine * PFIFO engine
******************************************************************************/ ******************************************************************************/
static const struct nouveau_enum nve0_fifo_fault_unit[] = { static const struct nouveau_enum nve0_fifo_sched_reason[] = {
{ 0x0a, "CTXSW_TIMEOUT" },
{}
};
static const struct nouveau_enum nve0_fifo_fault_engine[] = {
{ 0x00, "GR", NULL, NVDEV_ENGINE_GR },
{ 0x03, "IFB" },
{ 0x04, "BAR1", NULL, NVDEV_SUBDEV_BAR },
{ 0x05, "BAR3", NULL, NVDEV_SUBDEV_INSTMEM },
{ 0x07, "PBDMA0", NULL, NVDEV_ENGINE_FIFO },
{ 0x08, "PBDMA1", NULL, NVDEV_ENGINE_FIFO },
{ 0x09, "PBDMA2", NULL, NVDEV_ENGINE_FIFO },
{ 0x10, "MSVLD", NULL, NVDEV_ENGINE_BSP },
{ 0x11, "MSPPP", NULL, NVDEV_ENGINE_PPP },
{ 0x13, "PERF" },
{ 0x14, "MSPDEC", NULL, NVDEV_ENGINE_VP },
{ 0x15, "CE0", NULL, NVDEV_ENGINE_COPY0 },
{ 0x16, "CE1", NULL, NVDEV_ENGINE_COPY1 },
{ 0x17, "PMU" },
{ 0x19, "MSENC", NULL, NVDEV_ENGINE_VENC },
{ 0x1b, "CE2", NULL, NVDEV_ENGINE_COPY2 },
{} {}
}; };
static const struct nouveau_enum nve0_fifo_fault_reason[] = { static const struct nouveau_enum nve0_fifo_fault_reason[] = {
{ 0x00, "PT_NOT_PRESENT" }, { 0x00, "PDE" },
{ 0x01, "PT_TOO_SHORT" }, { 0x01, "PDE_SIZE" },
{ 0x02, "PAGE_NOT_PRESENT" }, { 0x02, "PTE" },
{ 0x03, "VM_LIMIT_EXCEEDED" }, { 0x03, "VA_LIMIT_VIOLATION" },
{ 0x04, "NO_CHANNEL" }, { 0x04, "UNBOUND_INST_BLOCK" },
{ 0x05, "PAGE_SYSTEM_ONLY" }, { 0x05, "PRIV_VIOLATION" },
{ 0x06, "PAGE_READ_ONLY" }, { 0x06, "RO_VIOLATION" },
{ 0x0a, "COMPRESSED_SYSRAM" }, { 0x07, "WO_VIOLATION" },
{ 0x0c, "INVALID_STORAGE_TYPE" }, { 0x08, "PITCH_MASK_VIOLATION" },
{ 0x09, "WORK_CREATION" },
{ 0x0a, "UNSUPPORTED_APERTURE" },
{ 0x0b, "COMPRESSION_FAILURE" },
{ 0x0c, "UNSUPPORTED_KIND" },
{ 0x0d, "REGION_VIOLATION" },
{ 0x0e, "BOTH_PTES_VALID" },
{ 0x0f, "INFO_TYPE_POISONED" },
{} {}
}; };
static const struct nouveau_enum nve0_fifo_fault_hubclient[] = { static const struct nouveau_enum nve0_fifo_fault_hubclient[] = {
{ 0x00, "VIP" },
{ 0x01, "CE0" },
{ 0x02, "CE1" },
{ 0x03, "DNISO" },
{ 0x04, "FE" },
{ 0x05, "FECS" },
{ 0x06, "HOST" },
{ 0x07, "HOST_CPU" },
{ 0x08, "HOST_CPU_NB" },
{ 0x09, "ISO" },
{ 0x0a, "MMU" },
{ 0x0b, "MSPDEC" },
{ 0x0c, "MSPPP" },
{ 0x0d, "MSVLD" },
{ 0x0e, "NISO" },
{ 0x0f, "P2P" },
{ 0x10, "PD" },
{ 0x11, "PERF" },
{ 0x12, "PMU" },
{ 0x13, "RASTERTWOD" },
{ 0x14, "SCC" },
{ 0x15, "SCC_NB" },
{ 0x16, "SEC" },
{ 0x17, "SSYNC" },
{ 0x18, "GR_COPY" },
{ 0x19, "CE2" },
{ 0x1a, "XV" },
{ 0x1b, "MMU_NB" },
{ 0x1c, "MSENC" },
{ 0x1d, "DFALCON" },
{ 0x1e, "SKED" },
{ 0x1f, "AFALCON" },
{} {}
}; };
static const struct nouveau_enum nve0_fifo_fault_gpcclient[] = { static const struct nouveau_enum nve0_fifo_fault_gpcclient[] = {
{ 0x00, "L1_0" }, { 0x01, "T1_0" }, { 0x02, "PE_0" },
{ 0x03, "L1_1" }, { 0x04, "T1_1" }, { 0x05, "PE_1" },
{ 0x06, "L1_2" }, { 0x07, "T1_2" }, { 0x08, "PE_2" },
{ 0x09, "L1_3" }, { 0x0a, "T1_3" }, { 0x0b, "PE_3" },
{ 0x0c, "RAST" },
{ 0x0d, "GCC" },
{ 0x0e, "GPCCS" },
{ 0x0f, "PROP_0" },
{ 0x10, "PROP_1" },
{ 0x11, "PROP_2" },
{ 0x12, "PROP_3" },
{ 0x13, "L1_4" }, { 0x14, "T1_4" }, { 0x15, "PE_4" },
{ 0x16, "L1_5" }, { 0x17, "T1_5" }, { 0x18, "PE_5" },
{ 0x19, "L1_6" }, { 0x1a, "T1_6" }, { 0x1b, "PE_6" },
{ 0x1c, "L1_7" }, { 0x1d, "T1_7" }, { 0x1e, "PE_7" },
{ 0x1f, "GPM" },
{ 0x20, "LTP_UTLB_0" },
{ 0x21, "LTP_UTLB_1" },
{ 0x22, "LTP_UTLB_2" },
{ 0x23, "LTP_UTLB_3" },
{ 0x24, "GPC_RGG_UTLB" },
{} {}
}; };
static const struct nouveau_bitfield nve0_fifo_subfifo_intr[] = { static const struct nouveau_bitfield nve0_fifo_pbdma_intr[] = {
{ 0x00200000, "ILLEGAL_MTHD" }, { 0x00000001, "MEMREQ" },
{ 0x00800000, "EMPTY_SUBC" }, { 0x00000002, "MEMACK_TIMEOUT" },
{ 0x00000004, "MEMACK_EXTRA" },
{ 0x00000008, "MEMDAT_TIMEOUT" },
{ 0x00000010, "MEMDAT_EXTRA" },
{ 0x00000020, "MEMFLUSH" },
{ 0x00000040, "MEMOP" },
{ 0x00000080, "LBCONNECT" },
{ 0x00000100, "LBREQ" },
{ 0x00000200, "LBACK_TIMEOUT" },
{ 0x00000400, "LBACK_EXTRA" },
{ 0x00000800, "LBDAT_TIMEOUT" },
{ 0x00001000, "LBDAT_EXTRA" },
{ 0x00002000, "GPFIFO" },
{ 0x00004000, "GPPTR" },
{ 0x00008000, "GPENTRY" },
{ 0x00010000, "GPCRC" },
{ 0x00020000, "PBPTR" },
{ 0x00040000, "PBENTRY" },
{ 0x00080000, "PBCRC" },
{ 0x00100000, "XBARCONNECT" },
{ 0x00200000, "METHOD" },
{ 0x00400000, "METHODCRC" },
{ 0x00800000, "DEVICE" },
{ 0x02000000, "SEMAPHORE" },
{ 0x04000000, "ACQUIRE" },
{ 0x08000000, "PRI" },
{ 0x20000000, "NO_CTXSW_SEG" },
{ 0x40000000, "PBSEG" },
{ 0x80000000, "SIGNATURE" },
{} {}
}; };
static void static void
nve0_fifo_isr_vm_fault(struct nve0_fifo_priv *priv, int unit) nve0_fifo_intr_sched(struct nve0_fifo_priv *priv)
{
u32 intr = nv_rd32(priv, 0x00254c);
u32 code = intr & 0x000000ff;
nv_error(priv, "SCHED_ERROR [");
nouveau_enum_print(nve0_fifo_sched_reason, code);
pr_cont("]\n");
}
static void
nve0_fifo_intr_chsw(struct nve0_fifo_priv *priv)
{
u32 stat = nv_rd32(priv, 0x00256c);
nv_error(priv, "CHSW_ERROR 0x%08x\n", stat);
nv_wr32(priv, 0x00256c, stat);
}
static void
nve0_fifo_intr_dropped_fault(struct nve0_fifo_priv *priv)
{
u32 stat = nv_rd32(priv, 0x00259c);
nv_error(priv, "DROPPED_MMU_FAULT 0x%08x\n", stat);
}
static void
nve0_fifo_intr_fault(struct nve0_fifo_priv *priv, int unit)
{ {
u32 inst = nv_rd32(priv, 0x2800 + (unit * 0x10)); u32 inst = nv_rd32(priv, 0x2800 + (unit * 0x10));
u32 valo = nv_rd32(priv, 0x2804 + (unit * 0x10)); u32 valo = nv_rd32(priv, 0x2804 + (unit * 0x10));
u32 vahi = nv_rd32(priv, 0x2808 + (unit * 0x10)); u32 vahi = nv_rd32(priv, 0x2808 + (unit * 0x10));
u32 stat = nv_rd32(priv, 0x280c + (unit * 0x10)); u32 stat = nv_rd32(priv, 0x280c + (unit * 0x10));
u32 client = (stat & 0x00001f00) >> 8; u32 client = (stat & 0x00001f00) >> 8;
const struct nouveau_enum *en; struct nouveau_engine *engine = NULL;
struct nouveau_engine *engine;
struct nouveau_object *engctx = NULL; struct nouveau_object *engctx = NULL;
const struct nouveau_enum *en;
const char *name = "unknown";
nv_error(priv, "PFIFO: %s fault at 0x%010llx [", (stat & 0x00000080) ? nv_error(priv, "PFIFO: %s fault at 0x%010llx [", (stat & 0x00000080) ?
"write" : "read", (u64)vahi << 32 | valo); "write" : "read", (u64)vahi << 32 | valo);
nouveau_enum_print(nve0_fifo_fault_reason, stat & 0x0000000f); nouveau_enum_print(nve0_fifo_fault_reason, stat & 0x0000000f);
pr_cont("] from "); pr_cont("] from ");
en = nouveau_enum_print(nve0_fifo_fault_unit, unit); en = nouveau_enum_print(nve0_fifo_fault_engine, unit);
if (stat & 0x00000040) { if (stat & 0x00000040) {
pr_cont("/"); pr_cont("/");
nouveau_enum_print(nve0_fifo_fault_hubclient, client); nouveau_enum_print(nve0_fifo_fault_hubclient, client);
@@ -432,14 +569,22 @@ nve0_fifo_isr_vm_fault(struct nve0_fifo_priv *priv, int unit)
} }
if (en && en->data2) { if (en && en->data2) {
engine = nouveau_engine(priv, en->data2); if (en->data2 == NVDEV_SUBDEV_BAR) {
if (engine) nv_mask(priv, 0x001704, 0x00000000, 0x00000000);
engctx = nouveau_engctx_get(engine, inst); name = "BAR1";
} else
if (en->data2 == NVDEV_SUBDEV_INSTMEM) {
nv_mask(priv, 0x001714, 0x00000000, 0x00000000);
name = "BAR3";
} else {
engine = nouveau_engine(priv, en->data2);
if (engine) {
engctx = nouveau_engctx_get(engine, inst);
name = nouveau_client_name(engctx);
}
}
} }
pr_cont(" on channel 0x%010llx [%s]\n", (u64)inst << 12, name);
pr_cont(" on channel 0x%010llx [%s]\n", (u64)inst << 12,
nouveau_client_name(engctx));
nouveau_engctx_put(engctx); nouveau_engctx_put(engctx);
} }
@@ -471,7 +616,7 @@ out:
} }
static void static void
nve0_fifo_isr_subfifo_intr(struct nve0_fifo_priv *priv, int unit) nve0_fifo_intr_pbdma(struct nve0_fifo_priv *priv, int unit)
{ {
u32 stat = nv_rd32(priv, 0x040108 + (unit * 0x2000)); u32 stat = nv_rd32(priv, 0x040108 + (unit * 0x2000));
u32 addr = nv_rd32(priv, 0x0400c0 + (unit * 0x2000)); u32 addr = nv_rd32(priv, 0x0400c0 + (unit * 0x2000));
@@ -487,11 +632,11 @@ nve0_fifo_isr_subfifo_intr(struct nve0_fifo_priv *priv, int unit)
} }
if (show) { if (show) {
nv_error(priv, "SUBFIFO%d:", unit); nv_error(priv, "PBDMA%d:", unit);
nouveau_bitfield_print(nve0_fifo_subfifo_intr, show); nouveau_bitfield_print(nve0_fifo_pbdma_intr, show);
pr_cont("\n"); pr_cont("\n");
nv_error(priv, nv_error(priv,
"SUBFIFO%d: ch %d [%s] subc %d mthd 0x%04x data 0x%08x\n", "PBDMA%d: ch %d [%s] subc %d mthd 0x%04x data 0x%08x\n",
unit, chid, unit, chid,
nouveau_client_name_for_fifo_chid(&priv->base, chid), nouveau_client_name_for_fifo_chid(&priv->base, chid),
subc, mthd, data); subc, mthd, data);
@@ -508,19 +653,56 @@ nve0_fifo_intr(struct nouveau_subdev *subdev)
u32 mask = nv_rd32(priv, 0x002140); u32 mask = nv_rd32(priv, 0x002140);
u32 stat = nv_rd32(priv, 0x002100) & mask; u32 stat = nv_rd32(priv, 0x002100) & mask;
if (stat & 0x00000001) {
u32 stat = nv_rd32(priv, 0x00252c);
nv_error(priv, "BIND_ERROR 0x%08x\n", stat);
nv_wr32(priv, 0x002100, 0x00000001);
stat &= ~0x00000001;
}
if (stat & 0x00000010) {
nv_error(priv, "PIO_ERROR\n");
nv_wr32(priv, 0x002100, 0x00000010);
stat &= ~0x00000010;
}
if (stat & 0x00000100) { if (stat & 0x00000100) {
nv_warn(priv, "unknown status 0x00000100\n"); nve0_fifo_intr_sched(priv);
nv_wr32(priv, 0x002100, 0x00000100); nv_wr32(priv, 0x002100, 0x00000100);
stat &= ~0x00000100; stat &= ~0x00000100;
} }
if (stat & 0x00010000) {
nve0_fifo_intr_chsw(priv);
nv_wr32(priv, 0x002100, 0x00010000);
stat &= ~0x00010000;
}
if (stat & 0x00800000) {
nv_error(priv, "FB_FLUSH_TIMEOUT\n");
nv_wr32(priv, 0x002100, 0x00800000);
stat &= ~0x00800000;
}
if (stat & 0x01000000) {
nv_error(priv, "LB_ERROR\n");
nv_wr32(priv, 0x002100, 0x01000000);
stat &= ~0x01000000;
}
if (stat & 0x08000000) {
nve0_fifo_intr_dropped_fault(priv);
nv_wr32(priv, 0x002100, 0x08000000);
stat &= ~0x08000000;
}
if (stat & 0x10000000) { if (stat & 0x10000000) {
u32 units = nv_rd32(priv, 0x00259c); u32 units = nv_rd32(priv, 0x00259c);
u32 u = units; u32 u = units;
while (u) { while (u) {
int i = ffs(u) - 1; int i = ffs(u) - 1;
nve0_fifo_isr_vm_fault(priv, i); nve0_fifo_intr_fault(priv, i);
u &= ~(1 << i); u &= ~(1 << i);
} }
@@ -529,22 +711,28 @@ nve0_fifo_intr(struct nouveau_subdev *subdev)
} }
if (stat & 0x20000000) { if (stat & 0x20000000) {
u32 units = nv_rd32(priv, 0x0025a0); u32 mask = nv_rd32(priv, 0x0025a0);
u32 u = units; u32 temp = mask;
while (u) { while (temp) {
int i = ffs(u) - 1; u32 unit = ffs(temp) - 1;
nve0_fifo_isr_subfifo_intr(priv, i); nve0_fifo_intr_pbdma(priv, unit);
u &= ~(1 << i); temp &= ~(1 << unit);
} }
nv_wr32(priv, 0x0025a0, units); nv_wr32(priv, 0x0025a0, mask);
stat &= ~0x20000000; stat &= ~0x20000000;
} }
if (stat & 0x40000000) { if (stat & 0x40000000) {
nv_warn(priv, "unknown status 0x40000000\n"); u32 mask = nv_mask(priv, 0x002a00, 0x00000000, 0x00000000);
nv_mask(priv, 0x002a00, 0x00000000, 0x00000000);
while (mask) {
u32 engn = ffs(mask) - 1;
/* runlist event, not currently used */
mask &= ~(1 << engn);
}
stat &= ~0x40000000; stat &= ~0x40000000;
} }
@@ -575,27 +763,91 @@ nve0_fifo_uevent_disable(struct nouveau_event *event, int index)
nv_mask(priv, 0x002140, 0x80000000, 0x00000000); nv_mask(priv, 0x002140, 0x80000000, 0x00000000);
} }
static int int
nve0_fifo_fini(struct nouveau_object *object, bool suspend)
{
struct nve0_fifo_priv *priv = (void *)object;
int ret;
ret = nouveau_fifo_fini(&priv->base, suspend);
if (ret)
return ret;
/* allow mmu fault interrupts, even when we're not using fifo */
nv_mask(priv, 0x002140, 0x10000000, 0x10000000);
return 0;
}
int
nve0_fifo_init(struct nouveau_object *object)
{
struct nve0_fifo_priv *priv = (void *)object;
int ret, i;
ret = nouveau_fifo_init(&priv->base);
if (ret)
return ret;
/* enable all available PBDMA units */
nv_wr32(priv, 0x000204, 0xffffffff);
priv->spoon_nr = hweight32(nv_rd32(priv, 0x000204));
nv_debug(priv, "%d PBDMA unit(s)\n", priv->spoon_nr);
/* PBDMA[n] */
for (i = 0; i < priv->spoon_nr; i++) {
nv_mask(priv, 0x04013c + (i * 0x2000), 0x10000100, 0x00000000);
nv_wr32(priv, 0x040108 + (i * 0x2000), 0xffffffff); /* INTR */
nv_wr32(priv, 0x04010c + (i * 0x2000), 0xfffffeff); /* INTREN */
}
nv_wr32(priv, 0x002254, 0x10000000 | priv->user.bar.offset >> 12);
nv_wr32(priv, 0x002a00, 0xffffffff);
nv_wr32(priv, 0x002100, 0xffffffff);
nv_wr32(priv, 0x002140, 0x3fffffff);
return 0;
}
void
nve0_fifo_dtor(struct nouveau_object *object)
{
struct nve0_fifo_priv *priv = (void *)object;
int i;
nouveau_gpuobj_unmap(&priv->user.bar);
nouveau_gpuobj_ref(NULL, &priv->user.mem);
for (i = 0; i < FIFO_ENGINE_NR; i++) {
nouveau_gpuobj_ref(NULL, &priv->engine[i].runlist[1]);
nouveau_gpuobj_ref(NULL, &priv->engine[i].runlist[0]);
}
nouveau_fifo_destroy(&priv->base);
}
int
nve0_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine, nve0_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size, struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject) struct nouveau_object **pobject)
{ {
struct nve0_fifo_impl *impl = (void *)oclass;
struct nve0_fifo_priv *priv; struct nve0_fifo_priv *priv;
int ret, i; int ret, i;
ret = nouveau_fifo_create(parent, engine, oclass, 0, 4095, &priv); ret = nouveau_fifo_create(parent, engine, oclass, 0,
impl->channels - 1, &priv);
*pobject = nv_object(priv); *pobject = nv_object(priv);
if (ret) if (ret)
return ret; return ret;
for (i = 0; i < FIFO_ENGINE_NR; i++) { for (i = 0; i < FIFO_ENGINE_NR; i++) {
ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x8000, 0x1000, ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x8000, 0x1000,
0, &priv->engine[i].playlist[0]); 0, &priv->engine[i].runlist[0]);
if (ret) if (ret)
return ret; return ret;
ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x8000, 0x1000, ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x8000, 0x1000,
0, &priv->engine[i].playlist[1]); 0, &priv->engine[i].runlist[1]);
if (ret) if (ret)
return ret; return ret;
} }
@@ -621,60 +873,14 @@ nve0_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
return 0; return 0;
} }
static void
nve0_fifo_dtor(struct nouveau_object *object)
{
struct nve0_fifo_priv *priv = (void *)object;
int i;
nouveau_gpuobj_unmap(&priv->user.bar);
nouveau_gpuobj_ref(NULL, &priv->user.mem);
for (i = 0; i < FIFO_ENGINE_NR; i++) {
nouveau_gpuobj_ref(NULL, &priv->engine[i].playlist[1]);
nouveau_gpuobj_ref(NULL, &priv->engine[i].playlist[0]);
}
nouveau_fifo_destroy(&priv->base);
}
static int
nve0_fifo_init(struct nouveau_object *object)
{
struct nve0_fifo_priv *priv = (void *)object;
int ret, i;
ret = nouveau_fifo_init(&priv->base);
if (ret)
return ret;
/* enable all available PSUBFIFOs */
nv_wr32(priv, 0x000204, 0xffffffff);
priv->spoon_nr = hweight32(nv_rd32(priv, 0x000204));
nv_debug(priv, "%d subfifo(s)\n", priv->spoon_nr);
/* PSUBFIFO[n] */
for (i = 0; i < priv->spoon_nr; i++) {
nv_mask(priv, 0x04013c + (i * 0x2000), 0x10000100, 0x00000000);
nv_wr32(priv, 0x040108 + (i * 0x2000), 0xffffffff); /* INTR */
nv_wr32(priv, 0x04010c + (i * 0x2000), 0xfffffeff); /* INTREN */
}
nv_wr32(priv, 0x002254, 0x10000000 | priv->user.bar.offset >> 12);
nv_wr32(priv, 0x002a00, 0xffffffff);
nv_wr32(priv, 0x002100, 0xffffffff);
nv_wr32(priv, 0x002140, 0x3fffffff);
return 0;
}
struct nouveau_oclass * struct nouveau_oclass *
nve0_fifo_oclass = &(struct nouveau_oclass) { nve0_fifo_oclass = &(struct nve0_fifo_impl) {
.handle = NV_ENGINE(FIFO, 0xe0), .base.handle = NV_ENGINE(FIFO, 0xe0),
.ofuncs = &(struct nouveau_ofuncs) { .base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nve0_fifo_ctor, .ctor = nve0_fifo_ctor,
.dtor = nve0_fifo_dtor, .dtor = nve0_fifo_dtor,
.init = nve0_fifo_init, .init = nve0_fifo_init,
.fini = _nouveau_fifo_fini, .fini = nve0_fifo_fini,
}, },
}; .channels = 4096,
}.base;

17
drivers/gpu/drm/nouveau/core/engine/fifo/nve0.h Normal file
View File

@@ -0,0 +1,17 @@
#ifndef __NVKM_FIFO_NVE0_H__
#define __NVKM_FIFO_NVE0_H__
#include <engine/fifo.h>
int nve0_fifo_ctor(struct nouveau_object *, struct nouveau_object *,
struct nouveau_oclass *, void *, u32,
struct nouveau_object **);
void nve0_fifo_dtor(struct nouveau_object *);
int nve0_fifo_init(struct nouveau_object *);
struct nve0_fifo_impl {
struct nouveau_oclass base;
u32 channels;
};
#endif

1408
drivers/gpu/drm/nouveau/core/engine/graph/ctxnv108.c Normal file
View File

File diff suppressed because it is too large Load Diff

7
drivers/gpu/drm/nouveau/core/engine/graph/ctxnvf0.c
View File

@@ -50,7 +50,7 @@ nvf0_grctx_init_unk40xx[] = {
{} {}
}; };
static struct nvc0_graph_init struct nvc0_graph_init
nvf0_grctx_init_unk44xx[] = { nvf0_grctx_init_unk44xx[] = {
{ 0x404404, 12, 0x04, 0x00000000 }, { 0x404404, 12, 0x04, 0x00000000 },
{ 0x404438, 1, 0x04, 0x00000000 }, { 0x404438, 1, 0x04, 0x00000000 },
@@ -62,7 +62,7 @@ nvf0_grctx_init_unk44xx[] = {
{} {}
}; };
static struct nvc0_graph_init struct nvc0_graph_init
nvf0_grctx_init_unk5bxx[] = { nvf0_grctx_init_unk5bxx[] = {
{ 0x405b00, 1, 0x04, 0x00000000 }, { 0x405b00, 1, 0x04, 0x00000000 },
{ 0x405b10, 1, 0x04, 0x00001000 }, { 0x405b10, 1, 0x04, 0x00001000 },
@@ -70,7 +70,7 @@ nvf0_grctx_init_unk5bxx[] = {
{} {}
}; };
static struct nvc0_graph_init struct nvc0_graph_init
nvf0_grctx_init_unk60xx[] = { nvf0_grctx_init_unk60xx[] = {
{ 0x406020, 1, 0x04, 0x034103c1 }, { 0x406020, 1, 0x04, 0x034103c1 },
{ 0x406028, 4, 0x04, 0x00000001 }, { 0x406028, 4, 0x04, 0x00000001 },
@@ -286,7 +286,6 @@ nvf0_grctx_init_hub[] = {
nvf0_grctx_init_unk64xx, nvf0_grctx_init_unk64xx,
nve4_grctx_init_unk80xx, nve4_grctx_init_unk80xx,
nvf0_grctx_init_unk88xx, nvf0_grctx_init_unk88xx,
nvd9_grctx_init_rop,
NULL NULL
}; };

138
drivers/gpu/drm/nouveau/core/engine/graph/fuc/com.fuc
View File

@@ -38,7 +38,7 @@ queue_put:
cmpu b32 $r8 $r9 cmpu b32 $r8 $r9
bra ne #queue_put_next bra ne #queue_put_next
mov $r15 E_CMD_OVERFLOW mov $r15 E_CMD_OVERFLOW
call #error call(error)
ret ret
// store cmd/data on queue // store cmd/data on queue
@@ -92,18 +92,16 @@ queue_get_done:
// Out: $r15 value // Out: $r15 value
// //
nv_rd32: nv_rd32:
mov $r11 0x728
shl b32 $r11 6
mov b32 $r12 $r14 mov b32 $r12 $r14
bset $r12 31 // MMIO_CTRL_PENDING bset $r12 31 // MMIO_CTRL_PENDING
iowr I[$r11 + 0x000] $r12 // MMIO_CTRL nv_iowr(NV_PGRAPH_FECS_MMIO_CTRL, 0, $r12)
nv_rd32_wait: nv_rd32_wait:
iord $r12 I[$r11 + 0x000] nv_iord($r12, NV_PGRAPH_FECS_MMIO_CTRL, 0)
xbit $r12 $r12 31 xbit $r12 $r12 31
bra ne #nv_rd32_wait bra ne #nv_rd32_wait
mov $r10 6 // DONE_MMIO_RD mov $r10 6 // DONE_MMIO_RD
call #wait_doneo call(wait_doneo)
iord $r15 I[$r11 + 0x100] // MMIO_RDVAL nv_iord($r15, NV_PGRAPH_FECS_MMIO_RDVAL, 0)
ret ret
// nv_wr32 - write 32-bit value to nv register // nv_wr32 - write 32-bit value to nv register
@@ -112,37 +110,17 @@ nv_rd32:
// $r15 value // $r15 value
// //
nv_wr32: nv_wr32:
mov $r11 0x728 nv_iowr(NV_PGRAPH_FECS_MMIO_WRVAL, 0, $r15)
shl b32 $r11 6
iowr I[$r11 + 0x200] $r15 // MMIO_WRVAL
mov b32 $r12 $r14 mov b32 $r12 $r14
bset $r12 31 // MMIO_CTRL_PENDING bset $r12 31 // MMIO_CTRL_PENDING
bset $r12 30 // MMIO_CTRL_WRITE bset $r12 30 // MMIO_CTRL_WRITE
iowr I[$r11 + 0x000] $r12 // MMIO_CTRL nv_iowr(NV_PGRAPH_FECS_MMIO_CTRL, 0, $r12)
nv_wr32_wait: nv_wr32_wait:
iord $r12 I[$r11 + 0x000] nv_iord($r12, NV_PGRAPH_FECS_MMIO_CTRL, 0)
xbit $r12 $r12 31 xbit $r12 $r12 31
bra ne #nv_wr32_wait bra ne #nv_wr32_wait
ret ret
// (re)set watchdog timer
//
// In : $r15 timeout
//
watchdog_reset:
mov $r8 0x430
shl b32 $r8 6
bset $r15 31
iowr I[$r8 + 0x000] $r15
ret
// clear watchdog timer
watchdog_clear:
mov $r8 0x430
shl b32 $r8 6
iowr I[$r8 + 0x000] $r0
ret
// wait_donez - wait on FUC_DONE bit to become clear // wait_donez - wait on FUC_DONE bit to become clear
// //
// In : $r10 bit to wait on // In : $r10 bit to wait on
@@ -163,13 +141,9 @@ wait_donez:
// //
wait_doneo: wait_doneo:
trace_set(T_WAIT); trace_set(T_WAIT);
mov $r8 0x818 nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_VAL(6), 0, $r10)
shl b32 $r8 6
iowr I[$r8 + 0x000] $r10
wait_doneo_e: wait_doneo_e:
mov $r8 0x400 nv_iord($r8, NV_PGRAPH_FECS_SIGNAL, 0)
shl b32 $r8 6
iord $r8 I[$r8 + 0x000]
xbit $r8 $r8 $r10 xbit $r8 $r8 $r10
bra e #wait_doneo_e bra e #wait_doneo_e
trace_clr(T_WAIT) trace_clr(T_WAIT)
@@ -209,21 +183,18 @@ mmctx_size:
// //
mmctx_xfer: mmctx_xfer:
trace_set(T_MMCTX) trace_set(T_MMCTX)
mov $r8 0x710
shl b32 $r8 6
clear b32 $r9 clear b32 $r9
or $r11 $r11 or $r11 $r11
bra e #mmctx_base_disabled bra e #mmctx_base_disabled
iowr I[$r8 + 0x000] $r11 // MMCTX_BASE nv_iowr(NV_PGRAPH_FECS_MMCTX_BASE, 0, $r11)
bset $r9 0 // BASE_EN bset $r9 0 // BASE_EN
mmctx_base_disabled: mmctx_base_disabled:
or $r14 $r14 or $r14 $r14
bra e #mmctx_multi_disabled bra e #mmctx_multi_disabled
iowr I[$r8 + 0x200] $r14 // MMCTX_MULTI_STRIDE nv_iowr(NV_PGRAPH_FECS_MMCTX_MULTI_STRIDE, 0, $r14)
iowr I[$r8 + 0x300] $r15 // MMCTX_MULTI_MASK nv_iowr(NV_PGRAPH_FECS_MMCTX_MULTI_MASK, 0, $r15)
bset $r9 1 // MULTI_EN bset $r9 1 // MULTI_EN
mmctx_multi_disabled: mmctx_multi_disabled:
add b32 $r8 0x100
xbit $r11 $r10 0 xbit $r11 $r10 0
shl b32 $r11 16 // DIR shl b32 $r11 16 // DIR
@@ -231,20 +202,20 @@ mmctx_xfer:
xbit $r14 $r10 1 xbit $r14 $r10 1
shl b32 $r14 17 shl b32 $r14 17
or $r11 $r14 // START_TRIGGER or $r11 $r14 // START_TRIGGER
iowr I[$r8 + 0x000] $r11 // MMCTX_CTRL nv_iowr(NV_PGRAPH_FECS_MMCTX_CTRL, 0, $r11)
// loop over the mmio list, and send requests to the hw // loop over the mmio list, and send requests to the hw
mmctx_exec_loop: mmctx_exec_loop:
// wait for space in mmctx queue // wait for space in mmctx queue
mmctx_wait_free: mmctx_wait_free:
iord $r14 I[$r8 + 0x000] // MMCTX_CTRL nv_iord($r14, NV_PGRAPH_FECS_MMCTX_CTRL, 0)
and $r14 0x1f and $r14 0x1f
bra e #mmctx_wait_free bra e #mmctx_wait_free
// queue up an entry // queue up an entry
ld b32 $r14 D[$r12] ld b32 $r14 D[$r12]
or $r14 $r9 or $r14 $r9
iowr I[$r8 + 0x300] $r14 nv_iowr(NV_PGRAPH_FECS_MMCTX_QUEUE, 0, $r14)
add b32 $r12 4 add b32 $r12 4
cmpu b32 $r12 $r13 cmpu b32 $r12 $r13
bra ne #mmctx_exec_loop bra ne #mmctx_exec_loop
@@ -253,22 +224,22 @@ mmctx_xfer:
bra ne #mmctx_stop bra ne #mmctx_stop
// wait for queue to empty // wait for queue to empty
mmctx_fini_wait: mmctx_fini_wait:
iord $r11 I[$r8 + 0x000] // MMCTX_CTRL nv_iord($r11, NV_PGRAPH_FECS_MMCTX_CTRL, 0)
and $r11 0x1f and $r11 0x1f
cmpu b32 $r11 0x10 cmpu b32 $r11 0x10
bra ne #mmctx_fini_wait bra ne #mmctx_fini_wait
mov $r10 2 // DONE_MMCTX mov $r10 2 // DONE_MMCTX
call #wait_donez call(wait_donez)
bra #mmctx_done bra #mmctx_done
mmctx_stop: mmctx_stop:
xbit $r11 $r10 0 xbit $r11 $r10 0
shl b32 $r11 16 // DIR shl b32 $r11 16 // DIR
bset $r11 12 // QLIMIT = 0x10 bset $r11 12 // QLIMIT = 0x10
bset $r11 18 // STOP_TRIGGER bset $r11 18 // STOP_TRIGGER
iowr I[$r8 + 0x000] $r11 // MMCTX_CTRL nv_iowr(NV_PGRAPH_FECS_MMCTX_CTRL, 0, $r11)
mmctx_stop_wait: mmctx_stop_wait:
// wait for STOP_TRIGGER to clear // wait for STOP_TRIGGER to clear
iord $r11 I[$r8 + 0x000] // MMCTX_CTRL nv_iord($r11, NV_PGRAPH_FECS_MMCTX_CTRL, 0)
xbit $r11 $r11 18 xbit $r11 $r11 18
bra ne #mmctx_stop_wait bra ne #mmctx_stop_wait
mmctx_done: mmctx_done:
@@ -280,28 +251,24 @@ mmctx_xfer:
strand_wait: strand_wait:
push $r10 push $r10
mov $r10 2 mov $r10 2
call #wait_donez call(wait_donez)
pop $r10 pop $r10
ret ret
// unknown - call before issuing strand commands // unknown - call before issuing strand commands
// //
strand_pre: strand_pre:
mov $r8 0x4afc mov $r9 NV_PGRAPH_FECS_STRAND_CMD_ENABLE
sethi $r8 0x20000 nv_iowr(NV_PGRAPH_FECS_STRAND_CMD, 0x3f, $r9)
mov $r9 0xc call(strand_wait)
iowr I[$r8] $r9
call #strand_wait
ret ret
// unknown - call after issuing strand commands // unknown - call after issuing strand commands
// //
strand_post: strand_post:
mov $r8 0x4afc mov $r9 NV_PGRAPH_FECS_STRAND_CMD_DISABLE
sethi $r8 0x20000 nv_iowr(NV_PGRAPH_FECS_STRAND_CMD, 0x3f, $r9)
mov $r9 0xd call(strand_wait)
iowr I[$r8] $r9
call #strand_wait
ret ret
// Selects strand set?! // Selects strand set?!
@@ -309,18 +276,14 @@ strand_post:
// In: $r14 id // In: $r14 id
// //
strand_set: strand_set:
mov $r10 0x4ffc
sethi $r10 0x20000
sub b32 $r11 $r10 0x500
mov $r12 0xf mov $r12 0xf
iowr I[$r10 + 0x000] $r12 // 0x93c = 0xf nv_iowr(NV_PGRAPH_FECS_STRAND_FILTER, 0x3f, $r12)
mov $r12 0xb mov $r12 NV_PGRAPH_FECS_STRAND_CMD_DEACTIVATE_FILTER
iowr I[$r11 + 0x000] $r12 // 0x928 = 0xb nv_iowr(NV_PGRAPH_FECS_STRAND_CMD, 0x3f, $r12)
call #strand_wait nv_iowr(NV_PGRAPH_FECS_STRAND_FILTER, 0x3f, $r14)
iowr I[$r10 + 0x000] $r14 // 0x93c = <id> mov $r12 NV_PGRAPH_FECS_STRAND_CMD_ACTIVATE_FILTER
mov $r12 0xa nv_iowr(NV_PGRAPH_FECS_STRAND_CMD, 0x3f, $r12)
iowr I[$r11 + 0x000] $r12 // 0x928 = 0xa call(strand_wait)
call #strand_wait
ret ret
// Initialise strand context data // Initialise strand context data
@@ -332,30 +295,27 @@ strand_set:
// //
strand_ctx_init: strand_ctx_init:
trace_set(T_STRINIT) trace_set(T_STRINIT)
call #strand_pre call(strand_pre)
mov $r14 3 mov $r14 3
call #strand_set call(strand_set)
mov $r10 0x46fc
sethi $r10 0x20000 clear b32 $r12
add b32 $r11 $r10 0x400 nv_iowr(NV_PGRAPH_FECS_STRAND_SELECT, 0x3f, $r12)
iowr I[$r10 + 0x100] $r0 // STRAND_FIRST_GENE = 0 mov $r12 NV_PGRAPH_FECS_STRAND_CMD_SEEK
mov $r12 1 nv_iowr(NV_PGRAPH_FECS_STRAND_CMD, 0x3f, $r12)
iowr I[$r11 + 0x000] $r12 // STRAND_CMD = LATCH_FIRST_GENE call(strand_wait)
call #strand_wait
sub b32 $r12 $r0 1 sub b32 $r12 $r0 1
iowr I[$r10 + 0x000] $r12 // STRAND_GENE_CNT = 0xffffffff nv_iowr(NV_PGRAPH_FECS_STRAND_DATA, 0x3f, $r12)
mov $r12 2 mov $r12 NV_PGRAPH_FECS_STRAND_CMD_GET_INFO
iowr I[$r11 + 0x000] $r12 // STRAND_CMD = LATCH_GENE_CNT nv_iowr(NV_PGRAPH_FECS_STRAND_CMD, 0x3f, $r12)
call #strand_wait call(strand_wait)
call #strand_post call(strand_post)
// read the size of each strand, poke the context offset of // read the size of each strand, poke the context offset of
// each into STRAND_{SAVE,LOAD}_SWBASE now, no need to worry // each into STRAND_{SAVE,LOAD}_SWBASE now, no need to worry
// about it later then. // about it later then.
mov $r8 0x880 nv_mkio($r8, NV_PGRAPH_FECS_STRAND_SAVE_SWBASE, 0x00)
shl b32 $r8 6 nv_iord($r9, NV_PGRAPH_FECS_STRANDS_CNT, 0x00)
iord $r9 I[$r8 + 0x000] // STRANDS
add b32 $r8 0x2200
shr b32 $r14 $r15 8 shr b32 $r14 $r15 8
ctx_init_strand_loop: ctx_init_strand_loop:
iowr I[$r8 + 0x000] $r14 // STRAND_SAVE_SWBASE iowr I[$r8 + 0x000] $r14 // STRAND_SAVE_SWBASE

137
drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpc.fuc
View File

@@ -58,12 +58,9 @@ mmio_list_base:
// //
error: error:
push $r14 push $r14
mov $r14 -0x67ec // 0x9814 nv_wr32(NV_PGRAPH_FECS_CC_SCRATCH_VAL(5), $r15)
sethi $r14 0x400000
call #nv_wr32 // HUB_CTXCTL_CC_SCRATCH[5] = error code
add b32 $r14 0x41c
mov $r15 1 mov $r15 1
call #nv_wr32 // HUB_CTXCTL_INTR_UP_SET nv_wr32(NV_PGRAPH_FECS_INTR_UP_SET, $r15)
pop $r14 pop $r14
ret ret
@@ -84,46 +81,40 @@ init:
mov $sp $r0 mov $sp $r0
// enable fifo access // enable fifo access
mov $r1 0x1200 mov $r2 NV_PGRAPH_GPCX_GPCCS_ACCESS_FIFO
mov $r2 2 nv_iowr(NV_PGRAPH_GPCX_GPCCS_ACCESS, 0, $r2)
iowr I[$r1 + 0x000] $r2 // FIFO_ENABLE
// setup i0 handler, and route all interrupts to it // setup i0 handler, and route all interrupts to it
mov $r1 #ih mov $r1 #ih
mov $iv0 $r1 mov $iv0 $r1
mov $r1 0x400 nv_iowr(NV_PGRAPH_GPCX_GPCCS_INTR_ROUTE, 0, $r0)
iowr I[$r1 + 0x300] $r0 // INTR_DISPATCH
// enable fifo interrupt // enable fifo interrupt
mov $r2 4 mov $r2 NV_PGRAPH_GPCX_GPCCS_INTR_EN_SET_FIFO
iowr I[$r1 + 0x000] $r2 // INTR_EN_SET nv_iowr(NV_PGRAPH_GPCX_GPCCS_INTR_EN_SET, 0, $r2)
// enable interrupts // enable interrupts
bset $flags ie0 bset $flags ie0
// figure out which GPC we are, and how many TPCs we have // figure out which GPC we are, and how many TPCs we have
mov $r1 0x608 nv_iord($r2, NV_PGRAPH_GPCX_GPCCS_UNITS, 0)
shl b32 $r1 6
iord $r2 I[$r1 + 0x000] // UNITS
mov $r3 1 mov $r3 1
and $r2 0x1f and $r2 0x1f
shl b32 $r3 $r2 shl b32 $r3 $r2
sub b32 $r3 1 sub b32 $r3 1
st b32 D[$r0 + #tpc_count] $r2 st b32 D[$r0 + #tpc_count] $r2
st b32 D[$r0 + #tpc_mask] $r3 st b32 D[$r0 + #tpc_mask] $r3
add b32 $r1 0x400 nv_iord($r2, NV_PGRAPH_GPCX_GPCCS_MYINDEX, 0)
iord $r2 I[$r1 + 0x000] // MYINDEX
st b32 D[$r0 + #gpc_id] $r2 st b32 D[$r0 + #gpc_id] $r2
#if NV_PGRAPH_GPCX_UNK__SIZE > 0 #if NV_PGRAPH_GPCX_UNK__SIZE > 0
// figure out which, and how many, UNKs are actually present // figure out which, and how many, UNKs are actually present
mov $r14 0x0c30 imm32($r14, 0x500c30)
sethi $r14 0x500000
clear b32 $r2 clear b32 $r2
clear b32 $r3 clear b32 $r3
clear b32 $r4 clear b32 $r4
init_unk_loop: init_unk_loop:
call #nv_rd32 call(nv_rd32)
cmp b32 $r15 0 cmp b32 $r15 0
bra z #init_unk_next bra z #init_unk_next
mov $r15 1 mov $r15 1
@@ -146,23 +137,21 @@ init:
// set mmctx base addresses now so we don't have to do it later, // set mmctx base addresses now so we don't have to do it later,
// they don't currently ever change // they don't currently ever change
mov $r4 0x700
shl b32 $r4 6
shr b32 $r5 $r2 8 shr b32 $r5 $r2 8
iowr I[$r4 + 0x000] $r5 // MMCTX_SAVE_SWBASE nv_iowr(NV_PGRAPH_GPCX_GPCCS_MMCTX_SAVE_SWBASE, 0, $r5)
iowr I[$r4 + 0x100] $r5 // MMCTX_LOAD_SWBASE nv_iowr(NV_PGRAPH_GPCX_GPCCS_MMCTX_LOAD_SWBASE, 0, $r5)
// calculate GPC mmio context size // calculate GPC mmio context size
ld b32 $r14 D[$r0 + #gpc_mmio_list_head] ld b32 $r14 D[$r0 + #gpc_mmio_list_head]
ld b32 $r15 D[$r0 + #gpc_mmio_list_tail] ld b32 $r15 D[$r0 + #gpc_mmio_list_tail]
call #mmctx_size call(mmctx_size)
add b32 $r2 $r15 add b32 $r2 $r15
add b32 $r3 $r15 add b32 $r3 $r15
// calculate per-TPC mmio context size // calculate per-TPC mmio context size
ld b32 $r14 D[$r0 + #tpc_mmio_list_head] ld b32 $r14 D[$r0 + #tpc_mmio_list_head]
ld b32 $r15 D[$r0 + #tpc_mmio_list_tail] ld b32 $r15 D[$r0 + #tpc_mmio_list_tail]
call #mmctx_size call(mmctx_size)
ld b32 $r14 D[$r0 + #tpc_count] ld b32 $r14 D[$r0 + #tpc_count]
mulu $r14 $r15 mulu $r14 $r15
add b32 $r2 $r14 add b32 $r2 $r14
@@ -172,7 +161,7 @@ init:
// calculate per-UNK mmio context size // calculate per-UNK mmio context size
ld b32 $r14 D[$r0 + #unk_mmio_list_head] ld b32 $r14 D[$r0 + #unk_mmio_list_head]
ld b32 $r15 D[$r0 + #unk_mmio_list_tail] ld b32 $r15 D[$r0 + #unk_mmio_list_tail]
call #mmctx_size call(mmctx_size)
ld b32 $r14 D[$r0 + #unk_count] ld b32 $r14 D[$r0 + #unk_count]
mulu $r14 $r15 mulu $r14 $r15
add b32 $r2 $r14 add b32 $r2 $r14
@@ -180,9 +169,8 @@ init:
#endif #endif
// round up base/size to 256 byte boundary (for strand SWBASE) // round up base/size to 256 byte boundary (for strand SWBASE)
add b32 $r4 0x1300
shr b32 $r3 2 shr b32 $r3 2
iowr I[$r4 + 0x000] $r3 // MMCTX_LOAD_COUNT, wtf for?!? nv_iowr(NV_PGRAPH_GPCX_GPCCS_MMCTX_LOAD_COUNT, 0, $r3) // wtf for?!
shr b32 $r2 8 shr b32 $r2 8
shr b32 $r3 6 shr b32 $r3 6
add b32 $r2 1 add b32 $r2 1
@@ -192,7 +180,7 @@ init:
// calculate size of strand context data // calculate size of strand context data
mov b32 $r15 $r2 mov b32 $r15 $r2
call #strand_ctx_init call(strand_ctx_init)
add b32 $r3 $r15 add b32 $r3 $r15
// save context size, and tell HUB we're done // save context size, and tell HUB we're done
@@ -208,7 +196,7 @@ main:
bset $flags $p0 bset $flags $p0
sleep $p0 sleep $p0
mov $r13 #cmd_queue mov $r13 #cmd_queue
call #queue_get call(queue_get)
bra $p1 #main bra $p1 #main
// 0x0000-0x0003 are all context transfers // 0x0000-0x0003 are all context transfers
@@ -224,13 +212,13 @@ main:
or $r1 $r14 or $r1 $r14
mov $flags $r1 mov $flags $r1
// transfer context data // transfer context data
call #ctx_xfer call(ctx_xfer)
bra #main bra #main
main_not_ctx_xfer: main_not_ctx_xfer:
shl b32 $r15 $r14 16 shl b32 $r15 $r14 16
or $r15 E_BAD_COMMAND or $r15 E_BAD_COMMAND
call #error call(error)
bra #main bra #main
// interrupt handler // interrupt handler
@@ -247,22 +235,20 @@ ih:
clear b32 $r0 clear b32 $r0
// incoming fifo command? // incoming fifo command?
iord $r10 I[$r0 + 0x200] // INTR nv_iord($r10, NV_PGRAPH_GPCX_GPCCS_INTR, 0)
and $r11 $r10 0x00000004 and $r11 $r10 NV_PGRAPH_GPCX_GPCCS_INTR_FIFO
bra e #ih_no_fifo bra e #ih_no_fifo
// queue incoming fifo command for later processing // queue incoming fifo command for later processing
mov $r11 0x1900
mov $r13 #cmd_queue mov $r13 #cmd_queue
iord $r14 I[$r11 + 0x100] // FIFO_CMD nv_iord($r14, NV_PGRAPH_GPCX_GPCCS_FIFO_CMD, 0)
iord $r15 I[$r11 + 0x000] // FIFO_DATA nv_iord($r15, NV_PGRAPH_GPCX_GPCCS_FIFO_DATA, 0)
call #queue_put call(queue_put)
add b32 $r11 0x400
mov $r14 1 mov $r14 1
iowr I[$r11 + 0x000] $r14 // FIFO_ACK nv_iowr(NV_PGRAPH_GPCX_GPCCS_FIFO_ACK, 0, $r14)
// ack, and wake up main() // ack, and wake up main()
ih_no_fifo: ih_no_fifo:
iowr I[$r0 + 0x100] $r10 // INTR_ACK nv_iowr(NV_PGRAPH_GPCX_GPCCS_INTR_ACK, 0, $r10)
pop $r15 pop $r15
pop $r14 pop $r14
@@ -283,9 +269,7 @@ hub_barrier_done:
mov $r15 1 mov $r15 1
ld b32 $r14 D[$r0 + #gpc_id] ld b32 $r14 D[$r0 + #gpc_id]
shl b32 $r15 $r14 shl b32 $r15 $r14
mov $r14 -0x6be8 // 0x409418 - HUB_BAR_SET nv_wr32(0x409418, $r15) // 0x409418 - HUB_BAR_SET
sethi $r14 0x400000
call #nv_wr32
ret ret
// Disables various things, waits a bit, and re-enables them.. // Disables various things, waits a bit, and re-enables them..
@@ -295,16 +279,15 @@ hub_barrier_done:
// funny things happen. // funny things happen.
// //
ctx_redswitch: ctx_redswitch:
mov $r14 0x614 mov $r15 NV_PGRAPH_GPCX_GPCCS_RED_SWITCH_POWER
shl b32 $r14 6 nv_iowr(NV_PGRAPH_GPCX_GPCCS_RED_SWITCH, 0, $r15)
mov $r15 0x020 mov $r14 8
iowr I[$r14] $r15 // GPC_RED_SWITCH = POWER
mov $r15 8
ctx_redswitch_delay: ctx_redswitch_delay:
sub b32 $r15 1 sub b32 $r14 1
bra ne #ctx_redswitch_delay bra ne #ctx_redswitch_delay
mov $r15 0xa20 or $r15 NV_PGRAPH_GPCX_GPCCS_RED_SWITCH_UNK11
iowr I[$r14] $r15 // GPC_RED_SWITCH = UNK11, ENABLE, POWER or $r15 NV_PGRAPH_GPCX_GPCCS_RED_SWITCH_ENABLE
nv_iowr(NV_PGRAPH_GPCX_GPCCS_RED_SWITCH, 0, $r15)
ret ret
// Transfer GPC context data between GPU and storage area // Transfer GPC context data between GPU and storage area
@@ -317,46 +300,37 @@ ctx_redswitch:
// //
ctx_xfer: ctx_xfer:
// set context base address // set context base address
mov $r1 0xa04 nv_iowr(NV_PGRAPH_GPCX_GPCCS_MEM_BASE, 0, $r15)
shl b32 $r1 6
iowr I[$r1 + 0x000] $r15// MEM_BASE
bra not $p1 #ctx_xfer_not_load bra not $p1 #ctx_xfer_not_load
call #ctx_redswitch call(ctx_redswitch)
ctx_xfer_not_load: ctx_xfer_not_load:
// strands // strands
mov $r1 0x4afc call(strand_pre)
sethi $r1 0x20000 clear b32 $r2
mov $r2 0xc nv_iowr(NV_PGRAPH_GPCX_GPCCS_STRAND_SELECT, 0x3f, $r2)
iowr I[$r1] $r2 // STRAND_CMD(0x3f) = 0x0c xbit $r2 $flags $p1 // SAVE/LOAD
call #strand_wait add b32 $r2 NV_PGRAPH_GPCX_GPCCS_STRAND_CMD_SAVE
mov $r2 0x47fc nv_iowr(NV_PGRAPH_GPCX_GPCCS_STRAND_CMD, 0x3f, $r2)
sethi $r2 0x20000
iowr I[$r2] $r0 // STRAND_FIRST_GENE(0x3f) = 0x00
xbit $r2 $flags $p1
add b32 $r2 3
iowr I[$r1] $r2 // STRAND_CMD(0x3f) = 0x03/0x04 (SAVE/LOAD)
// mmio context // mmio context
xbit $r10 $flags $p1 // direction xbit $r10 $flags $p1 // direction
or $r10 2 // first or $r10 2 // first
mov $r11 0x0000 imm32($r11,0x500000)
sethi $r11 0x500000
ld b32 $r12 D[$r0 + #gpc_id] ld b32 $r12 D[$r0 + #gpc_id]
shl b32 $r12 15 shl b32 $r12 15
add b32 $r11 $r12 // base = NV_PGRAPH_GPCn add b32 $r11 $r12 // base = NV_PGRAPH_GPCn
ld b32 $r12 D[$r0 + #gpc_mmio_list_head] ld b32 $r12 D[$r0 + #gpc_mmio_list_head]
ld b32 $r13 D[$r0 + #gpc_mmio_list_tail] ld b32 $r13 D[$r0 + #gpc_mmio_list_tail]
mov $r14 0 // not multi mov $r14 0 // not multi
call #mmctx_xfer call(mmctx_xfer)
// per-TPC mmio context // per-TPC mmio context
xbit $r10 $flags $p1 // direction xbit $r10 $flags $p1 // direction
#if !NV_PGRAPH_GPCX_UNK__SIZE #if !NV_PGRAPH_GPCX_UNK__SIZE
or $r10 4 // last or $r10 4 // last
#endif #endif
mov $r11 0x4000 imm32($r11, 0x504000)
sethi $r11 0x500000 // base = NV_PGRAPH_GPC0_TPC0
ld b32 $r12 D[$r0 + #gpc_id] ld b32 $r12 D[$r0 + #gpc_id]
shl b32 $r12 15 shl b32 $r12 15
add b32 $r11 $r12 // base = NV_PGRAPH_GPCn_TPC0 add b32 $r11 $r12 // base = NV_PGRAPH_GPCn_TPC0
@@ -364,14 +338,13 @@ ctx_xfer:
ld b32 $r13 D[$r0 + #tpc_mmio_list_tail] ld b32 $r13 D[$r0 + #tpc_mmio_list_tail]
ld b32 $r15 D[$r0 + #tpc_mask] ld b32 $r15 D[$r0 + #tpc_mask]
mov $r14 0x800 // stride = 0x800 mov $r14 0x800 // stride = 0x800
call #mmctx_xfer call(mmctx_xfer)
#if NV_PGRAPH_GPCX_UNK__SIZE > 0 #if NV_PGRAPH_GPCX_UNK__SIZE > 0
// per-UNK mmio context // per-UNK mmio context
xbit $r10 $flags $p1 // direction xbit $r10 $flags $p1 // direction
or $r10 4 // last or $r10 4 // last
mov $r11 0x3000 imm32($r11, 0x503000)
sethi $r11 0x500000 // base = NV_PGRAPH_GPC0_UNK0
ld b32 $r12 D[$r0 + #gpc_id] ld b32 $r12 D[$r0 + #gpc_id]
shl b32 $r12 15 shl b32 $r12 15
add b32 $r11 $r12 // base = NV_PGRAPH_GPCn_UNK0 add b32 $r11 $r12 // base = NV_PGRAPH_GPCn_UNK0
@@ -379,11 +352,11 @@ ctx_xfer:
ld b32 $r13 D[$r0 + #unk_mmio_list_tail] ld b32 $r13 D[$r0 + #unk_mmio_list_tail]
ld b32 $r15 D[$r0 + #unk_mask] ld b32 $r15 D[$r0 + #unk_mask]
mov $r14 0x200 // stride = 0x200 mov $r14 0x200 // stride = 0x200
call #mmctx_xfer call(mmctx_xfer)
#endif #endif
// wait for strands to finish // wait for strands to finish
call #strand_wait call(strand_wait)
// if load, or a save without a load following, do some // if load, or a save without a load following, do some
// unknown stuff that's done after finishing a block of // unknown stuff that's done after finishing a block of
@@ -391,14 +364,10 @@ ctx_xfer:
bra $p1 #ctx_xfer_post bra $p1 #ctx_xfer_post
bra not $p2 #ctx_xfer_done bra not $p2 #ctx_xfer_done
ctx_xfer_post: ctx_xfer_post:
mov $r1 0x4afc call(strand_post)
sethi $r1 0x20000
mov $r2 0xd
iowr I[$r1] $r2 // STRAND_CMD(0x3f) = 0x0d
call #strand_wait
// mark completion in HUB's barrier // mark completion in HUB's barrier
ctx_xfer_done: ctx_xfer_done:
call #hub_barrier_done call(hub_barrier_done)
ret ret
#endif #endif

42
drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnv108.fuc5 Normal file
View File

@@ -0,0 +1,42 @@
/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
#define NV_PGRAPH_GPCX_UNK__SIZE 0x00000001
#define CHIPSET GK208
#include "macros.fuc"
.section #nv108_grgpc_data
#define INCLUDE_DATA
#include "com.fuc"
#include "gpc.fuc"
#undef INCLUDE_DATA
.section #nv108_grgpc_code
#define INCLUDE_CODE
bra #init
#include "com.fuc"
#include "gpc.fuc"
.align 256
#undef INCLUDE_CODE

473
drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnv108.fuc5.h Normal file
View File

@@ -0,0 +1,473 @@
uint32_t nv108_grgpc_data[] = {
/* 0x0000: gpc_mmio_list_head */
0x0000006c,
/* 0x0004: gpc_mmio_list_tail */
/* 0x0004: tpc_mmio_list_head */
0x0000006c,
/* 0x0008: tpc_mmio_list_tail */
/* 0x0008: unk_mmio_list_head */
0x0000006c,
/* 0x000c: unk_mmio_list_tail */
0x0000006c,
/* 0x0010: gpc_id */
0x00000000,
/* 0x0014: tpc_count */
0x00000000,
/* 0x0018: tpc_mask */
0x00000000,
/* 0x001c: unk_count */
0x00000000,
/* 0x0020: unk_mask */
0x00000000,
/* 0x0024: cmd_queue */
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
};
uint32_t nv108_grgpc_code[] = {
0x03140ef5,
/* 0x0004: queue_put */
0x9800d898,
0x86f001d9,
0xf489a408,
0x020f0b1b,
0x0002f87e,
/* 0x001a: queue_put_next */
0x98c400f8,
0x0384b607,
0xb6008dbb,
0x8eb50880,
0x018fb500,
0xf00190b6,
0xd9b50f94,
/* 0x0037: queue_get */
0xf400f801,
0xd8980131,
0x01d99800,
0x0bf489a4,
0x0789c421,
0xbb0394b6,
0x90b6009d,
0x009e9808,
0xb6019f98,
0x84f00180,
0x00d8b50f,
/* 0x0063: queue_get_done */
0xf80132f4,
/* 0x0065: nv_rd32 */
0xf0ecb200,
0x00801fc9,
0x0cf601ca,
/* 0x0073: nv_rd32_wait */
0x8c04bd00,
0xcf01ca00,
0xccc800cc,
0xf61bf41f,
0xec7e060a,
0x008f0000,
0xffcf01cb,
/* 0x008f: nv_wr32 */
0x8000f800,
0xf601cc00,
0x04bd000f,
0xc9f0ecb2,
0x1ec9f01f,
0x01ca0080,
0xbd000cf6,
/* 0x00a9: nv_wr32_wait */
0xca008c04,
0x00cccf01,
0xf41fccc8,
0x00f8f61b,
/* 0x00b8: wait_donez */
0x99f094bd,
0x37008000,
0x0009f602,
0x008004bd,
0x0af60206,
/* 0x00cf: wait_donez_ne */
0x8804bd00,
0xcf010000,
0x8aff0088,
0xf61bf488,
0x99f094bd,
0x17008000,
0x0009f602,
0x00f804bd,
/* 0x00ec: wait_doneo */
0x99f094bd,
0x37008000,
0x0009f602,
0x008004bd,
0x0af60206,
/* 0x0103: wait_doneo_e */
0x8804bd00,
0xcf010000,
0x8aff0088,
0xf60bf488,
0x99f094bd,
0x17008000,
0x0009f602,
0x00f804bd,
/* 0x0120: mmctx_size */
/* 0x0122: nv_mmctx_size_loop */
0xe89894bd,
0x1a85b600,
0xb60180b6,
0x98bb0284,
0x04e0b600,
0x1bf4efa4,
0xf89fb2ec,
/* 0x013d: mmctx_xfer */
0xf094bd00,
0x00800199,
0x09f60237,
0xbd04bd00,
0x05bbfd94,
0x800f0bf4,
0xf601c400,
0x04bd000b,
/* 0x015f: mmctx_base_disabled */
0xfd0099f0,
0x0bf405ee,
0xc6008018,
0x000ef601,
0x008004bd,
0x0ff601c7,
0xf004bd00,
/* 0x017a: mmctx_multi_disabled */
0xabc80199,
0x10b4b600,
0xc80cb9f0,
0xe4b601ae,
0x05befd11,
0x01c50080,
0xbd000bf6,
/* 0x0195: mmctx_exec_loop */
/* 0x0195: mmctx_wait_free */
0xc5008e04,
0x00eecf01,
0xf41fe4f0,
0xce98f60b,
0x05e9fd00,
0x01c80080,
0xbd000ef6,
0x04c0b604,
0x1bf4cda4,
0x02abc8df,
/* 0x01bf: mmctx_fini_wait */
0x8b1c1bf4,
0xcf01c500,
0xb4f000bb,
0x10b4b01f,
0x0af31bf4,
0x00b87e02,
0x250ef400,
/* 0x01d8: mmctx_stop */
0xb600abc8,
0xb9f010b4,
0x12b9f00c,
0x01c50080,
0xbd000bf6,
/* 0x01ed: mmctx_stop_wait */
0xc5008b04,
0x00bbcf01,
0xf412bbc8,
/* 0x01fa: mmctx_done */
0x94bdf61b,
0x800199f0,
0xf6021700,
0x04bd0009,
/* 0x020a: strand_wait */
0xa0f900f8,
0xb87e020a,
0xa0fc0000,
/* 0x0216: strand_pre */
0x0c0900f8,
0x024afc80,
0xbd0009f6,
0x020a7e04,
/* 0x0227: strand_post */
0x0900f800,
0x4afc800d,
0x0009f602,
0x0a7e04bd,
0x00f80002,
/* 0x0238: strand_set */
0xfc800f0c,
0x0cf6024f,
0x0c04bd00,
0x4afc800b,
0x000cf602,
0xfc8004bd,
0x0ef6024f,
0x0c04bd00,
0x4afc800a,
0x000cf602,
0x0a7e04bd,
0x00f80002,
/* 0x0268: strand_ctx_init */
0x99f094bd,
0x37008003,
0x0009f602,
0x167e04bd,
0x030e0002,
0x0002387e,
0xfc80c4bd,
0x0cf60247,
0x0c04bd00,
0x4afc8001,
0x000cf602,
0x0a7e04bd,
0x0c920002,
0x46fc8001,
0x000cf602,
0x020c04bd,
0x024afc80,
0xbd000cf6,
0x020a7e04,
0x02277e00,
0x42008800,
0x20008902,
0x0099cf02,
/* 0x02c7: ctx_init_strand_loop */
0xf608fe95,
0x8ef6008e,
0x808acf40,
0xb606a5b6,
0xeabb01a0,
0x0480b600,
0xf40192b6,
0xe4b6e81b,
0xf2efbc08,
0x99f094bd,
0x17008003,
0x0009f602,
0x00f804bd,
/* 0x02f8: error */
0xffb2e0f9,
0x4098148e,
0x00008f7e,
0xffb2010f,
0x409c1c8e,
0x00008f7e,
0x00f8e0fc,
/* 0x0314: init */
0x04fe04bd,
0x40020200,
0x02f61200,
0x4104bd00,
0x10fe0465,
0x07004000,
0xbd0000f6,
0x40040204,
0x02f60400,
0xf404bd00,
0x00821031,
0x22cf0182,
0xf0010300,
0x32bb1f24,
0x0132b604,
0xb50502b5,
0x00820603,
0x22cf0186,
0x0402b500,
0x500c308e,
0x34bd24bd,
/* 0x036a: init_unk_loop */
0x657e44bd,
0xf6b00000,
0x0e0bf400,
0xf2bb010f,
0x054ffd04,
/* 0x037f: init_unk_next */
0xb60130b6,
0xe0b60120,
0x0126b004,
/* 0x038b: init_unk_done */
0xb5e21bf4,
0x04b50703,
0x01008208,
0x0022cf02,
0x259534bd,
0xc0008008,
0x0005f601,
0x008004bd,
0x05f601c1,
0x9804bd00,
0x0f98000e,
0x01207e01,
0x002fbb00,
0x98003fbb,
0x0f98010e,
0x01207e02,
0x050e9800,
0xbb00effd,
0x3ebb002e,
0x020e9800,
0x7e030f98,
0x98000120,
0xeffd070e,
0x002ebb00,
0xb6003ebb,
0x00800235,
0x03f601d3,
0xb604bd00,
0x35b60825,
0x0120b606,
0xb60130b6,
0x34b60824,
0x7e2fb208,
0xbb000268,
0x0080003f,
0x03f60201,
0xbd04bd00,
0x1f29f024,
0x02300080,
0xbd0002f6,
/* 0x0429: main */
0x0031f404,
0x0d0028f4,
0x00377e24,
0xf401f400,
0xf404e4b0,
0x81fe1d18,
0xbd060201,
0x0412fd20,
0xfd01e4b6,
0x18fe051e,
0x04fc7e00,
0xd40ef400,
/* 0x0458: main_not_ctx_xfer */
0xf010ef94,
0xf87e01f5,
0x0ef40002,
/* 0x0465: ih */
0xfe80f9c7,
0x80f90188,
0xa0f990f9,
0xd0f9b0f9,
0xf0f9e0f9,
0x004a04bd,
0x00aacf02,
0xf404abc4,
0x240d1f0b,
0xcf1a004e,
0x004f00ee,
0x00ffcf19,
0x0000047e,
0x0040010e,
0x000ef61d,
/* 0x04a2: ih_no_fifo */
0x004004bd,
0x000af601,
0xf0fc04bd,
0xd0fce0fc,
0xa0fcb0fc,
0x80fc90fc,
0xfc0088fe,
0x0032f480,
/* 0x04c2: hub_barrier_done */
0x010f01f8,
0xbb040e98,
0xffb204fe,
0x4094188e,
0x00008f7e,
/* 0x04d6: ctx_redswitch */
0x200f00f8,
0x01850080,
0xbd000ff6,
/* 0x04e3: ctx_redswitch_delay */
0xb6080e04,
0x1bf401e2,
0x00f5f1fd,
0x00f5f108,
0x85008002,
0x000ff601,
0x00f804bd,
/* 0x04fc: ctx_xfer */
0x02810080,
0xbd000ff6,
0x0711f404,
0x0004d67e,
/* 0x050c: ctx_xfer_not_load */
0x0002167e,
0xfc8024bd,
0x02f60247,
0xf004bd00,
0x20b6012c,
0x4afc8003,
0x0002f602,
0xacf004bd,
0x02a5f001,
0x5000008b,
0xb6040c98,
0xbcbb0fc4,
0x000c9800,
0x0e010d98,
0x013d7e00,
0x01acf000,
0x5040008b,
0xb6040c98,
0xbcbb0fc4,
0x010c9800,
0x98020d98,
0x004e060f,
0x013d7e08,
0x01acf000,
0x8b04a5f0,
0x98503000,
0xc4b6040c,
0x00bcbb0f,
0x98020c98,
0x0f98030d,
0x02004e08,
0x00013d7e,
0x00020a7e,
0xf40601f4,
/* 0x0596: ctx_xfer_post */
0x277e0712,
/* 0x059a: ctx_xfer_done */
0xc27e0002,
0x00f80004,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
};

708
drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc.h
View File

@@ -37,14 +37,14 @@ uint32_t nvc0_grgpc_data[] = {
}; };
uint32_t nvc0_grgpc_code[] = { uint32_t nvc0_grgpc_code[] = {
0x03180ef5, 0x03a10ef5,
/* 0x0004: queue_put */ /* 0x0004: queue_put */
0x9800d898, 0x9800d898,
0x86f001d9, 0x86f001d9,
0x0489b808, 0x0489b808,
0xf00c1bf4, 0xf00c1bf4,
0x21f502f7, 0x21f502f7,
0x00f802fe, 0x00f8037e,
/* 0x001c: queue_put_next */ /* 0x001c: queue_put_next */
0xb60798c4, 0xb60798c4,
0x8dbb0384, 0x8dbb0384,
@@ -68,184 +68,214 @@ uint32_t nvc0_grgpc_code[] = {
/* 0x0066: queue_get_done */ /* 0x0066: queue_get_done */
0x00f80132, 0x00f80132,
/* 0x0068: nv_rd32 */ /* 0x0068: nv_rd32 */
0x0728b7f1, 0xf002ecb9,
0xb906b4b6, 0x07f11fc9,
0xc9f002ec, 0x03f0ca00,
0x00bcd01f, 0x000cd001,
/* 0x0078: nv_rd32_wait */ /* 0x007a: nv_rd32_wait */
0xc800bccf, 0xc7f104bd,
0x1bf41fcc, 0xc3f0ca00,
0x06a7f0fa, 0x00cccf01,
0x010921f5, 0xf41fccc8,
0xf840bfcf, 0xa7f0f31b,
/* 0x008d: nv_wr32 */ 0x1021f506,
0x28b7f100, 0x00f7f101,
0x06b4b607, 0x01f3f0cb,
0xb980bfd0, 0xf800ffcf,
0xc9f002ec, /* 0x009d: nv_wr32 */
0x1ec9f01f, 0x0007f100,
/* 0x00a3: nv_wr32_wait */ 0x0103f0cc,
0xcf00bcd0, 0xbd000fd0,
0xccc800bc, 0x02ecb904,
0xfa1bf41f, 0xf01fc9f0,
/* 0x00ae: watchdog_reset */ 0x07f11ec9,
0x87f100f8, 0x03f0ca00,
0x84b60430, 0x000cd001,
0x1ff9f006, /* 0x00be: nv_wr32_wait */
0xf8008fd0, 0xc7f104bd,
/* 0x00bd: watchdog_clear */ 0xc3f0ca00,
0x3087f100, 0x00cccf01,
0x0684b604, 0xf41fccc8,
0xf80080d0, 0x00f8f31b,
/* 0x00c9: wait_donez */ /* 0x00d0: wait_donez */
0xf094bd00,
0x07f10099,
0x03f00f00,
0x0009d002,
0x07f104bd,
0x03f00600,
0x000ad002,
/* 0x00e6: wait_donez_ne */
0x87f104bd,
0x83f00000,
0x0088cf01,
0xf4888aff,
0x94bdf31b,
0xf10099f0,
0xf0170007,
0x09d00203,
0xf804bd00,
/* 0x0109: wait_doneo */
0xf094bd00,
0x07f10099,
0x03f00f00,
0x0009d002,
0x87f104bd,
0x84b60818,
0x008ad006,
/* 0x0124: wait_doneo_e */
0x040087f1,
0xcf0684b6,
0x8aff0088,
0xf30bf488,
0x99f094bd, 0x99f094bd,
0x0007f100, 0x0007f100,
0x0203f017, 0x0203f00f,
0xbd0009d0, 0xbd0009d0,
/* 0x0147: mmctx_size */ 0x0007f104,
0xbd00f804, 0x0203f006,
/* 0x0149: nv_mmctx_size_loop */ 0xbd000ad0,
0x00e89894, /* 0x00ed: wait_donez_ne */
0xb61a85b6, 0x0087f104,
0x84b60180, 0x0183f000,
0x0098bb02, 0xff0088cf,
0xb804e0b6, 0x1bf4888a,
0x1bf404ef, 0xf094bdf3,
0x029fb9eb, 0x07f10099,
/* 0x0166: mmctx_xfer */ 0x03f01700,
0x94bd00f8, 0x0009d002,
0xf10199f0, 0x00f804bd,
0xf00f0007, /* 0x0110: wait_doneo */
0x09d00203, 0x99f094bd,
0xf104bd00, 0x0007f100,
0xb6071087, 0x0203f00f,
0x94bd0684, 0xbd0009d0,
0xf405bbfd, 0x0007f104,
0x8bd0090b, 0x0203f006,
0x0099f000, 0xbd000ad0,
/* 0x018c: mmctx_base_disabled */ /* 0x012d: wait_doneo_e */
0xf405eefd, 0x0087f104,
0x8ed00c0b, 0x0183f000,
0xc08fd080, 0xff0088cf,
/* 0x019b: mmctx_multi_disabled */ 0x0bf4888a,
0xb70199f0, 0xf094bdf3,
0xc8010080, 0x07f10099,
0x03f01700,
0x0009d002,
0x00f804bd,
/* 0x0150: mmctx_size */
/* 0x0152: nv_mmctx_size_loop */
0xe89894bd,
0x1a85b600,
0xb60180b6,
0x98bb0284,
0x04e0b600,
0xf404efb8,
0x9fb9eb1b,
/* 0x016f: mmctx_xfer */
0xbd00f802,
0x0199f094,
0x0f0007f1,
0xd00203f0,
0x04bd0009,
0xbbfd94bd,
0x120bf405,
0xc40007f1,
0xd00103f0,
0x04bd000b,
/* 0x0197: mmctx_base_disabled */
0xfd0099f0,
0x0bf405ee,
0x0007f11e,
0x0103f0c6,
0xbd000ed0,
0x0007f104,
0x0103f0c7,
0xbd000fd0,
0x0199f004,
/* 0x01b8: mmctx_multi_disabled */
0xb600abc8,
0xb9f010b4,
0x01aec80c,
0xfd11e4b6,
0x07f105be,
0x03f0c500,
0x000bd001,
/* 0x01d6: mmctx_exec_loop */
/* 0x01d6: mmctx_wait_free */
0xe7f104bd,
0xe3f0c500,
0x00eecf01,
0xf41fe4f0,
0xce98f30b,
0x05e9fd00,
0xc80007f1,
0xd00103f0,
0x04bd000e,
0xb804c0b6,
0x1bf404cd,
0x02abc8d8,
/* 0x0207: mmctx_fini_wait */
0xf11f1bf4,
0xf0c500b7,
0xbbcf01b3,
0x1fb4f000,
0xf410b4b0,
0xa7f0f01b,
0xd021f402,
/* 0x0223: mmctx_stop */
0xc82b0ef4,
0xb4b600ab, 0xb4b600ab,
0x0cb9f010, 0x0cb9f010,
0xb601aec8, 0xf112b9f0,
0xbefd11e4, 0xf0c50007,
0x008bd005, 0x0bd00103,
/* 0x01b4: mmctx_exec_loop */ /* 0x023b: mmctx_stop_wait */
/* 0x01b4: mmctx_wait_free */ 0xf104bd00,
0xf0008ecf, 0xf0c500b7,
0x0bf41fe4, 0xbbcf01b3,
0x00ce98fa, 0x12bbc800,
0xd005e9fd, /* 0x024b: mmctx_done */
0xc0b6c08e, 0xbdf31bf4,
0x04cdb804, 0x0199f094,
0xc8e81bf4, 0x170007f1,
0x1bf402ab, 0xd00203f0,
/* 0x01d5: mmctx_fini_wait */ 0x04bd0009,
0x008bcf18, /* 0x025e: strand_wait */
0xb01fb4f0, 0xa0f900f8,
0x1bf410b4, 0xf402a7f0,
0x02a7f0f7, 0xa0fcd021,
0xf4c921f4, /* 0x026a: strand_pre */
/* 0x01ea: mmctx_stop */ 0x97f000f8,
0xabc81b0e, 0xfc07f10c,
0x10b4b600, 0x0203f04a,
0xf00cb9f0, 0xbd0009d0,
0x8bd012b9, 0x5e21f504,
/* 0x01f9: mmctx_stop_wait */ /* 0x027f: strand_post */
0x008bcf00, 0xf000f802,
0xf412bbc8, 0x07f10d97,
/* 0x0202: mmctx_done */ 0x03f04afc,
0x94bdfa1b,
0xf10199f0,
0xf0170007,
0x09d00203,
0xf804bd00,
/* 0x0215: strand_wait */
0xf0a0f900,
0x21f402a7,
0xf8a0fcc9,
/* 0x0221: strand_pre */
0xfc87f100,
0x0283f04a,
0xd00c97f0,
0x21f50089,
0x00f80215,
/* 0x0234: strand_post */
0x4afc87f1,
0xf00283f0,
0x89d00d97,
0x1521f500,
/* 0x0247: strand_set */
0xf100f802,
0xf04ffca7,
0xaba202a3,
0xc7f00500,
0x00acd00f,
0xd00bc7f0,
0x21f500bc,
0xaed00215,
0x0ac7f000,
0xf500bcd0,
0xf8021521,
/* 0x0271: strand_ctx_init */
0xf094bd00,
0x07f10399,
0x03f00f00,
0x0009d002, 0x0009d002,
0x21f504bd, 0x21f504bd,
0xe7f00221, 0x00f8025e,
0x4721f503, /* 0x0294: strand_set */
0xfca7f102, 0xf10fc7f0,
0x02a3f046, 0xf04ffc07,
0x0400aba0, 0x0cd00203,
0xf040a0d0, 0xf004bd00,
0xbcd001c7, 0x07f10bc7,
0x1521f500, 0x03f04afc,
0x010c9202, 0x000cd002,
0xf000acd0, 0x07f104bd,
0xbcd002c7, 0x03f04ffc,
0x1521f500, 0x000ed002,
0x3421f502, 0xc7f004bd,
0x8087f102, 0xfc07f10a,
0x0684b608, 0x0203f04a,
0xb70089cf, 0xbd000cd0,
0x95220080, 0x5e21f504,
/* 0x02ca: ctx_init_strand_loop */ /* 0x02d3: strand_ctx_init */
0xbd00f802,
0x0399f094,
0x0f0007f1,
0xd00203f0,
0x04bd0009,
0x026a21f5,
0xf503e7f0,
0xbd029421,
0xfc07f1c4,
0x0203f047,
0xbd000cd0,
0x01c7f004,
0x4afc07f1,
0xd00203f0,
0x04bd000c,
0x025e21f5,
0xf1010c92,
0xf046fc07,
0x0cd00203,
0xf004bd00,
0x07f102c7,
0x03f04afc,
0x000cd002,
0x21f504bd,
0x21f5025e,
0x87f1027f,
0x83f04200,
0x0097f102,
0x0293f020,
0x950099cf,
/* 0x034a: ctx_init_strand_loop */
0x8ed008fe, 0x8ed008fe,
0x408ed000, 0x408ed000,
0xb6808acf, 0xb6808acf,
@@ -259,167 +289,199 @@ uint32_t nvc0_grgpc_code[] = {
0x170007f1, 0x170007f1,
0xd00203f0, 0xd00203f0,
0x04bd0009, 0x04bd0009,
/* 0x02fe: error */ /* 0x037e: error */
0xe0f900f8, 0xe0f900f8,
0x9814e7f1, 0xf102ffb9,
0xf440e3f0, 0xf09814e7,
0xe0b78d21, 0x21f440e3,
0xf7f0041c, 0x01f7f09d,
0x8d21f401, 0xf102ffb9,
0x00f8e0fc, 0xf09c1ce7,
/* 0x0318: init */ 0x21f440e3,
0x04fe04bd, 0xf8e0fc9d,
0x0017f100, /* 0x03a1: init */
0x0227f012, 0xfe04bd00,
0xf10012d0, 0x27f00004,
0xfe042617, 0x0007f102,
0x17f10010, 0x0003f012,
0x10d00400, 0xbd0002d0,
0x0427f0c0, 0xd517f104,
0xf40012d0, 0x0010fe04,
0x17f11031, 0x070007f1,
0x14b60608, 0xd00003f0,
0x0012cf06, 0x04bd0000,
0xf10427f0,
0xf0040007,
0x02d00003,
0xf404bd00,
0x27f11031,
0x23f08200,
0x0022cf01,
0xf00137f0, 0xf00137f0,
0x32bb1f24, 0x32bb1f24,
0x0132b604, 0x0132b604,
0x80050280, 0x80050280,
0x10b70603, 0x27f10603,
0x12cf0400, 0x23f08600,
0x04028000, 0x0022cf01,
0x010027f1, 0xf1040280,
0xcf0223f0, 0xf0010027,
0x34bd0022, 0x22cf0223,
0x070047f1, 0x9534bd00,
0x950644b6, 0x07f10825,
0x45d00825, 0x03f0c000,
0x4045d000, 0x0005d001,
0x98000e98, 0x07f104bd,
0x21f5010f, 0x03f0c100,
0x2fbb0147, 0x0005d001,
0x003fbb00, 0x0e9804bd,
0x98010e98, 0x010f9800,
0x21f5020f, 0x015021f5,
0x0e980147, 0xbb002fbb,
0x00effd05, 0x0e98003f,
0xbb002ebb, 0x020f9801,
0x40b7003e, 0x015021f5,
0x35b61300, 0xfd050e98,
0x0043d002, 0x2ebb00ef,
0xb60825b6, 0x003ebb00,
0x20b60635, 0xf10235b6,
0x0130b601, 0xf0d30007,
0xb60824b6, 0x03d00103,
0x2fb90834, 0xb604bd00,
0x7121f502, 0x35b60825,
0x003fbb02, 0x0120b606,
0x010007f1, 0xb60130b6,
0x34b60824,
0x022fb908,
0x02d321f5,
0xf1003fbb,
0xf0010007,
0x03d00203,
0xbd04bd00,
0x1f29f024,
0x080007f1,
0xd00203f0, 0xd00203f0,
0x04bd0003, 0x04bd0002,
0x29f024bd, /* 0x0498: main */
0x0007f11f, 0xf40031f4,
0x0203f008, 0xd7f00028,
0xbd0002d0, 0x3921f41c,
/* 0x03e9: main */ 0xb0f401f4,
0x0031f404, 0x18f404e4,
0xf00028f4, 0x0181fe1e,
0x21f41cd7, 0xbd0627f0,
0xf401f439, 0x0412fd20,
0xf404e4b0, 0xfd01e4b6,
0x81fe1e18, 0x18fe051e,
0x0627f001, 0x8d21f500,
0x12fd20bd, 0xd30ef405,
0x01e4b604, /* 0x04c8: main_not_ctx_xfer */
0xfe051efd, 0xf010ef94,
0x21f50018, 0x21f501f5,
0x0ef404ad, 0x0ef4037e,
/* 0x0419: main_not_ctx_xfer */ /* 0x04d5: ih */
0x10ef94d3, 0xfe80f9c6,
0xf501f5f0, 0x80f90188,
0xf402fe21, 0xa0f990f9,
/* 0x0426: ih */ 0xd0f9b0f9,
0x80f9c60e, 0xf0f9e0f9,
0xf90188fe, 0xa7f104bd,
0xf990f980, 0xa3f00200,
0xf9b0f9a0, 0x00aacf00,
0xf9e0f9d0, 0xf404abc4,
0xcf04bdf0, 0xd7f02c0b,
0xabc4800a, 0x00e7f11c,
0x1d0bf404, 0x00e3f01a,
0x1900b7f1, 0xf100eecf,
0xcf1cd7f0, 0xf01900f7,
0xbfcf40be, 0xffcf00f3,
0x0421f400, 0x0421f400,
0x0400b0b7, 0xf101e7f0,
0xd001e7f0, 0xf01d0007,
/* 0x045e: ih_no_fifo */ 0x0ed00003,
0x0ad000be, /* 0x0523: ih_no_fifo */
0xfcf0fc40, 0xf104bd00,
0xfcd0fce0, 0xf0010007,
0xfca0fcb0, 0x0ad00003,
0xfe80fc90, 0xfc04bd00,
0x80fc0088, 0xfce0fcf0,
0xf80032f4, 0xfcb0fcd0,
/* 0x0479: hub_barrier_done */ 0xfc90fca0,
0x01f7f001, 0x0088fe80,
0xbb040e98, 0x32f480fc,
0xe7f104fe, /* 0x0547: hub_barrier_done */
0xe3f09418, 0xf001f800,
0x8d21f440, 0x0e9801f7,
/* 0x048e: ctx_redswitch */ 0x04febb04,
0xe7f100f8, 0xf102ffb9,
0xe4b60614, 0xf09418e7,
0x20f7f006, 0x21f440e3,
0xf000efd0, /* 0x055f: ctx_redswitch */
/* 0x049e: ctx_redswitch_delay */ 0xf000f89d,
0xf2b608f7, 0x07f120f7,
0xfd1bf401, 0x03f08500,
0x0a20f7f1, 0x000fd001,
0xf800efd0, 0xe7f004bd,
/* 0x04ad: ctx_xfer */ /* 0x0571: ctx_redswitch_delay */
0x0417f100, 0x01e2b608,
0x0614b60a, 0xf1fd1bf4,
0xf4001fd0, 0xf10800f5,
0x21f50711, 0xf10200f5,
/* 0x04be: ctx_xfer_not_load */ 0xf0850007,
0x17f1048e, 0x0fd00103,
0x13f04afc, 0xf804bd00,
0x0c27f002, /* 0x058d: ctx_xfer */
0xf50012d0, 0x0007f100,
0xf1021521, 0x0203f081,
0xf047fc27, 0xbd000fd0,
0x20d00223, 0x0711f404,
0x012cf000, 0x055f21f5,
0xd00320b6, /* 0x05a0: ctx_xfer_not_load */
0xacf00012, 0x026a21f5,
0x02a5f001, 0x07f124bd,
0xf000b7f0, 0x03f047fc,
0x0c9850b3, 0x0002d002,
0x0fc4b604, 0x2cf004bd,
0x9800bcbb, 0x0320b601,
0x0d98000c, 0x4afc07f1,
0x00e7f001, 0xd00203f0,
0x016621f5, 0x04bd0002,
0xf001acf0, 0xf001acf0,
0xb7f104a5, 0xb7f102a5,
0xb3f04000, 0xb3f00000,
0x040c9850, 0x040c9850,
0xbb0fc4b6, 0xbb0fc4b6,
0x0c9800bc, 0x0c9800bc,
0x020d9801, 0x010d9800,
0xf1060f98, 0xf500e7f0,
0xf50800e7, 0xf0016f21,
0xf5016621, 0xa5f001ac,
0xf4021521, 0x00b7f104,
0x12f40601, 0x50b3f040,
/* 0x0535: ctx_xfer_post */ 0xb6040c98,
0xfc17f114, 0xbcbb0fc4,
0x0213f04a, 0x010c9800,
0xd00d27f0, 0x98020d98,
0x21f50012, 0xe7f1060f,
/* 0x0546: ctx_xfer_done */ 0x21f50800,
0x21f50215, 0x21f5016f,
0x00f80479, 0x01f4025e,
0x0712f406,
/* 0x0618: ctx_xfer_post */
0x027f21f5,
/* 0x061c: ctx_xfer_done */
0x054721f5,
0x000000f8,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000, 0x00000000,
0x00000000, 0x00000000,
0x00000000, 0x00000000,

770
drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvd7.fuc.h
View File

@@ -41,14 +41,14 @@ uint32_t nvd7_grgpc_data[] = {
}; };
uint32_t nvd7_grgpc_code[] = { uint32_t nvd7_grgpc_code[] = {
0x03180ef5, 0x03a10ef5,
/* 0x0004: queue_put */ /* 0x0004: queue_put */
0x9800d898, 0x9800d898,
0x86f001d9, 0x86f001d9,
0x0489b808, 0x0489b808,
0xf00c1bf4, 0xf00c1bf4,
0x21f502f7, 0x21f502f7,
0x00f802fe, 0x00f8037e,
/* 0x001c: queue_put_next */ /* 0x001c: queue_put_next */
0xb60798c4, 0xb60798c4,
0x8dbb0384, 0x8dbb0384,
@@ -72,184 +72,214 @@ uint32_t nvd7_grgpc_code[] = {
/* 0x0066: queue_get_done */ /* 0x0066: queue_get_done */
0x00f80132, 0x00f80132,
/* 0x0068: nv_rd32 */ /* 0x0068: nv_rd32 */
0x0728b7f1, 0xf002ecb9,
0xb906b4b6, 0x07f11fc9,
0xc9f002ec, 0x03f0ca00,
0x00bcd01f, 0x000cd001,
/* 0x0078: nv_rd32_wait */ /* 0x007a: nv_rd32_wait */
0xc800bccf, 0xc7f104bd,
0x1bf41fcc, 0xc3f0ca00,
0x06a7f0fa, 0x00cccf01,
0x010921f5, 0xf41fccc8,
0xf840bfcf, 0xa7f0f31b,
/* 0x008d: nv_wr32 */ 0x1021f506,
0x28b7f100, 0x00f7f101,
0x06b4b607, 0x01f3f0cb,
0xb980bfd0, 0xf800ffcf,
0xc9f002ec, /* 0x009d: nv_wr32 */
0x1ec9f01f, 0x0007f100,
/* 0x00a3: nv_wr32_wait */ 0x0103f0cc,
0xcf00bcd0, 0xbd000fd0,
0xccc800bc, 0x02ecb904,
0xfa1bf41f, 0xf01fc9f0,
/* 0x00ae: watchdog_reset */ 0x07f11ec9,
0x87f100f8, 0x03f0ca00,
0x84b60430, 0x000cd001,
0x1ff9f006, /* 0x00be: nv_wr32_wait */
0xf8008fd0, 0xc7f104bd,
/* 0x00bd: watchdog_clear */ 0xc3f0ca00,
0x3087f100, 0x00cccf01,
0x0684b604, 0xf41fccc8,
0xf80080d0, 0x00f8f31b,
/* 0x00c9: wait_donez */ /* 0x00d0: wait_donez */
0xf094bd00,
0x07f10099,
0x03f00f00,
0x0009d002,
0x07f104bd,
0x03f00600,
0x000ad002,
/* 0x00e6: wait_donez_ne */
0x87f104bd,
0x83f00000,
0x0088cf01,
0xf4888aff,
0x94bdf31b,
0xf10099f0,
0xf0170007,
0x09d00203,
0xf804bd00,
/* 0x0109: wait_doneo */
0xf094bd00,
0x07f10099,
0x03f00f00,
0x0009d002,
0x87f104bd,
0x84b60818,
0x008ad006,
/* 0x0124: wait_doneo_e */
0x040087f1,
0xcf0684b6,
0x8aff0088,
0xf30bf488,
0x99f094bd, 0x99f094bd,
0x0007f100, 0x0007f100,
0x0203f017, 0x0203f00f,
0xbd0009d0, 0xbd0009d0,
/* 0x0147: mmctx_size */ 0x0007f104,
0xbd00f804, 0x0203f006,
/* 0x0149: nv_mmctx_size_loop */ 0xbd000ad0,
0x00e89894, /* 0x00ed: wait_donez_ne */
0xb61a85b6, 0x0087f104,
0x84b60180, 0x0183f000,
0x0098bb02, 0xff0088cf,
0xb804e0b6, 0x1bf4888a,
0x1bf404ef, 0xf094bdf3,
0x029fb9eb, 0x07f10099,
/* 0x0166: mmctx_xfer */ 0x03f01700,
0x94bd00f8, 0x0009d002,
0xf10199f0, 0x00f804bd,
0xf00f0007, /* 0x0110: wait_doneo */
0x09d00203, 0x99f094bd,
0xf104bd00, 0x0007f100,
0xb6071087, 0x0203f00f,
0x94bd0684, 0xbd0009d0,
0xf405bbfd, 0x0007f104,
0x8bd0090b, 0x0203f006,
0x0099f000, 0xbd000ad0,
/* 0x018c: mmctx_base_disabled */ /* 0x012d: wait_doneo_e */
0xf405eefd, 0x0087f104,
0x8ed00c0b, 0x0183f000,
0xc08fd080, 0xff0088cf,
/* 0x019b: mmctx_multi_disabled */ 0x0bf4888a,
0xb70199f0, 0xf094bdf3,
0xc8010080, 0x07f10099,
0x03f01700,
0x0009d002,
0x00f804bd,
/* 0x0150: mmctx_size */
/* 0x0152: nv_mmctx_size_loop */
0xe89894bd,
0x1a85b600,
0xb60180b6,
0x98bb0284,
0x04e0b600,
0xf404efb8,
0x9fb9eb1b,
/* 0x016f: mmctx_xfer */
0xbd00f802,
0x0199f094,
0x0f0007f1,
0xd00203f0,
0x04bd0009,
0xbbfd94bd,
0x120bf405,
0xc40007f1,
0xd00103f0,
0x04bd000b,
/* 0x0197: mmctx_base_disabled */
0xfd0099f0,
0x0bf405ee,
0x0007f11e,
0x0103f0c6,
0xbd000ed0,
0x0007f104,
0x0103f0c7,
0xbd000fd0,
0x0199f004,
/* 0x01b8: mmctx_multi_disabled */
0xb600abc8,
0xb9f010b4,
0x01aec80c,
0xfd11e4b6,
0x07f105be,
0x03f0c500,
0x000bd001,
/* 0x01d6: mmctx_exec_loop */
/* 0x01d6: mmctx_wait_free */
0xe7f104bd,
0xe3f0c500,
0x00eecf01,
0xf41fe4f0,
0xce98f30b,
0x05e9fd00,
0xc80007f1,
0xd00103f0,
0x04bd000e,
0xb804c0b6,
0x1bf404cd,
0x02abc8d8,
/* 0x0207: mmctx_fini_wait */
0xf11f1bf4,
0xf0c500b7,
0xbbcf01b3,
0x1fb4f000,
0xf410b4b0,
0xa7f0f01b,
0xd021f402,
/* 0x0223: mmctx_stop */
0xc82b0ef4,
0xb4b600ab, 0xb4b600ab,
0x0cb9f010, 0x0cb9f010,
0xb601aec8, 0xf112b9f0,
0xbefd11e4, 0xf0c50007,
0x008bd005, 0x0bd00103,
/* 0x01b4: mmctx_exec_loop */ /* 0x023b: mmctx_stop_wait */
/* 0x01b4: mmctx_wait_free */ 0xf104bd00,
0xf0008ecf, 0xf0c500b7,
0x0bf41fe4, 0xbbcf01b3,
0x00ce98fa, 0x12bbc800,
0xd005e9fd, /* 0x024b: mmctx_done */
0xc0b6c08e, 0xbdf31bf4,
0x04cdb804, 0x0199f094,
0xc8e81bf4, 0x170007f1,
0x1bf402ab, 0xd00203f0,
/* 0x01d5: mmctx_fini_wait */ 0x04bd0009,
0x008bcf18, /* 0x025e: strand_wait */
0xb01fb4f0, 0xa0f900f8,
0x1bf410b4, 0xf402a7f0,
0x02a7f0f7, 0xa0fcd021,
0xf4c921f4, /* 0x026a: strand_pre */
/* 0x01ea: mmctx_stop */ 0x97f000f8,
0xabc81b0e, 0xfc07f10c,
0x10b4b600, 0x0203f04a,
0xf00cb9f0, 0xbd0009d0,
0x8bd012b9, 0x5e21f504,
/* 0x01f9: mmctx_stop_wait */ /* 0x027f: strand_post */
0x008bcf00, 0xf000f802,
0xf412bbc8, 0x07f10d97,
/* 0x0202: mmctx_done */ 0x03f04afc,
0x94bdfa1b,
0xf10199f0,
0xf0170007,
0x09d00203,
0xf804bd00,
/* 0x0215: strand_wait */
0xf0a0f900,
0x21f402a7,
0xf8a0fcc9,
/* 0x0221: strand_pre */
0xfc87f100,
0x0283f04a,
0xd00c97f0,
0x21f50089,
0x00f80215,
/* 0x0234: strand_post */
0x4afc87f1,
0xf00283f0,
0x89d00d97,
0x1521f500,
/* 0x0247: strand_set */
0xf100f802,
0xf04ffca7,
0xaba202a3,
0xc7f00500,
0x00acd00f,
0xd00bc7f0,
0x21f500bc,
0xaed00215,
0x0ac7f000,
0xf500bcd0,
0xf8021521,
/* 0x0271: strand_ctx_init */
0xf094bd00,
0x07f10399,
0x03f00f00,
0x0009d002, 0x0009d002,
0x21f504bd, 0x21f504bd,
0xe7f00221, 0x00f8025e,
0x4721f503, /* 0x0294: strand_set */
0xfca7f102, 0xf10fc7f0,
0x02a3f046, 0xf04ffc07,
0x0400aba0, 0x0cd00203,
0xf040a0d0, 0xf004bd00,
0xbcd001c7, 0x07f10bc7,
0x1521f500, 0x03f04afc,
0x010c9202, 0x000cd002,
0xf000acd0, 0x07f104bd,
0xbcd002c7, 0x03f04ffc,
0x1521f500, 0x000ed002,
0x3421f502, 0xc7f004bd,
0x8087f102, 0xfc07f10a,
0x0684b608, 0x0203f04a,
0xb70089cf, 0xbd000cd0,
0x95220080, 0x5e21f504,
/* 0x02ca: ctx_init_strand_loop */ /* 0x02d3: strand_ctx_init */
0xbd00f802,
0x0399f094,
0x0f0007f1,
0xd00203f0,
0x04bd0009,
0x026a21f5,
0xf503e7f0,
0xbd029421,
0xfc07f1c4,
0x0203f047,
0xbd000cd0,
0x01c7f004,
0x4afc07f1,
0xd00203f0,
0x04bd000c,
0x025e21f5,
0xf1010c92,
0xf046fc07,
0x0cd00203,
0xf004bd00,
0x07f102c7,
0x03f04afc,
0x000cd002,
0x21f504bd,
0x21f5025e,
0x87f1027f,
0x83f04200,
0x0097f102,
0x0293f020,
0x950099cf,
/* 0x034a: ctx_init_strand_loop */
0x8ed008fe, 0x8ed008fe,
0x408ed000, 0x408ed000,
0xb6808acf, 0xb6808acf,
@@ -263,198 +293,230 @@ uint32_t nvd7_grgpc_code[] = {
0x170007f1, 0x170007f1,
0xd00203f0, 0xd00203f0,
0x04bd0009, 0x04bd0009,
/* 0x02fe: error */ /* 0x037e: error */
0xe0f900f8, 0xe0f900f8,
0x9814e7f1, 0xf102ffb9,
0xf440e3f0, 0xf09814e7,
0xe0b78d21, 0x21f440e3,
0xf7f0041c, 0x01f7f09d,
0x8d21f401, 0xf102ffb9,
0x00f8e0fc, 0xf09c1ce7,
/* 0x0318: init */ 0x21f440e3,
0x04fe04bd, 0xf8e0fc9d,
0x0017f100, /* 0x03a1: init */
0x0227f012, 0xfe04bd00,
0xf10012d0, 0x27f00004,
0xfe047017, 0x0007f102,
0x17f10010, 0x0003f012,
0x10d00400, 0xbd0002d0,
0x0427f0c0, 0x1f17f104,
0xf40012d0, 0x0010fe05,
0x17f11031, 0x070007f1,
0x14b60608, 0xd00003f0,
0x0012cf06, 0x04bd0000,
0xf10427f0,
0xf0040007,
0x02d00003,
0xf404bd00,
0x27f11031,
0x23f08200,
0x0022cf01,
0xf00137f0, 0xf00137f0,
0x32bb1f24, 0x32bb1f24,
0x0132b604, 0x0132b604,
0x80050280, 0x80050280,
0x10b70603, 0x27f10603,
0x12cf0400, 0x23f08600,
0x04028000, 0x0022cf01,
0x0c30e7f1, 0xf1040280,
0xbd50e3f0, 0xf00c30e7,
0xbd34bd24, 0x24bd50e3,
/* 0x0371: init_unk_loop */ 0x44bd34bd,
0x6821f444, /* 0x0410: init_unk_loop */
0xf400f6b0, 0xb06821f4,
0xf7f00f0b, 0x0bf400f6,
0x04f2bb01, 0x01f7f00f,
0xb6054ffd, 0xfd04f2bb,
/* 0x0386: init_unk_next */ 0x30b6054f,
0x20b60130, /* 0x0425: init_unk_next */
0x04e0b601, 0x0120b601,
0xf40126b0, 0xb004e0b6,
/* 0x0392: init_unk_done */ 0x1bf40126,
0x0380e21b, /* 0x0431: init_unk_done */
0x08048007, 0x070380e2,
0x010027f1, 0xf1080480,
0xcf0223f0, 0xf0010027,
0x34bd0022, 0x22cf0223,
0x070047f1, 0x9534bd00,
0x950644b6, 0x07f10825,
0x45d00825, 0x03f0c000,
0x4045d000, 0x0005d001,
0x98000e98, 0x07f104bd,
0x21f5010f, 0x03f0c100,
0x2fbb0147, 0x0005d001,
0x003fbb00, 0x0e9804bd,
0x98010e98, 0x010f9800,
0x21f5020f, 0x015021f5,
0x0e980147, 0xbb002fbb,
0x00effd05, 0x0e98003f,
0xbb002ebb, 0x020f9801,
0x0e98003e, 0x015021f5,
0x030f9802, 0xfd050e98,
0x014721f5,
0xfd070e98,
0x2ebb00ef, 0x2ebb00ef,
0x003ebb00, 0x003ebb00,
0x130040b7, 0x98020e98,
0xd00235b6, 0x21f5030f,
0x25b60043, 0x0e980150,
0x0635b608, 0x00effd07,
0xb60120b6, 0xbb002ebb,
0x24b60130, 0x35b6003e,
0x0834b608, 0x0007f102,
0xf5022fb9, 0x0103f0d3,
0xbb027121, 0xbd0003d0,
0x07f1003f, 0x0825b604,
0x03f00100, 0xb60635b6,
0x0003d002, 0x30b60120,
0x24bd04bd, 0x0824b601,
0xf11f29f0, 0xb90834b6,
0xf0080007, 0x21f5022f,
0x02d00203, 0x3fbb02d3,
/* 0x0433: main */ 0x0007f100,
0x0203f001,
0xbd0003d0,
0xf024bd04,
0x07f11f29,
0x03f00800,
0x0002d002,
/* 0x04e2: main */
0x31f404bd,
0x0028f400,
0xf424d7f0,
0x01f43921,
0x04e4b0f4,
0xfe1e18f4,
0x27f00181,
0xfd20bd06,
0xe4b60412,
0x051efd01,
0xf50018fe,
0xf405d721,
/* 0x0512: main_not_ctx_xfer */
0xef94d30e,
0x01f5f010,
0x037e21f5,
/* 0x051f: ih */
0xf9c60ef4,
0x0188fe80,
0x90f980f9,
0xb0f9a0f9,
0xe0f9d0f9,
0x04bdf0f9,
0x0200a7f1,
0xcf00a3f0,
0xabc400aa,
0x2c0bf404,
0xf124d7f0,
0xf01a00e7,
0xeecf00e3,
0x00f7f100,
0x00f3f019,
0xf400ffcf,
0xe7f00421,
0x0007f101,
0x0003f01d,
0xbd000ed0,
/* 0x056d: ih_no_fifo */
0x0007f104,
0x0003f001,
0xbd000ad0,
0xfcf0fc04,
0xfcd0fce0,
0xfca0fcb0,
0xfe80fc90,
0x80fc0088,
0xf80032f4,
/* 0x0591: hub_barrier_done */
0x01f7f001,
0xbb040e98,
0xffb904fe,
0x18e7f102,
0x40e3f094,
0xf89d21f4,
/* 0x05a9: ctx_redswitch */
0x20f7f000,
0x850007f1,
0xd00103f0,
0x04bd000f,
/* 0x05bb: ctx_redswitch_delay */
0xb608e7f0,
0x1bf401e2,
0x00f5f1fd,
0x00f5f108,
0x0007f102,
0x0103f085,
0xbd000fd0,
/* 0x05d7: ctx_xfer */
0xf100f804,
0xf0810007,
0x0fd00203,
0xf404bd00, 0xf404bd00,
0x28f40031, 0x21f50711,
0x24d7f000, /* 0x05ea: ctx_xfer_not_load */
0xf43921f4, 0x21f505a9,
0xe4b0f401, 0x24bd026a,
0x1e18f404, 0x47fc07f1,
0xf00181fe, 0xd00203f0,
0x20bd0627, 0x04bd0002,
0xb60412fd, 0xb6012cf0,
0x1efd01e4, 0x07f10320,
0x0018fe05, 0x03f04afc,
0x04f721f5, 0x0002d002,
/* 0x0463: main_not_ctx_xfer */ 0xacf004bd,
0x94d30ef4, 0x02a5f001,
0xf5f010ef, 0x0000b7f1,
0xfe21f501,
0xc60ef402,
/* 0x0470: ih */
0x88fe80f9,
0xf980f901,
0xf9a0f990,
0xf9d0f9b0,
0xbdf0f9e0,
0x800acf04,
0xf404abc4,
0xb7f11d0b,
0xd7f01900,
0x40becf24,
0xf400bfcf,
0xb0b70421,
0xe7f00400,
0x00bed001,
/* 0x04a8: ih_no_fifo */
0xfc400ad0,
0xfce0fcf0,
0xfcb0fcd0,
0xfc90fca0,
0x0088fe80,
0x32f480fc,
/* 0x04c3: hub_barrier_done */
0xf001f800,
0x0e9801f7,
0x04febb04,
0x9418e7f1,
0xf440e3f0,
0x00f88d21,
/* 0x04d8: ctx_redswitch */
0x0614e7f1,
0xf006e4b6,
0xefd020f7,
0x08f7f000,
/* 0x04e8: ctx_redswitch_delay */
0xf401f2b6,
0xf7f1fd1b,
0xefd00a20,
/* 0x04f7: ctx_xfer */
0xf100f800,
0xb60a0417,
0x1fd00614,
0x0711f400,
0x04d821f5,
/* 0x0508: ctx_xfer_not_load */
0x4afc17f1,
0xf00213f0,
0x12d00c27,
0x1521f500,
0xfc27f102,
0x0223f047,
0xf00020d0,
0x20b6012c,
0x0012d003,
0xf001acf0,
0xb7f002a5,
0x50b3f000,
0xb6040c98,
0xbcbb0fc4,
0x000c9800,
0xf0010d98,
0x21f500e7,
0xacf00166,
0x00b7f101,
0x50b3f040,
0xb6040c98,
0xbcbb0fc4,
0x010c9800,
0x98020d98,
0xe7f1060f,
0x21f50800,
0xacf00166,
0x04a5f001,
0x3000b7f1,
0x9850b3f0, 0x9850b3f0,
0xc4b6040c, 0xc4b6040c,
0x00bcbb0f, 0x00bcbb0f,
0x98020c98, 0x98000c98,
0x0f98030d, 0xe7f0010d,
0x00e7f108, 0x6f21f500,
0x6621f502, 0x01acf001,
0x1521f501, 0x4000b7f1,
0x0601f402, 0x9850b3f0,
/* 0x05a3: ctx_xfer_post */ 0xc4b6040c,
0xf11412f4, 0x00bcbb0f,
0xf04afc17, 0x98010c98,
0x27f00213, 0x0f98020d,
0x0012d00d, 0x00e7f106,
0x021521f5, 0x6f21f508,
/* 0x05b4: ctx_xfer_done */ 0x01acf001,
0x04c321f5, 0xf104a5f0,
0x000000f8, 0xf03000b7,
0x0c9850b3,
0x0fc4b604,
0x9800bcbb,
0x0d98020c,
0x080f9803,
0x0200e7f1,
0x016f21f5,
0x025e21f5,
0xf40601f4,
/* 0x0686: ctx_xfer_post */
0x21f50712,
/* 0x068a: ctx_xfer_done */
0x21f5027f,
0x00f80591,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000, 0x00000000,
0x00000000, 0x00000000,
0x00000000, 0x00000000,

770
drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc.h
View File

@@ -41,14 +41,14 @@ uint32_t nve0_grgpc_data[] = {
}; };
uint32_t nve0_grgpc_code[] = { uint32_t nve0_grgpc_code[] = {
0x03180ef5, 0x03a10ef5,
/* 0x0004: queue_put */ /* 0x0004: queue_put */
0x9800d898, 0x9800d898,
0x86f001d9, 0x86f001d9,
0x0489b808, 0x0489b808,
0xf00c1bf4, 0xf00c1bf4,
0x21f502f7, 0x21f502f7,
0x00f802fe, 0x00f8037e,
/* 0x001c: queue_put_next */ /* 0x001c: queue_put_next */
0xb60798c4, 0xb60798c4,
0x8dbb0384, 0x8dbb0384,
@@ -72,184 +72,214 @@ uint32_t nve0_grgpc_code[] = {
/* 0x0066: queue_get_done */ /* 0x0066: queue_get_done */
0x00f80132, 0x00f80132,
/* 0x0068: nv_rd32 */ /* 0x0068: nv_rd32 */
0x0728b7f1, 0xf002ecb9,
0xb906b4b6, 0x07f11fc9,
0xc9f002ec, 0x03f0ca00,
0x00bcd01f, 0x000cd001,
/* 0x0078: nv_rd32_wait */ /* 0x007a: nv_rd32_wait */
0xc800bccf, 0xc7f104bd,
0x1bf41fcc, 0xc3f0ca00,
0x06a7f0fa, 0x00cccf01,
0x010921f5, 0xf41fccc8,
0xf840bfcf, 0xa7f0f31b,
/* 0x008d: nv_wr32 */ 0x1021f506,
0x28b7f100, 0x00f7f101,
0x06b4b607, 0x01f3f0cb,
0xb980bfd0, 0xf800ffcf,
0xc9f002ec, /* 0x009d: nv_wr32 */
0x1ec9f01f, 0x0007f100,
/* 0x00a3: nv_wr32_wait */ 0x0103f0cc,
0xcf00bcd0, 0xbd000fd0,
0xccc800bc, 0x02ecb904,
0xfa1bf41f, 0xf01fc9f0,
/* 0x00ae: watchdog_reset */ 0x07f11ec9,
0x87f100f8, 0x03f0ca00,
0x84b60430, 0x000cd001,
0x1ff9f006, /* 0x00be: nv_wr32_wait */
0xf8008fd0, 0xc7f104bd,
/* 0x00bd: watchdog_clear */ 0xc3f0ca00,
0x3087f100, 0x00cccf01,
0x0684b604, 0xf41fccc8,
0xf80080d0, 0x00f8f31b,
/* 0x00c9: wait_donez */ /* 0x00d0: wait_donez */
0xf094bd00,
0x07f10099,
0x03f00f00,
0x0009d002,
0x07f104bd,
0x03f00600,
0x000ad002,
/* 0x00e6: wait_donez_ne */
0x87f104bd,
0x83f00000,
0x0088cf01,
0xf4888aff,
0x94bdf31b,
0xf10099f0,
0xf0170007,
0x09d00203,
0xf804bd00,
/* 0x0109: wait_doneo */
0xf094bd00,
0x07f10099,
0x03f00f00,
0x0009d002,
0x87f104bd,
0x84b60818,
0x008ad006,
/* 0x0124: wait_doneo_e */
0x040087f1,
0xcf0684b6,
0x8aff0088,
0xf30bf488,
0x99f094bd, 0x99f094bd,
0x0007f100, 0x0007f100,
0x0203f017, 0x0203f00f,
0xbd0009d0, 0xbd0009d0,
/* 0x0147: mmctx_size */ 0x0007f104,
0xbd00f804, 0x0203f006,
/* 0x0149: nv_mmctx_size_loop */ 0xbd000ad0,
0x00e89894, /* 0x00ed: wait_donez_ne */
0xb61a85b6, 0x0087f104,
0x84b60180, 0x0183f000,
0x0098bb02, 0xff0088cf,
0xb804e0b6, 0x1bf4888a,
0x1bf404ef, 0xf094bdf3,
0x029fb9eb, 0x07f10099,
/* 0x0166: mmctx_xfer */ 0x03f01700,
0x94bd00f8, 0x0009d002,
0xf10199f0, 0x00f804bd,
0xf00f0007, /* 0x0110: wait_doneo */
0x09d00203, 0x99f094bd,
0xf104bd00, 0x0007f100,
0xb6071087, 0x0203f00f,
0x94bd0684, 0xbd0009d0,
0xf405bbfd, 0x0007f104,
0x8bd0090b, 0x0203f006,
0x0099f000, 0xbd000ad0,
/* 0x018c: mmctx_base_disabled */ /* 0x012d: wait_doneo_e */
0xf405eefd, 0x0087f104,
0x8ed00c0b, 0x0183f000,
0xc08fd080, 0xff0088cf,
/* 0x019b: mmctx_multi_disabled */ 0x0bf4888a,
0xb70199f0, 0xf094bdf3,
0xc8010080, 0x07f10099,
0x03f01700,
0x0009d002,
0x00f804bd,
/* 0x0150: mmctx_size */
/* 0x0152: nv_mmctx_size_loop */
0xe89894bd,
0x1a85b600,
0xb60180b6,
0x98bb0284,
0x04e0b600,
0xf404efb8,
0x9fb9eb1b,
/* 0x016f: mmctx_xfer */
0xbd00f802,
0x0199f094,
0x0f0007f1,
0xd00203f0,
0x04bd0009,
0xbbfd94bd,
0x120bf405,
0xc40007f1,
0xd00103f0,
0x04bd000b,
/* 0x0197: mmctx_base_disabled */
0xfd0099f0,
0x0bf405ee,
0x0007f11e,
0x0103f0c6,
0xbd000ed0,
0x0007f104,
0x0103f0c7,
0xbd000fd0,
0x0199f004,
/* 0x01b8: mmctx_multi_disabled */
0xb600abc8,
0xb9f010b4,
0x01aec80c,
0xfd11e4b6,
0x07f105be,
0x03f0c500,
0x000bd001,
/* 0x01d6: mmctx_exec_loop */
/* 0x01d6: mmctx_wait_free */
0xe7f104bd,
0xe3f0c500,
0x00eecf01,
0xf41fe4f0,
0xce98f30b,
0x05e9fd00,
0xc80007f1,
0xd00103f0,
0x04bd000e,
0xb804c0b6,
0x1bf404cd,
0x02abc8d8,
/* 0x0207: mmctx_fini_wait */
0xf11f1bf4,
0xf0c500b7,
0xbbcf01b3,
0x1fb4f000,
0xf410b4b0,
0xa7f0f01b,
0xd021f402,
/* 0x0223: mmctx_stop */
0xc82b0ef4,
0xb4b600ab, 0xb4b600ab,
0x0cb9f010, 0x0cb9f010,
0xb601aec8, 0xf112b9f0,
0xbefd11e4, 0xf0c50007,
0x008bd005, 0x0bd00103,
/* 0x01b4: mmctx_exec_loop */ /* 0x023b: mmctx_stop_wait */
/* 0x01b4: mmctx_wait_free */ 0xf104bd00,
0xf0008ecf, 0xf0c500b7,
0x0bf41fe4, 0xbbcf01b3,
0x00ce98fa, 0x12bbc800,
0xd005e9fd, /* 0x024b: mmctx_done */
0xc0b6c08e, 0xbdf31bf4,
0x04cdb804, 0x0199f094,
0xc8e81bf4, 0x170007f1,
0x1bf402ab, 0xd00203f0,
/* 0x01d5: mmctx_fini_wait */ 0x04bd0009,
0x008bcf18, /* 0x025e: strand_wait */
0xb01fb4f0, 0xa0f900f8,
0x1bf410b4, 0xf402a7f0,
0x02a7f0f7, 0xa0fcd021,
0xf4c921f4, /* 0x026a: strand_pre */
/* 0x01ea: mmctx_stop */ 0x97f000f8,
0xabc81b0e, 0xfc07f10c,
0x10b4b600, 0x0203f04a,
0xf00cb9f0, 0xbd0009d0,
0x8bd012b9, 0x5e21f504,
/* 0x01f9: mmctx_stop_wait */ /* 0x027f: strand_post */
0x008bcf00, 0xf000f802,
0xf412bbc8, 0x07f10d97,
/* 0x0202: mmctx_done */ 0x03f04afc,
0x94bdfa1b,
0xf10199f0,
0xf0170007,
0x09d00203,
0xf804bd00,
/* 0x0215: strand_wait */
0xf0a0f900,
0x21f402a7,
0xf8a0fcc9,
/* 0x0221: strand_pre */
0xfc87f100,
0x0283f04a,
0xd00c97f0,
0x21f50089,
0x00f80215,
/* 0x0234: strand_post */
0x4afc87f1,
0xf00283f0,
0x89d00d97,
0x1521f500,
/* 0x0247: strand_set */
0xf100f802,
0xf04ffca7,
0xaba202a3,
0xc7f00500,
0x00acd00f,
0xd00bc7f0,
0x21f500bc,
0xaed00215,
0x0ac7f000,
0xf500bcd0,
0xf8021521,
/* 0x0271: strand_ctx_init */
0xf094bd00,
0x07f10399,
0x03f00f00,
0x0009d002, 0x0009d002,
0x21f504bd, 0x21f504bd,
0xe7f00221, 0x00f8025e,
0x4721f503, /* 0x0294: strand_set */
0xfca7f102, 0xf10fc7f0,
0x02a3f046, 0xf04ffc07,
0x0400aba0, 0x0cd00203,
0xf040a0d0, 0xf004bd00,
0xbcd001c7, 0x07f10bc7,
0x1521f500, 0x03f04afc,
0x010c9202, 0x000cd002,
0xf000acd0, 0x07f104bd,
0xbcd002c7, 0x03f04ffc,
0x1521f500, 0x000ed002,
0x3421f502, 0xc7f004bd,
0x8087f102, 0xfc07f10a,
0x0684b608, 0x0203f04a,
0xb70089cf, 0xbd000cd0,
0x95220080, 0x5e21f504,
/* 0x02ca: ctx_init_strand_loop */ /* 0x02d3: strand_ctx_init */
0xbd00f802,
0x0399f094,
0x0f0007f1,
0xd00203f0,
0x04bd0009,
0x026a21f5,
0xf503e7f0,
0xbd029421,
0xfc07f1c4,
0x0203f047,
0xbd000cd0,
0x01c7f004,
0x4afc07f1,
0xd00203f0,
0x04bd000c,
0x025e21f5,
0xf1010c92,
0xf046fc07,
0x0cd00203,
0xf004bd00,
0x07f102c7,
0x03f04afc,
0x000cd002,
0x21f504bd,
0x21f5025e,
0x87f1027f,
0x83f04200,
0x0097f102,
0x0293f020,
0x950099cf,
/* 0x034a: ctx_init_strand_loop */
0x8ed008fe, 0x8ed008fe,
0x408ed000, 0x408ed000,
0xb6808acf, 0xb6808acf,
@@ -263,198 +293,230 @@ uint32_t nve0_grgpc_code[] = {
0x170007f1, 0x170007f1,
0xd00203f0, 0xd00203f0,
0x04bd0009, 0x04bd0009,
/* 0x02fe: error */ /* 0x037e: error */
0xe0f900f8, 0xe0f900f8,
0x9814e7f1, 0xf102ffb9,
0xf440e3f0, 0xf09814e7,
0xe0b78d21, 0x21f440e3,
0xf7f0041c, 0x01f7f09d,
0x8d21f401, 0xf102ffb9,
0x00f8e0fc, 0xf09c1ce7,
/* 0x0318: init */ 0x21f440e3,
0x04fe04bd, 0xf8e0fc9d,
0x0017f100, /* 0x03a1: init */
0x0227f012, 0xfe04bd00,
0xf10012d0, 0x27f00004,
0xfe047017, 0x0007f102,
0x17f10010, 0x0003f012,
0x10d00400, 0xbd0002d0,
0x0427f0c0, 0x1f17f104,
0xf40012d0, 0x0010fe05,
0x17f11031, 0x070007f1,
0x14b60608, 0xd00003f0,
0x0012cf06, 0x04bd0000,
0xf10427f0,
0xf0040007,
0x02d00003,
0xf404bd00,
0x27f11031,
0x23f08200,
0x0022cf01,
0xf00137f0, 0xf00137f0,
0x32bb1f24, 0x32bb1f24,
0x0132b604, 0x0132b604,
0x80050280, 0x80050280,
0x10b70603, 0x27f10603,
0x12cf0400, 0x23f08600,
0x04028000, 0x0022cf01,
0x0c30e7f1, 0xf1040280,
0xbd50e3f0, 0xf00c30e7,
0xbd34bd24, 0x24bd50e3,
/* 0x0371: init_unk_loop */ 0x44bd34bd,
0x6821f444, /* 0x0410: init_unk_loop */
0xf400f6b0, 0xb06821f4,
0xf7f00f0b, 0x0bf400f6,
0x04f2bb01, 0x01f7f00f,
0xb6054ffd, 0xfd04f2bb,
/* 0x0386: init_unk_next */ 0x30b6054f,
0x20b60130, /* 0x0425: init_unk_next */
0x04e0b601, 0x0120b601,
0xf40126b0, 0xb004e0b6,
/* 0x0392: init_unk_done */ 0x1bf40126,
0x0380e21b, /* 0x0431: init_unk_done */
0x08048007, 0x070380e2,
0x010027f1, 0xf1080480,
0xcf0223f0, 0xf0010027,
0x34bd0022, 0x22cf0223,
0x070047f1, 0x9534bd00,
0x950644b6, 0x07f10825,
0x45d00825, 0x03f0c000,
0x4045d000, 0x0005d001,
0x98000e98, 0x07f104bd,
0x21f5010f, 0x03f0c100,
0x2fbb0147, 0x0005d001,
0x003fbb00, 0x0e9804bd,
0x98010e98, 0x010f9800,
0x21f5020f, 0x015021f5,
0x0e980147, 0xbb002fbb,
0x00effd05, 0x0e98003f,
0xbb002ebb, 0x020f9801,
0x0e98003e, 0x015021f5,
0x030f9802, 0xfd050e98,
0x014721f5,
0xfd070e98,
0x2ebb00ef, 0x2ebb00ef,
0x003ebb00, 0x003ebb00,
0x130040b7, 0x98020e98,
0xd00235b6, 0x21f5030f,
0x25b60043, 0x0e980150,
0x0635b608, 0x00effd07,
0xb60120b6, 0xbb002ebb,
0x24b60130, 0x35b6003e,
0x0834b608, 0x0007f102,
0xf5022fb9, 0x0103f0d3,
0xbb027121, 0xbd0003d0,
0x07f1003f, 0x0825b604,
0x03f00100, 0xb60635b6,
0x0003d002, 0x30b60120,
0x24bd04bd, 0x0824b601,
0xf11f29f0, 0xb90834b6,
0xf0080007, 0x21f5022f,
0x02d00203, 0x3fbb02d3,
/* 0x0433: main */ 0x0007f100,
0x0203f001,
0xbd0003d0,
0xf024bd04,
0x07f11f29,
0x03f00800,
0x0002d002,
/* 0x04e2: main */
0x31f404bd,
0x0028f400,
0xf424d7f0,
0x01f43921,
0x04e4b0f4,
0xfe1e18f4,
0x27f00181,
0xfd20bd06,
0xe4b60412,
0x051efd01,
0xf50018fe,
0xf405d721,
/* 0x0512: main_not_ctx_xfer */
0xef94d30e,
0x01f5f010,
0x037e21f5,
/* 0x051f: ih */
0xf9c60ef4,
0x0188fe80,
0x90f980f9,
0xb0f9a0f9,
0xe0f9d0f9,
0x04bdf0f9,
0x0200a7f1,
0xcf00a3f0,
0xabc400aa,
0x2c0bf404,
0xf124d7f0,
0xf01a00e7,
0xeecf00e3,
0x00f7f100,
0x00f3f019,
0xf400ffcf,
0xe7f00421,
0x0007f101,
0x0003f01d,
0xbd000ed0,
/* 0x056d: ih_no_fifo */
0x0007f104,
0x0003f001,
0xbd000ad0,
0xfcf0fc04,
0xfcd0fce0,
0xfca0fcb0,
0xfe80fc90,
0x80fc0088,
0xf80032f4,
/* 0x0591: hub_barrier_done */
0x01f7f001,
0xbb040e98,
0xffb904fe,
0x18e7f102,
0x40e3f094,
0xf89d21f4,
/* 0x05a9: ctx_redswitch */
0x20f7f000,
0x850007f1,
0xd00103f0,
0x04bd000f,
/* 0x05bb: ctx_redswitch_delay */
0xb608e7f0,
0x1bf401e2,
0x00f5f1fd,
0x00f5f108,
0x0007f102,
0x0103f085,
0xbd000fd0,
/* 0x05d7: ctx_xfer */
0xf100f804,
0xf0810007,
0x0fd00203,
0xf404bd00, 0xf404bd00,
0x28f40031, 0x21f50711,
0x24d7f000, /* 0x05ea: ctx_xfer_not_load */
0xf43921f4, 0x21f505a9,
0xe4b0f401, 0x24bd026a,
0x1e18f404, 0x47fc07f1,
0xf00181fe, 0xd00203f0,
0x20bd0627, 0x04bd0002,
0xb60412fd, 0xb6012cf0,
0x1efd01e4, 0x07f10320,
0x0018fe05, 0x03f04afc,
0x04f721f5, 0x0002d002,
/* 0x0463: main_not_ctx_xfer */ 0xacf004bd,
0x94d30ef4, 0x02a5f001,
0xf5f010ef, 0x0000b7f1,
0xfe21f501,
0xc60ef402,
/* 0x0470: ih */
0x88fe80f9,
0xf980f901,
0xf9a0f990,
0xf9d0f9b0,
0xbdf0f9e0,
0x800acf04,
0xf404abc4,
0xb7f11d0b,
0xd7f01900,
0x40becf24,
0xf400bfcf,
0xb0b70421,
0xe7f00400,
0x00bed001,
/* 0x04a8: ih_no_fifo */
0xfc400ad0,
0xfce0fcf0,
0xfcb0fcd0,
0xfc90fca0,
0x0088fe80,
0x32f480fc,
/* 0x04c3: hub_barrier_done */
0xf001f800,
0x0e9801f7,
0x04febb04,
0x9418e7f1,
0xf440e3f0,
0x00f88d21,
/* 0x04d8: ctx_redswitch */
0x0614e7f1,
0xf006e4b6,
0xefd020f7,
0x08f7f000,
/* 0x04e8: ctx_redswitch_delay */
0xf401f2b6,
0xf7f1fd1b,
0xefd00a20,
/* 0x04f7: ctx_xfer */
0xf100f800,
0xb60a0417,
0x1fd00614,
0x0711f400,
0x04d821f5,
/* 0x0508: ctx_xfer_not_load */
0x4afc17f1,
0xf00213f0,
0x12d00c27,
0x1521f500,
0xfc27f102,
0x0223f047,
0xf00020d0,
0x20b6012c,
0x0012d003,
0xf001acf0,
0xb7f002a5,
0x50b3f000,
0xb6040c98,
0xbcbb0fc4,
0x000c9800,
0xf0010d98,
0x21f500e7,
0xacf00166,
0x00b7f101,
0x50b3f040,
0xb6040c98,
0xbcbb0fc4,
0x010c9800,
0x98020d98,
0xe7f1060f,
0x21f50800,
0xacf00166,
0x04a5f001,
0x3000b7f1,
0x9850b3f0, 0x9850b3f0,
0xc4b6040c, 0xc4b6040c,
0x00bcbb0f, 0x00bcbb0f,
0x98020c98, 0x98000c98,
0x0f98030d, 0xe7f0010d,
0x00e7f108, 0x6f21f500,
0x6621f502, 0x01acf001,
0x1521f501, 0x4000b7f1,
0x0601f402, 0x9850b3f0,
/* 0x05a3: ctx_xfer_post */ 0xc4b6040c,
0xf11412f4, 0x00bcbb0f,
0xf04afc17, 0x98010c98,
0x27f00213, 0x0f98020d,
0x0012d00d, 0x00e7f106,
0x021521f5, 0x6f21f508,
/* 0x05b4: ctx_xfer_done */ 0x01acf001,
0x04c321f5, 0xf104a5f0,
0x000000f8, 0xf03000b7,
0x0c9850b3,
0x0fc4b604,
0x9800bcbb,
0x0d98020c,
0x080f9803,
0x0200e7f1,
0x016f21f5,
0x025e21f5,
0xf40601f4,
/* 0x0686: ctx_xfer_post */
0x21f50712,
/* 0x068a: ctx_xfer_done */
0x21f5027f,
0x00f80591,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000, 0x00000000,
0x00000000, 0x00000000,
0x00000000, 0x00000000,

770
drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvf0.fuc.h
View File

@@ -41,14 +41,14 @@ uint32_t nvf0_grgpc_data[] = {
}; };
uint32_t nvf0_grgpc_code[] = { uint32_t nvf0_grgpc_code[] = {
0x03180ef5, 0x03a10ef5,
/* 0x0004: queue_put */ /* 0x0004: queue_put */
0x9800d898, 0x9800d898,
0x86f001d9, 0x86f001d9,
0x0489b808, 0x0489b808,
0xf00c1bf4, 0xf00c1bf4,
0x21f502f7, 0x21f502f7,
0x00f802fe, 0x00f8037e,
/* 0x001c: queue_put_next */ /* 0x001c: queue_put_next */
0xb60798c4, 0xb60798c4,
0x8dbb0384, 0x8dbb0384,
@@ -72,184 +72,214 @@ uint32_t nvf0_grgpc_code[] = {
/* 0x0066: queue_get_done */ /* 0x0066: queue_get_done */
0x00f80132, 0x00f80132,
/* 0x0068: nv_rd32 */ /* 0x0068: nv_rd32 */
0x0728b7f1, 0xf002ecb9,
0xb906b4b6, 0x07f11fc9,
0xc9f002ec, 0x03f0ca00,
0x00bcd01f, 0x000cd001,
/* 0x0078: nv_rd32_wait */ /* 0x007a: nv_rd32_wait */
0xc800bccf, 0xc7f104bd,
0x1bf41fcc, 0xc3f0ca00,
0x06a7f0fa, 0x00cccf01,
0x010921f5, 0xf41fccc8,
0xf840bfcf, 0xa7f0f31b,
/* 0x008d: nv_wr32 */ 0x1021f506,
0x28b7f100, 0x00f7f101,
0x06b4b607, 0x01f3f0cb,
0xb980bfd0, 0xf800ffcf,
0xc9f002ec, /* 0x009d: nv_wr32 */
0x1ec9f01f, 0x0007f100,
/* 0x00a3: nv_wr32_wait */ 0x0103f0cc,
0xcf00bcd0, 0xbd000fd0,
0xccc800bc, 0x02ecb904,
0xfa1bf41f, 0xf01fc9f0,
/* 0x00ae: watchdog_reset */ 0x07f11ec9,
0x87f100f8, 0x03f0ca00,
0x84b60430, 0x000cd001,
0x1ff9f006, /* 0x00be: nv_wr32_wait */
0xf8008fd0, 0xc7f104bd,
/* 0x00bd: watchdog_clear */ 0xc3f0ca00,
0x3087f100, 0x00cccf01,
0x0684b604, 0xf41fccc8,
0xf80080d0, 0x00f8f31b,
/* 0x00c9: wait_donez */ /* 0x00d0: wait_donez */
0xf094bd00,
0x07f10099,
0x03f03700,
0x0009d002,
0x07f104bd,
0x03f00600,
0x000ad002,
/* 0x00e6: wait_donez_ne */
0x87f104bd,
0x83f00000,
0x0088cf01,
0xf4888aff,
0x94bdf31b,
0xf10099f0,
0xf0170007,
0x09d00203,
0xf804bd00,
/* 0x0109: wait_doneo */
0xf094bd00,
0x07f10099,
0x03f03700,
0x0009d002,
0x87f104bd,
0x84b60818,
0x008ad006,
/* 0x0124: wait_doneo_e */
0x040087f1,
0xcf0684b6,
0x8aff0088,
0xf30bf488,
0x99f094bd, 0x99f094bd,
0x0007f100, 0x0007f100,
0x0203f017, 0x0203f037,
0xbd0009d0, 0xbd0009d0,
/* 0x0147: mmctx_size */ 0x0007f104,
0xbd00f804, 0x0203f006,
/* 0x0149: nv_mmctx_size_loop */ 0xbd000ad0,
0x00e89894, /* 0x00ed: wait_donez_ne */
0xb61a85b6, 0x0087f104,
0x84b60180, 0x0183f000,
0x0098bb02, 0xff0088cf,
0xb804e0b6, 0x1bf4888a,
0x1bf404ef, 0xf094bdf3,
0x029fb9eb, 0x07f10099,
/* 0x0166: mmctx_xfer */ 0x03f01700,
0x94bd00f8, 0x0009d002,
0xf10199f0, 0x00f804bd,
0xf0370007, /* 0x0110: wait_doneo */
0x09d00203, 0x99f094bd,
0xf104bd00, 0x0007f100,
0xb6071087, 0x0203f037,
0x94bd0684, 0xbd0009d0,
0xf405bbfd, 0x0007f104,
0x8bd0090b, 0x0203f006,
0x0099f000, 0xbd000ad0,
/* 0x018c: mmctx_base_disabled */ /* 0x012d: wait_doneo_e */
0xf405eefd, 0x0087f104,
0x8ed00c0b, 0x0183f000,
0xc08fd080, 0xff0088cf,
/* 0x019b: mmctx_multi_disabled */ 0x0bf4888a,
0xb70199f0, 0xf094bdf3,
0xc8010080, 0x07f10099,
0x03f01700,
0x0009d002,
0x00f804bd,
/* 0x0150: mmctx_size */
/* 0x0152: nv_mmctx_size_loop */
0xe89894bd,
0x1a85b600,
0xb60180b6,
0x98bb0284,
0x04e0b600,
0xf404efb8,
0x9fb9eb1b,
/* 0x016f: mmctx_xfer */
0xbd00f802,
0x0199f094,
0x370007f1,
0xd00203f0,
0x04bd0009,
0xbbfd94bd,
0x120bf405,
0xc40007f1,
0xd00103f0,
0x04bd000b,
/* 0x0197: mmctx_base_disabled */
0xfd0099f0,
0x0bf405ee,
0x0007f11e,
0x0103f0c6,
0xbd000ed0,
0x0007f104,
0x0103f0c7,
0xbd000fd0,
0x0199f004,
/* 0x01b8: mmctx_multi_disabled */
0xb600abc8,
0xb9f010b4,
0x01aec80c,
0xfd11e4b6,
0x07f105be,
0x03f0c500,
0x000bd001,
/* 0x01d6: mmctx_exec_loop */
/* 0x01d6: mmctx_wait_free */
0xe7f104bd,
0xe3f0c500,
0x00eecf01,
0xf41fe4f0,
0xce98f30b,
0x05e9fd00,
0xc80007f1,
0xd00103f0,
0x04bd000e,
0xb804c0b6,
0x1bf404cd,
0x02abc8d8,
/* 0x0207: mmctx_fini_wait */
0xf11f1bf4,
0xf0c500b7,
0xbbcf01b3,
0x1fb4f000,
0xf410b4b0,
0xa7f0f01b,
0xd021f402,
/* 0x0223: mmctx_stop */
0xc82b0ef4,
0xb4b600ab, 0xb4b600ab,
0x0cb9f010, 0x0cb9f010,
0xb601aec8, 0xf112b9f0,
0xbefd11e4, 0xf0c50007,
0x008bd005, 0x0bd00103,
/* 0x01b4: mmctx_exec_loop */ /* 0x023b: mmctx_stop_wait */
/* 0x01b4: mmctx_wait_free */ 0xf104bd00,
0xf0008ecf, 0xf0c500b7,
0x0bf41fe4, 0xbbcf01b3,
0x00ce98fa, 0x12bbc800,
0xd005e9fd, /* 0x024b: mmctx_done */
0xc0b6c08e, 0xbdf31bf4,
0x04cdb804, 0x0199f094,
0xc8e81bf4, 0x170007f1,
0x1bf402ab, 0xd00203f0,
/* 0x01d5: mmctx_fini_wait */ 0x04bd0009,
0x008bcf18, /* 0x025e: strand_wait */
0xb01fb4f0, 0xa0f900f8,
0x1bf410b4, 0xf402a7f0,
0x02a7f0f7, 0xa0fcd021,
0xf4c921f4, /* 0x026a: strand_pre */
/* 0x01ea: mmctx_stop */ 0x97f000f8,
0xabc81b0e, 0xfc07f10c,
0x10b4b600, 0x0203f04a,
0xf00cb9f0, 0xbd0009d0,
0x8bd012b9, 0x5e21f504,
/* 0x01f9: mmctx_stop_wait */ /* 0x027f: strand_post */
0x008bcf00, 0xf000f802,
0xf412bbc8, 0x07f10d97,
/* 0x0202: mmctx_done */ 0x03f04afc,
0x94bdfa1b,
0xf10199f0,
0xf0170007,
0x09d00203,
0xf804bd00,
/* 0x0215: strand_wait */
0xf0a0f900,
0x21f402a7,
0xf8a0fcc9,
/* 0x0221: strand_pre */
0xfc87f100,
0x0283f04a,
0xd00c97f0,
0x21f50089,
0x00f80215,
/* 0x0234: strand_post */
0x4afc87f1,
0xf00283f0,
0x89d00d97,
0x1521f500,
/* 0x0247: strand_set */
0xf100f802,
0xf04ffca7,
0xaba202a3,
0xc7f00500,
0x00acd00f,
0xd00bc7f0,
0x21f500bc,
0xaed00215,
0x0ac7f000,
0xf500bcd0,
0xf8021521,
/* 0x0271: strand_ctx_init */
0xf094bd00,
0x07f10399,
0x03f03700,
0x0009d002, 0x0009d002,
0x21f504bd, 0x21f504bd,
0xe7f00221, 0x00f8025e,
0x4721f503, /* 0x0294: strand_set */
0xfca7f102, 0xf10fc7f0,
0x02a3f046, 0xf04ffc07,
0x0400aba0, 0x0cd00203,
0xf040a0d0, 0xf004bd00,
0xbcd001c7, 0x07f10bc7,
0x1521f500, 0x03f04afc,
0x010c9202, 0x000cd002,
0xf000acd0, 0x07f104bd,
0xbcd002c7, 0x03f04ffc,
0x1521f500, 0x000ed002,
0x3421f502, 0xc7f004bd,
0x8087f102, 0xfc07f10a,
0x0684b608, 0x0203f04a,
0xb70089cf, 0xbd000cd0,
0x95220080, 0x5e21f504,
/* 0x02ca: ctx_init_strand_loop */ /* 0x02d3: strand_ctx_init */
0xbd00f802,
0x0399f094,
0x370007f1,
0xd00203f0,
0x04bd0009,
0x026a21f5,
0xf503e7f0,
0xbd029421,
0xfc07f1c4,
0x0203f047,
0xbd000cd0,
0x01c7f004,
0x4afc07f1,
0xd00203f0,
0x04bd000c,
0x025e21f5,
0xf1010c92,
0xf046fc07,
0x0cd00203,
0xf004bd00,
0x07f102c7,
0x03f04afc,
0x000cd002,
0x21f504bd,
0x21f5025e,
0x87f1027f,
0x83f04200,
0x0097f102,
0x0293f020,
0x950099cf,
/* 0x034a: ctx_init_strand_loop */
0x8ed008fe, 0x8ed008fe,
0x408ed000, 0x408ed000,
0xb6808acf, 0xb6808acf,
@@ -263,198 +293,230 @@ uint32_t nvf0_grgpc_code[] = {
0x170007f1, 0x170007f1,
0xd00203f0, 0xd00203f0,
0x04bd0009, 0x04bd0009,
/* 0x02fe: error */ /* 0x037e: error */
0xe0f900f8, 0xe0f900f8,
0x9814e7f1, 0xf102ffb9,
0xf440e3f0, 0xf09814e7,
0xe0b78d21, 0x21f440e3,
0xf7f0041c, 0x01f7f09d,
0x8d21f401, 0xf102ffb9,
0x00f8e0fc, 0xf09c1ce7,
/* 0x0318: init */ 0x21f440e3,
0x04fe04bd, 0xf8e0fc9d,
0x0017f100, /* 0x03a1: init */
0x0227f012, 0xfe04bd00,
0xf10012d0, 0x27f00004,
0xfe047017, 0x0007f102,
0x17f10010, 0x0003f012,
0x10d00400, 0xbd0002d0,
0x0427f0c0, 0x1f17f104,
0xf40012d0, 0x0010fe05,
0x17f11031, 0x070007f1,
0x14b60608, 0xd00003f0,
0x0012cf06, 0x04bd0000,
0xf10427f0,
0xf0040007,
0x02d00003,
0xf404bd00,
0x27f11031,
0x23f08200,
0x0022cf01,
0xf00137f0, 0xf00137f0,
0x32bb1f24, 0x32bb1f24,
0x0132b604, 0x0132b604,
0x80050280, 0x80050280,
0x10b70603, 0x27f10603,
0x12cf0400, 0x23f08600,
0x04028000, 0x0022cf01,
0x0c30e7f1, 0xf1040280,
0xbd50e3f0, 0xf00c30e7,
0xbd34bd24, 0x24bd50e3,
/* 0x0371: init_unk_loop */ 0x44bd34bd,
0x6821f444, /* 0x0410: init_unk_loop */
0xf400f6b0, 0xb06821f4,
0xf7f00f0b, 0x0bf400f6,
0x04f2bb01, 0x01f7f00f,
0xb6054ffd, 0xfd04f2bb,
/* 0x0386: init_unk_next */ 0x30b6054f,
0x20b60130, /* 0x0425: init_unk_next */
0x04e0b601, 0x0120b601,
0xf40226b0, 0xb004e0b6,
/* 0x0392: init_unk_done */ 0x1bf40226,
0x0380e21b, /* 0x0431: init_unk_done */
0x08048007, 0x070380e2,
0x010027f1, 0xf1080480,
0xcf0223f0, 0xf0010027,
0x34bd0022, 0x22cf0223,
0x070047f1, 0x9534bd00,
0x950644b6, 0x07f10825,
0x45d00825, 0x03f0c000,
0x4045d000, 0x0005d001,
0x98000e98, 0x07f104bd,
0x21f5010f, 0x03f0c100,
0x2fbb0147, 0x0005d001,
0x003fbb00, 0x0e9804bd,
0x98010e98, 0x010f9800,
0x21f5020f, 0x015021f5,
0x0e980147, 0xbb002fbb,
0x00effd05, 0x0e98003f,
0xbb002ebb, 0x020f9801,
0x0e98003e, 0x015021f5,
0x030f9802, 0xfd050e98,
0x014721f5,
0xfd070e98,
0x2ebb00ef, 0x2ebb00ef,
0x003ebb00, 0x003ebb00,
0x130040b7, 0x98020e98,
0xd00235b6, 0x21f5030f,
0x25b60043, 0x0e980150,
0x0635b608, 0x00effd07,
0xb60120b6, 0xbb002ebb,
0x24b60130, 0x35b6003e,
0x0834b608, 0x0007f102,
0xf5022fb9, 0x0103f0d3,
0xbb027121, 0xbd0003d0,
0x07f1003f, 0x0825b604,
0x03f00100, 0xb60635b6,
0x0003d002, 0x30b60120,
0x24bd04bd, 0x0824b601,
0xf11f29f0, 0xb90834b6,
0xf0300007, 0x21f5022f,
0x02d00203, 0x3fbb02d3,
/* 0x0433: main */ 0x0007f100,
0x0203f001,
0xbd0003d0,
0xf024bd04,
0x07f11f29,
0x03f03000,
0x0002d002,
/* 0x04e2: main */
0x31f404bd,
0x0028f400,
0xf424d7f0,
0x01f43921,
0x04e4b0f4,
0xfe1e18f4,
0x27f00181,
0xfd20bd06,
0xe4b60412,
0x051efd01,
0xf50018fe,
0xf405d721,
/* 0x0512: main_not_ctx_xfer */
0xef94d30e,
0x01f5f010,
0x037e21f5,
/* 0x051f: ih */
0xf9c60ef4,
0x0188fe80,
0x90f980f9,
0xb0f9a0f9,
0xe0f9d0f9,
0x04bdf0f9,
0x0200a7f1,
0xcf00a3f0,
0xabc400aa,
0x2c0bf404,
0xf124d7f0,
0xf01a00e7,
0xeecf00e3,
0x00f7f100,
0x00f3f019,
0xf400ffcf,
0xe7f00421,
0x0007f101,
0x0003f01d,
0xbd000ed0,
/* 0x056d: ih_no_fifo */
0x0007f104,
0x0003f001,
0xbd000ad0,
0xfcf0fc04,
0xfcd0fce0,
0xfca0fcb0,
0xfe80fc90,
0x80fc0088,
0xf80032f4,
/* 0x0591: hub_barrier_done */
0x01f7f001,
0xbb040e98,
0xffb904fe,
0x18e7f102,
0x40e3f094,
0xf89d21f4,
/* 0x05a9: ctx_redswitch */
0x20f7f000,
0x850007f1,
0xd00103f0,
0x04bd000f,
/* 0x05bb: ctx_redswitch_delay */
0xb608e7f0,
0x1bf401e2,
0x00f5f1fd,
0x00f5f108,
0x0007f102,
0x0103f085,
0xbd000fd0,
/* 0x05d7: ctx_xfer */
0xf100f804,
0xf0810007,
0x0fd00203,
0xf404bd00, 0xf404bd00,
0x28f40031, 0x21f50711,
0x24d7f000, /* 0x05ea: ctx_xfer_not_load */
0xf43921f4, 0x21f505a9,
0xe4b0f401, 0x24bd026a,
0x1e18f404, 0x47fc07f1,
0xf00181fe, 0xd00203f0,
0x20bd0627, 0x04bd0002,
0xb60412fd, 0xb6012cf0,
0x1efd01e4, 0x07f10320,
0x0018fe05, 0x03f04afc,
0x04f721f5, 0x0002d002,
/* 0x0463: main_not_ctx_xfer */ 0xacf004bd,
0x94d30ef4, 0x02a5f001,
0xf5f010ef, 0x0000b7f1,
0xfe21f501,
0xc60ef402,
/* 0x0470: ih */
0x88fe80f9,
0xf980f901,
0xf9a0f990,
0xf9d0f9b0,
0xbdf0f9e0,
0x800acf04,
0xf404abc4,
0xb7f11d0b,
0xd7f01900,
0x40becf24,
0xf400bfcf,
0xb0b70421,
0xe7f00400,
0x00bed001,
/* 0x04a8: ih_no_fifo */
0xfc400ad0,
0xfce0fcf0,
0xfcb0fcd0,
0xfc90fca0,
0x0088fe80,
0x32f480fc,
/* 0x04c3: hub_barrier_done */
0xf001f800,
0x0e9801f7,
0x04febb04,
0x9418e7f1,
0xf440e3f0,
0x00f88d21,
/* 0x04d8: ctx_redswitch */
0x0614e7f1,
0xf006e4b6,
0xefd020f7,
0x08f7f000,
/* 0x04e8: ctx_redswitch_delay */
0xf401f2b6,
0xf7f1fd1b,
0xefd00a20,
/* 0x04f7: ctx_xfer */
0xf100f800,
0xb60a0417,
0x1fd00614,
0x0711f400,
0x04d821f5,
/* 0x0508: ctx_xfer_not_load */
0x4afc17f1,
0xf00213f0,
0x12d00c27,
0x1521f500,
0xfc27f102,
0x0223f047,
0xf00020d0,
0x20b6012c,
0x0012d003,
0xf001acf0,
0xb7f002a5,
0x50b3f000,
0xb6040c98,
0xbcbb0fc4,
0x000c9800,
0xf0010d98,
0x21f500e7,
0xacf00166,
0x00b7f101,
0x50b3f040,
0xb6040c98,
0xbcbb0fc4,
0x010c9800,
0x98020d98,
0xe7f1060f,
0x21f50800,
0xacf00166,
0x04a5f001,
0x3000b7f1,
0x9850b3f0, 0x9850b3f0,
0xc4b6040c, 0xc4b6040c,
0x00bcbb0f, 0x00bcbb0f,
0x98020c98, 0x98000c98,
0x0f98030d, 0xe7f0010d,
0x00e7f108, 0x6f21f500,
0x6621f502, 0x01acf001,
0x1521f501, 0x4000b7f1,
0x0601f402, 0x9850b3f0,
/* 0x05a3: ctx_xfer_post */ 0xc4b6040c,
0xf11412f4, 0x00bcbb0f,
0xf04afc17, 0x98010c98,
0x27f00213, 0x0f98020d,
0x0012d00d, 0x00e7f106,
0x021521f5, 0x6f21f508,
/* 0x05b4: ctx_xfer_done */ 0x01acf001,
0x04c321f5, 0xf104a5f0,
0x000000f8, 0xf03000b7,
0x0c9850b3,
0x0fc4b604,
0x9800bcbb,
0x0d98020c,
0x080f9803,
0x0200e7f1,
0x016f21f5,
0x025e21f5,
0xf40601f4,
/* 0x0686: ctx_xfer_post */
0x21f50712,
/* 0x068a: ctx_xfer_done */
0x21f5027f,
0x00f80591,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000, 0x00000000,
0x00000000, 0x00000000,
0x00000000, 0x00000000,

382
drivers/gpu/drm/nouveau/core/engine/graph/fuc/hub.fuc
View File

@@ -68,60 +68,57 @@ error:
// //
init: init:
clear b32 $r0 clear b32 $r0
mov $sp $r0
mov $xdbase $r0 mov $xdbase $r0
// setup stack
nv_iord($r1, NV_PGRAPH_FECS_CAPS, 0)
extr $r1 $r1 9:17
shl b32 $r1 8
mov $sp $r1
// enable fifo access // enable fifo access
mov $r1 0x1200 mov $r2 NV_PGRAPH_FECS_ACCESS_FIFO
mov $r2 2 nv_iowr(NV_PGRAPH_FECS_ACCESS, 0, $r2)
iowr I[$r1 + 0x000] $r2 // FIFO_ENABLE
// setup i0 handler, and route all interrupts to it // setup i0 handler, and route all interrupts to it
mov $r1 #ih mov $r1 #ih
mov $iv0 $r1 mov $iv0 $r1
mov $r1 0x400
iowr I[$r1 + 0x300] $r0 // INTR_DISPATCH
// route HUB_CHANNEL_SWITCH to fuc interrupt 8 clear b32 $r2
mov $r3 0x404 nv_iowr(NV_PGRAPH_FECS_INTR_ROUTE, 0, $r2)
shl b32 $r3 6
mov $r2 0x2003 // { HUB_CHANNEL_SWITCH, ZERO } -> intr 8 // route HUB_CHSW_PULSE to fuc interrupt 8
iowr I[$r3 + 0x000] $r2 mov $r2 0x2003 // { HUB_CHSW_PULSE, ZERO } -> intr 8
nv_iowr(NV_PGRAPH_FECS_IROUTE, 0, $r2)
// not sure what these are, route them because NVIDIA does, and // not sure what these are, route them because NVIDIA does, and
// the IRQ handler will signal the host if we ever get one.. we // the IRQ handler will signal the host if we ever get one.. we
// may find out if/why we need to handle these if so.. // may find out if/why we need to handle these if so..
// //
mov $r2 0x2004 mov $r2 0x2004 // { 0x04, ZERO } -> intr 9
iowr I[$r3 + 0x004] $r2 // { 0x04, ZERO } -> intr 9 nv_iowr(NV_PGRAPH_FECS_IROUTE, 1, $r2)
mov $r2 0x200b mov $r2 0x200b // { HUB_FIRMWARE_MTHD, ZERO } -> intr 10
iowr I[$r3 + 0x008] $r2 // { 0x0b, ZERO } -> intr 10 nv_iowr(NV_PGRAPH_FECS_IROUTE, 2, $r2)
mov $r2 0x200c mov $r2 0x200c // { 0x0c, ZERO } -> intr 15
iowr I[$r3 + 0x01c] $r2 // { 0x0c, ZERO } -> intr 15 nv_iowr(NV_PGRAPH_FECS_IROUTE, 7, $r2)
// enable all INTR_UP interrupts // enable all INTR_UP interrupts
mov $r2 0xc24 sub b32 $r3 $r0 1
shl b32 $r2 6 nv_iowr(NV_PGRAPH_FECS_INTR_UP_EN, 0, $r3)
not b32 $r3 $r0
iowr I[$r2] $r3
// enable fifo, ctxsw, 9, 10, 15 interrupts // enable fifo, ctxsw, 9, fwmthd, 15 interrupts
mov $r2 -0x78fc // 0x8704 imm32($r2, 0x8704)
sethi $r2 0 nv_iowr(NV_PGRAPH_FECS_INTR_EN_SET, 0, $r2)
iowr I[$r1 + 0x000] $r2 // INTR_EN_SET
// fifo level triggered, rest edge // fifo level triggered, rest edge
sub b32 $r1 0x100 mov $r2 NV_PGRAPH_FECS_INTR_MODE_FIFO_LEVEL
mov $r2 4 nv_iowr(NV_PGRAPH_FECS_INTR_MODE, 0, $r2)
iowr I[$r1] $r2
// enable interrupts // enable interrupts
bset $flags ie0 bset $flags ie0
// fetch enabled GPC/ROP counts // fetch enabled GPC/ROP counts
mov $r14 -0x69fc // 0x409604 nv_rd32($r14, 0x409604)
sethi $r14 0x400000
call #nv_rd32
extr $r1 $r15 16:20 extr $r1 $r15 16:20
st b32 D[$r0 + #rop_count] $r1 st b32 D[$r0 + #rop_count] $r1
and $r15 0x1f and $r15 0x1f
@@ -131,37 +128,40 @@ init:
mov $r1 1 mov $r1 1
shl b32 $r1 $r15 shl b32 $r1 $r15
sub b32 $r1 1 sub b32 $r1 1
mov $r2 0x40c nv_iowr(NV_PGRAPH_FECS_BAR_MASK0, 0, $r1)
shl b32 $r2 6 nv_iowr(NV_PGRAPH_FECS_BAR_MASK1, 0, $r1)
iowr I[$r2 + 0x000] $r1
iowr I[$r2 + 0x100] $r1
// context size calculation, reserve first 256 bytes for use by fuc // context size calculation, reserve first 256 bytes for use by fuc
mov $r1 256 mov $r1 256
//
mov $r15 2
call(ctx_4170s)
call(ctx_4170w)
mov $r15 0x10
call(ctx_86c)
// calculate size of mmio context data // calculate size of mmio context data
ld b32 $r14 D[$r0 + #hub_mmio_list_head] ld b32 $r14 D[$r0 + #hub_mmio_list_head]
ld b32 $r15 D[$r0 + #hub_mmio_list_tail] ld b32 $r15 D[$r0 + #hub_mmio_list_tail]
call #mmctx_size call(mmctx_size)
// set mmctx base addresses now so we don't have to do it later, // set mmctx base addresses now so we don't have to do it later,
// they don't (currently) ever change // they don't (currently) ever change
mov $r3 0x700
shl b32 $r3 6
shr b32 $r4 $r1 8 shr b32 $r4 $r1 8
iowr I[$r3 + 0x000] $r4 // MMCTX_SAVE_SWBASE nv_iowr(NV_PGRAPH_FECS_MMCTX_SAVE_SWBASE, 0, $r4)
iowr I[$r3 + 0x100] $r4 // MMCTX_LOAD_SWBASE nv_iowr(NV_PGRAPH_FECS_MMCTX_LOAD_SWBASE, 0, $r4)
add b32 $r3 0x1300 add b32 $r3 0x1300
add b32 $r1 $r15 add b32 $r1 $r15
shr b32 $r15 2 shr b32 $r15 2
iowr I[$r3 + 0x000] $r15 // MMCTX_LOAD_COUNT, wtf for?!? nv_iowr(NV_PGRAPH_FECS_MMCTX_LOAD_COUNT, 0, $r15) // wtf??
// strands, base offset needs to be aligned to 256 bytes // strands, base offset needs to be aligned to 256 bytes
shr b32 $r1 8 shr b32 $r1 8
add b32 $r1 1 add b32 $r1 1
shl b32 $r1 8 shl b32 $r1 8
mov b32 $r15 $r1 mov b32 $r15 $r1
call #strand_ctx_init call(strand_ctx_init)
add b32 $r1 $r15 add b32 $r1 $r15
// initialise each GPC in sequence by passing in the offset of its // initialise each GPC in sequence by passing in the offset of its
@@ -173,30 +173,29 @@ init:
// in GPCn_CC_SCRATCH[1] // in GPCn_CC_SCRATCH[1]
// //
ld b32 $r3 D[$r0 + #gpc_count] ld b32 $r3 D[$r0 + #gpc_count]
mov $r4 0x2000 imm32($r4, 0x502000)
sethi $r4 0x500000
init_gpc: init_gpc:
// setup, and start GPC ucode running // setup, and start GPC ucode running
add b32 $r14 $r4 0x804 add b32 $r14 $r4 0x804
mov b32 $r15 $r1 mov b32 $r15 $r1
call #nv_wr32 // CC_SCRATCH[1] = ctx offset call(nv_wr32) // CC_SCRATCH[1] = ctx offset
add b32 $r14 $r4 0x10c add b32 $r14 $r4 0x10c
clear b32 $r15 clear b32 $r15
call #nv_wr32 call(nv_wr32)
add b32 $r14 $r4 0x104 add b32 $r14 $r4 0x104
call #nv_wr32 // ENTRY call(nv_wr32) // ENTRY
add b32 $r14 $r4 0x100 add b32 $r14 $r4 0x100
mov $r15 2 // CTRL_START_TRIGGER mov $r15 2 // CTRL_START_TRIGGER
call #nv_wr32 // CTRL call(nv_wr32) // CTRL
// wait for it to complete, and adjust context size // wait for it to complete, and adjust context size
add b32 $r14 $r4 0x800 add b32 $r14 $r4 0x800
init_gpc_wait: init_gpc_wait:
call #nv_rd32 call(nv_rd32)
xbit $r15 $r15 31 xbit $r15 $r15 31
bra e #init_gpc_wait bra e #init_gpc_wait
add b32 $r14 $r4 0x804 add b32 $r14 $r4 0x804
call #nv_rd32 call(nv_rd32)
add b32 $r1 $r15 add b32 $r1 $r15
// next! // next!
@@ -204,6 +203,12 @@ init:
sub b32 $r3 1 sub b32 $r3 1
bra ne #init_gpc bra ne #init_gpc
//
mov $r15 0
call(ctx_86c)
mov $r15 0
call(ctx_4170s)
// save context size, and tell host we're ready // save context size, and tell host we're ready
nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_VAL(1), 0, $r1) nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_VAL(1), 0, $r1)
clear b32 $r1 clear b32 $r1
@@ -218,17 +223,15 @@ main:
bset $flags $p0 bset $flags $p0
sleep $p0 sleep $p0
mov $r13 #cmd_queue mov $r13 #cmd_queue
call #queue_get call(queue_get)
bra $p1 #main bra $p1 #main
// context switch, requested by GPU? // context switch, requested by GPU?
cmpu b32 $r14 0x4001 cmpu b32 $r14 0x4001
bra ne #main_not_ctx_switch bra ne #main_not_ctx_switch
trace_set(T_AUTO) trace_set(T_AUTO)
mov $r1 0xb00 nv_iord($r1, NV_PGRAPH_FECS_CHAN_ADDR, 0)
shl b32 $r1 6 nv_iord($r2, NV_PGRAPH_FECS_CHAN_NEXT, 0)
iord $r2 I[$r1 + 0x100] // CHAN_NEXT
iord $r1 I[$r1 + 0x000] // CHAN_CUR
xbit $r3 $r1 31 xbit $r3 $r1 31
bra e #chsw_no_prev bra e #chsw_no_prev
@@ -239,12 +242,12 @@ main:
trace_set(T_SAVE) trace_set(T_SAVE)
bclr $flags $p1 bclr $flags $p1
bset $flags $p2 bset $flags $p2
call #ctx_xfer call(ctx_xfer)
trace_clr(T_SAVE); trace_clr(T_SAVE);
pop $r2 pop $r2
trace_set(T_LOAD); trace_set(T_LOAD);
bset $flags $p1 bset $flags $p1
call #ctx_xfer call(ctx_xfer)
trace_clr(T_LOAD); trace_clr(T_LOAD);
bra #chsw_done bra #chsw_done
chsw_prev_no_next: chsw_prev_no_next:
@@ -252,25 +255,21 @@ main:
mov b32 $r2 $r1 mov b32 $r2 $r1
bclr $flags $p1 bclr $flags $p1
bclr $flags $p2 bclr $flags $p2
call #ctx_xfer call(ctx_xfer)
pop $r2 pop $r2
mov $r1 0xb00 nv_iowr(NV_PGRAPH_FECS_CHAN_ADDR, 0, $r2)
shl b32 $r1 6
iowr I[$r1] $r2
bra #chsw_done bra #chsw_done
chsw_no_prev: chsw_no_prev:
xbit $r3 $r2 31 xbit $r3 $r2 31
bra e #chsw_done bra e #chsw_done
bset $flags $p1 bset $flags $p1
bclr $flags $p2 bclr $flags $p2
call #ctx_xfer call(ctx_xfer)
// ack the context switch request // ack the context switch request
chsw_done: chsw_done:
mov $r1 0xb0c mov $r2 NV_PGRAPH_FECS_CHSW_ACK
shl b32 $r1 6 nv_iowr(NV_PGRAPH_FECS_CHSW, 0, $r2)
mov $r2 1
iowr I[$r1 + 0x000] $r2 // 0x409b0c
trace_clr(T_AUTO) trace_clr(T_AUTO)
bra #main bra #main
@@ -279,7 +278,7 @@ main:
cmpu b32 $r14 0x0001 cmpu b32 $r14 0x0001
bra ne #main_not_ctx_chan bra ne #main_not_ctx_chan
mov b32 $r2 $r15 mov b32 $r2 $r15
call #ctx_chan call(ctx_chan)
bra #main_done bra #main_done
// request to store current channel context? // request to store current channel context?
@@ -289,14 +288,14 @@ main:
trace_set(T_SAVE) trace_set(T_SAVE)
bclr $flags $p1 bclr $flags $p1
bclr $flags $p2 bclr $flags $p2
call #ctx_xfer call(ctx_xfer)
trace_clr(T_SAVE) trace_clr(T_SAVE)
bra #main_done bra #main_done
main_not_ctx_save: main_not_ctx_save:
shl b32 $r15 $r14 16 shl b32 $r15 $r14 16
or $r15 E_BAD_COMMAND or $r15 E_BAD_COMMAND
call #error call(error)
bra #main bra #main
main_done: main_done:
@@ -319,41 +318,46 @@ ih:
clear b32 $r0 clear b32 $r0
// incoming fifo command? // incoming fifo command?
iord $r10 I[$r0 + 0x200] // INTR nv_iord($r10, NV_PGRAPH_FECS_INTR, 0)
and $r11 $r10 0x00000004 and $r11 $r10 NV_PGRAPH_FECS_INTR_FIFO
bra e #ih_no_fifo bra e #ih_no_fifo
// queue incoming fifo command for later processing // queue incoming fifo command for later processing
mov $r11 0x1900
mov $r13 #cmd_queue mov $r13 #cmd_queue
iord $r14 I[$r11 + 0x100] // FIFO_CMD nv_iord($r14, NV_PGRAPH_FECS_FIFO_CMD, 0)
iord $r15 I[$r11 + 0x000] // FIFO_DATA nv_iord($r15, NV_PGRAPH_FECS_FIFO_DATA, 0)
call #queue_put call(queue_put)
add b32 $r11 0x400 add b32 $r11 0x400
mov $r14 1 mov $r14 1
iowr I[$r11 + 0x000] $r14 // FIFO_ACK nv_iowr(NV_PGRAPH_FECS_FIFO_ACK, 0, $r14)
// context switch request? // context switch request?
ih_no_fifo: ih_no_fifo:
and $r11 $r10 0x00000100 and $r11 $r10 NV_PGRAPH_FECS_INTR_CHSW
bra e #ih_no_ctxsw bra e #ih_no_ctxsw
// enqueue a context switch for later processing // enqueue a context switch for later processing
mov $r13 #cmd_queue mov $r13 #cmd_queue
mov $r14 0x4001 mov $r14 0x4001
call #queue_put call(queue_put)
// firmware method?
ih_no_ctxsw:
and $r11 $r10 NV_PGRAPH_FECS_INTR_FWMTHD
bra e #ih_no_fwmthd
// none we handle, ack, and fall-through to unhandled
mov $r11 0x100
nv_wr32(0x400144, $r11)
// anything we didn't handle, bring it to the host's attention // anything we didn't handle, bring it to the host's attention
ih_no_ctxsw: ih_no_fwmthd:
mov $r11 0x104 mov $r11 0x104 // FIFO | CHSW
not b32 $r11 not b32 $r11
and $r11 $r10 $r11 and $r11 $r10 $r11
bra e #ih_no_other bra e #ih_no_other
mov $r10 0xc1c nv_iowr(NV_PGRAPH_FECS_INTR_UP_SET, 0, $r11)
shl b32 $r10 6
iowr I[$r10] $r11 // INTR_UP_SET
// ack, and wake up main() // ack, and wake up main()
ih_no_other: ih_no_other:
iowr I[$r0 + 0x100] $r10 // INTR_ACK nv_iowr(NV_PGRAPH_FECS_INTR_ACK, 0, $r10)
pop $r15 pop $r15
pop $r14 pop $r14
@@ -370,12 +374,10 @@ ih:
#if CHIPSET < GK100 #if CHIPSET < GK100
// Not real sure, but, MEM_CMD 7 will hang forever if this isn't done // Not real sure, but, MEM_CMD 7 will hang forever if this isn't done
ctx_4160s: ctx_4160s:
mov $r14 0x4160
sethi $r14 0x400000
mov $r15 1 mov $r15 1
call #nv_wr32 nv_wr32(0x404160, $r15)
ctx_4160s_wait: ctx_4160s_wait:
call #nv_rd32 nv_rd32($r15, 0x404160)
xbit $r15 $r15 4 xbit $r15 $r15 4
bra e #ctx_4160s_wait bra e #ctx_4160s_wait
ret ret
@@ -384,10 +386,8 @@ ctx_4160s:
// to hang with STATUS=0x00000007 until it's cleared.. fbcon can // to hang with STATUS=0x00000007 until it's cleared.. fbcon can
// still function with it set however... // still function with it set however...
ctx_4160c: ctx_4160c:
mov $r14 0x4160
sethi $r14 0x400000
clear b32 $r15 clear b32 $r15
call #nv_wr32 nv_wr32(0x404160, $r15)
ret ret
#endif #endif
@@ -396,18 +396,14 @@ ctx_4160c:
// In: $r15 value to set 0x404170 to // In: $r15 value to set 0x404170 to
// //
ctx_4170s: ctx_4170s:
mov $r14 0x4170
sethi $r14 0x400000
or $r15 0x10 or $r15 0x10
call #nv_wr32 nv_wr32(0x404170, $r15)
ret ret
// Waits for a ctx_4170s() call to complete // Waits for a ctx_4170s() call to complete
// //
ctx_4170w: ctx_4170w:
mov $r14 0x4170 nv_rd32($r15, 0x404170)
sethi $r14 0x400000
call #nv_rd32
and $r15 0x10 and $r15 0x10
bra ne #ctx_4170w bra ne #ctx_4170w
ret ret
@@ -419,16 +415,18 @@ ctx_4170w:
// funny things happen. // funny things happen.
// //
ctx_redswitch: ctx_redswitch:
mov $r14 0x614 mov $r14 NV_PGRAPH_FECS_RED_SWITCH_ENABLE_GPC
shl b32 $r14 6 or $r14 NV_PGRAPH_FECS_RED_SWITCH_POWER_ROP
mov $r15 0x270 or $r14 NV_PGRAPH_FECS_RED_SWITCH_POWER_GPC
iowr I[$r14] $r15 // HUB_RED_SWITCH = ENABLE_GPC, POWER_ALL or $r14 NV_PGRAPH_FECS_RED_SWITCH_POWER_MAIN
nv_iowr(NV_PGRAPH_FECS_RED_SWITCH, 0, $r14)
mov $r15 8 mov $r15 8
ctx_redswitch_delay: ctx_redswitch_delay:
sub b32 $r15 1 sub b32 $r15 1
bra ne #ctx_redswitch_delay bra ne #ctx_redswitch_delay
mov $r15 0x770 or $r14 NV_PGRAPH_FECS_RED_SWITCH_ENABLE_ROP
iowr I[$r14] $r15 // HUB_RED_SWITCH = ENABLE_ALL, POWER_ALL or $r14 NV_PGRAPH_FECS_RED_SWITCH_ENABLE_MAIN
nv_iowr(NV_PGRAPH_FECS_RED_SWITCH, 0, $r14)
ret ret
// Not a clue what this is for, except that unless the value is 0x10, the // Not a clue what this is for, except that unless the value is 0x10, the
@@ -437,15 +435,18 @@ ctx_redswitch:
// In: $r15 value to set to (0x00/0x10 are used) // In: $r15 value to set to (0x00/0x10 are used)
// //
ctx_86c: ctx_86c:
mov $r14 0x86c nv_iowr(NV_PGRAPH_FECS_UNK86C, 0, $r15)
shl b32 $r14 6 nv_wr32(0x408a14, $r15)
iowr I[$r14] $r15 // HUB(0x86c) = val nv_wr32(NV_PGRAPH_GPCX_GPCCS_UNK86C, $r15)
mov $r14 -0x75ec ret
sethi $r14 0x400000
call #nv_wr32 // ROP(0xa14) = val // In: $r15 NV_PGRAPH_FECS_MEM_CMD_*
mov $r14 -0x5794 ctx_mem:
sethi $r14 0x410000 nv_iowr(NV_PGRAPH_FECS_MEM_CMD, 0, $r15)
call #nv_wr32 // GPC(0x86c) = val ctx_mem_wait:
nv_iord($r15, NV_PGRAPH_FECS_MEM_CMD, 0)
or $r15 $r15
bra ne #ctx_mem_wait
ret ret
// ctx_load - load's a channel's ctxctl data, and selects its vm // ctx_load - load's a channel's ctxctl data, and selects its vm
@@ -457,23 +458,14 @@ ctx_load:
// switch to channel, somewhat magic in parts.. // switch to channel, somewhat magic in parts..
mov $r10 12 // DONE_UNK12 mov $r10 12 // DONE_UNK12
call #wait_donez call(wait_donez)
mov $r1 0xa24 clear b32 $r15
shl b32 $r1 6 nv_iowr(0x409a24, 0, $r15)
iowr I[$r1 + 0x000] $r0 // 0x409a24 nv_iowr(NV_PGRAPH_FECS_CHAN_NEXT, 0, $r2)
mov $r3 0xb00 nv_iowr(NV_PGRAPH_FECS_MEM_CHAN, 0, $r2)
shl b32 $r3 6 mov $r15 NV_PGRAPH_FECS_MEM_CMD_LOAD_CHAN
iowr I[$r3 + 0x100] $r2 // CHAN_NEXT call(ctx_mem)
mov $r1 0xa0c nv_iowr(NV_PGRAPH_FECS_CHAN_ADDR, 0, $r2)
shl b32 $r1 6
mov $r4 7
iowr I[$r1 + 0x000] $r2 // MEM_CHAN
iowr I[$r1 + 0x100] $r4 // MEM_CMD
ctx_chan_wait_0:
iord $r4 I[$r1 + 0x100]
and $r4 0x1f
bra ne #ctx_chan_wait_0
iowr I[$r3 + 0x000] $r2 // CHAN_CUR
// load channel header, fetch PGRAPH context pointer // load channel header, fetch PGRAPH context pointer
mov $xtargets $r0 mov $xtargets $r0
@@ -482,14 +474,10 @@ ctx_load:
add b32 $r2 2 add b32 $r2 2
trace_set(T_LCHAN) trace_set(T_LCHAN)
mov $r1 0xa04 nv_iowr(NV_PGRAPH_FECS_MEM_BASE, 0, $r2)
shl b32 $r1 6 imm32($r2, NV_PGRAPH_FECS_MEM_TARGET_UNK31)
iowr I[$r1 + 0x000] $r2 // MEM_BASE or $r2 NV_PGRAPH_FECS_MEM_TARGET_AS_VRAM
mov $r1 0xa20 nv_iowr(NV_PGRAPH_FECS_MEM_TARGET, 0, $r2)
shl b32 $r1 6
mov $r2 0x0002
sethi $r2 0x80000000
iowr I[$r1 + 0x000] $r2 // MEM_TARGET = vram
mov $r1 0x10 // chan + 0x0210 mov $r1 0x10 // chan + 0x0210
mov $r2 #xfer_data mov $r2 #xfer_data
sethi $r2 0x00020000 // 16 bytes sethi $r2 0x00020000 // 16 bytes
@@ -507,13 +495,9 @@ ctx_load:
// set transfer base to start of context, and fetch context header // set transfer base to start of context, and fetch context header
trace_set(T_LCTXH) trace_set(T_LCTXH)
mov $r2 0xa04 nv_iowr(NV_PGRAPH_FECS_MEM_BASE, 0, $r1)
shl b32 $r2 6 mov $r2 NV_PGRAPH_FECS_MEM_TARGET_AS_VM
iowr I[$r2 + 0x000] $r1 // MEM_BASE nv_iowr(NV_PGRAPH_FECS_MEM_TARGET, 0, $r2)
mov $r2 1
mov $r1 0xa20
shl b32 $r1 6
iowr I[$r1 + 0x000] $r2 // MEM_TARGET = vm
mov $r1 #chan_data mov $r1 #chan_data
sethi $r1 0x00060000 // 256 bytes sethi $r1 0x00060000 // 256 bytes
xdld $r0 $r1 xdld $r0 $r1
@@ -532,21 +516,15 @@ ctx_load:
// //
ctx_chan: ctx_chan:
#if CHIPSET < GK100 #if CHIPSET < GK100
call #ctx_4160s call(ctx_4160s)
#endif #endif
call #ctx_load call(ctx_load)
mov $r10 12 // DONE_UNK12 mov $r10 12 // DONE_UNK12
call #wait_donez call(wait_donez)
mov $r1 0xa10 mov $r15 5 // MEM_CMD 5 ???
shl b32 $r1 6 call(ctx_mem)
mov $r2 5
iowr I[$r1 + 0x000] $r2 // MEM_CMD = 5 (???)
ctx_chan_wait:
iord $r2 I[$r1 + 0x000]
or $r2 $r2
bra ne #ctx_chan_wait
#if CHIPSET < GK100 #if CHIPSET < GK100
call #ctx_4160c call(ctx_4160c)
#endif #endif
ret ret
@@ -562,9 +540,7 @@ ctx_chan:
ctx_mmio_exec: ctx_mmio_exec:
// set transfer base to be the mmio list // set transfer base to be the mmio list
ld b32 $r3 D[$r0 + #chan_mmio_address] ld b32 $r3 D[$r0 + #chan_mmio_address]
mov $r2 0xa04 nv_iowr(NV_PGRAPH_FECS_MEM_BASE, 0, $r3)
shl b32 $r2 6
iowr I[$r2 + 0x000] $r3 // MEM_BASE
clear b32 $r3 clear b32 $r3
ctx_mmio_loop: ctx_mmio_loop:
@@ -580,7 +556,7 @@ ctx_mmio_exec:
ctx_mmio_pull: ctx_mmio_pull:
ld b32 $r14 D[$r4 + #xfer_data + 0x00] ld b32 $r14 D[$r4 + #xfer_data + 0x00]
ld b32 $r15 D[$r4 + #xfer_data + 0x04] ld b32 $r15 D[$r4 + #xfer_data + 0x04]
call #nv_wr32 call(nv_wr32)
// next! // next!
add b32 $r3 8 add b32 $r3 8
@@ -590,7 +566,7 @@ ctx_mmio_exec:
// set transfer base back to the current context // set transfer base back to the current context
ctx_mmio_done: ctx_mmio_done:
ld b32 $r3 D[$r0 + #ctx_current] ld b32 $r3 D[$r0 + #ctx_current]
iowr I[$r2 + 0x000] $r3 // MEM_BASE nv_iowr(NV_PGRAPH_FECS_MEM_BASE, 0, $r3)
// disable the mmio list now, we don't need/want to execute it again // disable the mmio list now, we don't need/want to execute it again
st b32 D[$r0 + #chan_mmio_count] $r0 st b32 D[$r0 + #chan_mmio_count] $r0
@@ -610,12 +586,10 @@ ctx_mmio_exec:
// //
ctx_xfer: ctx_xfer:
// according to mwk, some kind of wait for idle // according to mwk, some kind of wait for idle
mov $r15 0xc00
shl b32 $r15 6
mov $r14 4 mov $r14 4
iowr I[$r15 + 0x200] $r14 nv_iowr(0x409c08, 0, $r14)
ctx_xfer_idle: ctx_xfer_idle:
iord $r14 I[$r15 + 0x000] nv_iord($r14, 0x409c00, 0)
and $r14 0x2000 and $r14 0x2000
bra ne #ctx_xfer_idle bra ne #ctx_xfer_idle
@@ -623,50 +597,42 @@ ctx_xfer:
bra $p2 #ctx_xfer_pre_load bra $p2 #ctx_xfer_pre_load
ctx_xfer_pre: ctx_xfer_pre:
mov $r15 0x10 mov $r15 0x10
call #ctx_86c call(ctx_86c)
#if CHIPSET < GK100 #if CHIPSET < GK100
call #ctx_4160s call(ctx_4160s)
#endif #endif
bra not $p1 #ctx_xfer_exec bra not $p1 #ctx_xfer_exec
ctx_xfer_pre_load: ctx_xfer_pre_load:
mov $r15 2 mov $r15 2
call #ctx_4170s call(ctx_4170s)
call #ctx_4170w call(ctx_4170w)
call #ctx_redswitch call(ctx_redswitch)
clear b32 $r15 clear b32 $r15
call #ctx_4170s call(ctx_4170s)
call #ctx_load call(ctx_load)
// fetch context pointer, and initiate xfer on all GPCs // fetch context pointer, and initiate xfer on all GPCs
ctx_xfer_exec: ctx_xfer_exec:
ld b32 $r1 D[$r0 + #ctx_current] ld b32 $r1 D[$r0 + #ctx_current]
mov $r2 0x414
shl b32 $r2 6 clear b32 $r2
iowr I[$r2 + 0x000] $r0 // BAR_STATUS = reset nv_iowr(NV_PGRAPH_FECS_BAR, 0, $r2)
mov $r14 -0x5b00
sethi $r14 0x410000 nv_wr32(0x41a500, $r1) // GPC_BCAST_WRCMD_DATA = ctx pointer
mov b32 $r15 $r1
call #nv_wr32 // GPC_BCAST_WRCMD_DATA = ctx pointer
add b32 $r14 4
xbit $r15 $flags $p1 xbit $r15 $flags $p1
xbit $r2 $flags $p2 xbit $r2 $flags $p2
shl b32 $r2 1 shl b32 $r2 1
or $r15 $r2 or $r15 $r2
call #nv_wr32 // GPC_BCAST_WRCMD_CMD = GPC_XFER(type) nv_wr32(0x41a504, $r15) // GPC_BCAST_WRCMD_CMD = GPC_XFER(type)
// strands // strands
mov $r1 0x4afc call(strand_pre)
sethi $r1 0x20000 clear b32 $r2
mov $r2 0xc nv_iowr(NV_PGRAPH_FECS_STRAND_SELECT, 0x3f, $r2)
iowr I[$r1] $r2 // STRAND_CMD(0x3f) = 0x0c xbit $r2 $flags $p1 // SAVE/LOAD
call #strand_wait add b32 $r2 NV_PGRAPH_FECS_STRAND_CMD_SAVE
mov $r2 0x47fc nv_iowr(NV_PGRAPH_FECS_STRAND_CMD, 0x3f, $r2)
sethi $r2 0x20000
iowr I[$r2] $r0 // STRAND_FIRST_GENE(0x3f) = 0x00
xbit $r2 $flags $p1
add b32 $r2 3
iowr I[$r1] $r2 // STRAND_CMD(0x3f) = 0x03/0x04 (SAVE/LOAD)
// mmio context // mmio context
xbit $r10 $flags $p1 // direction xbit $r10 $flags $p1 // direction
@@ -675,48 +641,42 @@ ctx_xfer:
ld b32 $r12 D[$r0 + #hub_mmio_list_head] ld b32 $r12 D[$r0 + #hub_mmio_list_head]
ld b32 $r13 D[$r0 + #hub_mmio_list_tail] ld b32 $r13 D[$r0 + #hub_mmio_list_tail]
mov $r14 0 // not multi mov $r14 0 // not multi
call #mmctx_xfer call(mmctx_xfer)
// wait for GPCs to all complete // wait for GPCs to all complete
mov $r10 8 // DONE_BAR mov $r10 8 // DONE_BAR
call #wait_doneo call(wait_doneo)
// wait for strand xfer to complete // wait for strand xfer to complete
call #strand_wait call(strand_wait)
// post-op // post-op
bra $p1 #ctx_xfer_post bra $p1 #ctx_xfer_post
mov $r10 12 // DONE_UNK12 mov $r10 12 // DONE_UNK12
call #wait_donez call(wait_donez)
mov $r1 0xa10 mov $r15 5 // MEM_CMD 5 ???
shl b32 $r1 6 call(ctx_mem)
mov $r2 5
iowr I[$r1] $r2 // MEM_CMD
ctx_xfer_post_save_wait:
iord $r2 I[$r1]
or $r2 $r2
bra ne #ctx_xfer_post_save_wait
bra $p2 #ctx_xfer_done bra $p2 #ctx_xfer_done
ctx_xfer_post: ctx_xfer_post:
mov $r15 2 mov $r15 2
call #ctx_4170s call(ctx_4170s)
clear b32 $r15 clear b32 $r15
call #ctx_86c call(ctx_86c)
call #strand_post call(strand_post)
call #ctx_4170w call(ctx_4170w)
clear b32 $r15 clear b32 $r15
call #ctx_4170s call(ctx_4170s)
bra not $p1 #ctx_xfer_no_post_mmio bra not $p1 #ctx_xfer_no_post_mmio
ld b32 $r1 D[$r0 + #chan_mmio_count] ld b32 $r1 D[$r0 + #chan_mmio_count]
or $r1 $r1 or $r1 $r1
bra e #ctx_xfer_no_post_mmio bra e #ctx_xfer_no_post_mmio
call #ctx_mmio_exec call(ctx_mmio_exec)
ctx_xfer_no_post_mmio: ctx_xfer_no_post_mmio:
#if CHIPSET < GK100 #if CHIPSET < GK100
call #ctx_4160c call(ctx_4160c)
#endif #endif
ctx_xfer_done: ctx_xfer_done:

40
drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnv108.fuc5 Normal file
View File

@@ -0,0 +1,40 @@
/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
#define CHIPSET GK208
#include "macros.fuc"
.section #nv108_grhub_data
#define INCLUDE_DATA
#include "com.fuc"
#include "hub.fuc"
#undef INCLUDE_DATA
.section #nv108_grhub_code
#define INCLUDE_CODE
bra #init
#include "com.fuc"
#include "hub.fuc"
.align 256
#undef INCLUDE_CODE

916
drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnv108.fuc5.h Normal file
View File

@@ -0,0 +1,916 @@
uint32_t nv108_grhub_data[] = {
/* 0x0000: hub_mmio_list_head */
0x00000300,
/* 0x0004: hub_mmio_list_tail */
0x00000304,
/* 0x0008: gpc_count */
0x00000000,
/* 0x000c: rop_count */
0x00000000,
/* 0x0010: cmd_queue */
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
/* 0x0058: ctx_current */
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
/* 0x0100: chan_data */
/* 0x0100: chan_mmio_count */
0x00000000,
/* 0x0104: chan_mmio_address */
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
/* 0x0200: xfer_data */
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
/* 0x0300: hub_mmio_list_base */
0x0417e91c,
};
uint32_t nv108_grhub_code[] = {
0x030e0ef5,
/* 0x0004: queue_put */
0x9800d898,
0x86f001d9,
0xf489a408,
0x020f0b1b,
0x0002f87e,
/* 0x001a: queue_put_next */
0x98c400f8,
0x0384b607,
0xb6008dbb,
0x8eb50880,
0x018fb500,
0xf00190b6,
0xd9b50f94,
/* 0x0037: queue_get */
0xf400f801,
0xd8980131,
0x01d99800,
0x0bf489a4,
0x0789c421,
0xbb0394b6,
0x90b6009d,
0x009e9808,
0xb6019f98,
0x84f00180,
0x00d8b50f,
/* 0x0063: queue_get_done */
0xf80132f4,
/* 0x0065: nv_rd32 */
0xf0ecb200,
0x00801fc9,
0x0cf601ca,
/* 0x0073: nv_rd32_wait */
0x8c04bd00,
0xcf01ca00,
0xccc800cc,
0xf61bf41f,
0xec7e060a,
0x008f0000,
0xffcf01cb,
/* 0x008f: nv_wr32 */
0x8000f800,
0xf601cc00,
0x04bd000f,
0xc9f0ecb2,
0x1ec9f01f,
0x01ca0080,
0xbd000cf6,
/* 0x00a9: nv_wr32_wait */
0xca008c04,
0x00cccf01,
0xf41fccc8,
0x00f8f61b,
/* 0x00b8: wait_donez */
0x99f094bd,
0x37008000,
0x0009f602,
0x008004bd,
0x0af60206,
/* 0x00cf: wait_donez_ne */
0x8804bd00,
0xcf010000,
0x8aff0088,
0xf61bf488,
0x99f094bd,
0x17008000,
0x0009f602,
0x00f804bd,
/* 0x00ec: wait_doneo */
0x99f094bd,
0x37008000,
0x0009f602,
0x008004bd,
0x0af60206,
/* 0x0103: wait_doneo_e */
0x8804bd00,
0xcf010000,
0x8aff0088,
0xf60bf488,
0x99f094bd,
0x17008000,
0x0009f602,
0x00f804bd,
/* 0x0120: mmctx_size */
/* 0x0122: nv_mmctx_size_loop */
0xe89894bd,
0x1a85b600,
0xb60180b6,
0x98bb0284,
0x04e0b600,
0x1bf4efa4,
0xf89fb2ec,
/* 0x013d: mmctx_xfer */
0xf094bd00,
0x00800199,
0x09f60237,
0xbd04bd00,
0x05bbfd94,
0x800f0bf4,
0xf601c400,
0x04bd000b,
/* 0x015f: mmctx_base_disabled */
0xfd0099f0,
0x0bf405ee,
0xc6008018,
0x000ef601,
0x008004bd,
0x0ff601c7,
0xf004bd00,
/* 0x017a: mmctx_multi_disabled */
0xabc80199,
0x10b4b600,
0xc80cb9f0,
0xe4b601ae,
0x05befd11,
0x01c50080,
0xbd000bf6,
/* 0x0195: mmctx_exec_loop */
/* 0x0195: mmctx_wait_free */
0xc5008e04,
0x00eecf01,
0xf41fe4f0,
0xce98f60b,
0x05e9fd00,
0x01c80080,
0xbd000ef6,
0x04c0b604,
0x1bf4cda4,
0x02abc8df,
/* 0x01bf: mmctx_fini_wait */
0x8b1c1bf4,
0xcf01c500,
0xb4f000bb,
0x10b4b01f,
0x0af31bf4,
0x00b87e02,
0x250ef400,
/* 0x01d8: mmctx_stop */
0xb600abc8,
0xb9f010b4,
0x12b9f00c,
0x01c50080,
0xbd000bf6,
/* 0x01ed: mmctx_stop_wait */
0xc5008b04,
0x00bbcf01,
0xf412bbc8,
/* 0x01fa: mmctx_done */
0x94bdf61b,
0x800199f0,
0xf6021700,
0x04bd0009,
/* 0x020a: strand_wait */
0xa0f900f8,
0xb87e020a,
0xa0fc0000,
/* 0x0216: strand_pre */
0x0c0900f8,
0x024afc80,
0xbd0009f6,
0x020a7e04,
/* 0x0227: strand_post */
0x0900f800,
0x4afc800d,
0x0009f602,
0x0a7e04bd,
0x00f80002,
/* 0x0238: strand_set */
0xfc800f0c,
0x0cf6024f,
0x0c04bd00,
0x4afc800b,
0x000cf602,
0xfc8004bd,
0x0ef6024f,
0x0c04bd00,
0x4afc800a,
0x000cf602,
0x0a7e04bd,
0x00f80002,
/* 0x0268: strand_ctx_init */
0x99f094bd,
0x37008003,
0x0009f602,
0x167e04bd,
0x030e0002,
0x0002387e,
0xfc80c4bd,
0x0cf60247,
0x0c04bd00,
0x4afc8001,
0x000cf602,
0x0a7e04bd,
0x0c920002,
0x46fc8001,
0x000cf602,
0x020c04bd,
0x024afc80,
0xbd000cf6,
0x020a7e04,
0x02277e00,
0x42008800,
0x20008902,
0x0099cf02,
/* 0x02c7: ctx_init_strand_loop */
0xf608fe95,
0x8ef6008e,
0x808acf40,
0xb606a5b6,
0xeabb01a0,
0x0480b600,
0xf40192b6,
0xe4b6e81b,
0xf2efbc08,
0x99f094bd,
0x17008003,
0x0009f602,
0x00f804bd,
/* 0x02f8: error */
0x02050080,
0xbd000ff6,
0x80010f04,
0xf6030700,
0x04bd000f,
/* 0x030e: init */
0x04bd00f8,
0x410007fe,
0x11cf4200,
0x0911e700,
0x0814b601,
0x020014fe,
0x12004002,
0xbd0002f6,
0x05c94104,
0xbd0010fe,
0x07004024,
0xbd0002f6,
0x20034204,
0x01010080,
0xbd0002f6,
0x20044204,
0x01010480,
0xbd0002f6,
0x200b4204,
0x01010880,
0xbd0002f6,
0x200c4204,
0x01011c80,
0xbd0002f6,
0x01039204,
0x03090080,
0xbd0003f6,
0x87044204,
0xf6040040,
0x04bd0002,
0x00400402,
0x0002f603,
0x31f404bd,
0x96048e10,
0x00657e40,
0xc7feb200,
0x01b590f1,
0x1ff4f003,
0x01020fb5,
0x041fbb01,
0x800112b6,
0xf6010300,
0x04bd0001,
0x01040080,
0xbd0001f6,
0x01004104,
0x627e020f,
0x717e0006,
0x100f0006,
0x0006b37e,
0x98000e98,
0x207e010f,
0x14950001,
0xc0008008,
0x0004f601,
0x008004bd,
0x04f601c1,
0xb704bd00,
0xbb130030,
0xf5b6001f,
0xd3008002,
0x000ff601,
0x15b604bd,
0x0110b608,
0xb20814b6,
0x02687e1f,
0x001fbb00,
0x84020398,
/* 0x041f: init_gpc */
0xb8502000,
0x0008044e,
0x8f7e1fb2,
0x4eb80000,
0xbd00010c,
0x008f7ef4,
0x044eb800,
0x8f7e0001,
0x4eb80000,
0x0f000100,
0x008f7e02,
0x004eb800,
/* 0x044e: init_gpc_wait */
0x657e0008,
0xffc80000,
0xf90bf41f,
0x08044eb8,
0x00657e00,
0x001fbb00,
0x800040b7,
0xf40132b6,
0x000fb41b,
0x0006b37e,
0x627e000f,
0x00800006,
0x01f60201,
0xbd04bd00,
0x1f19f014,
0x02300080,
0xbd0001f6,
/* 0x0491: main */
0x0031f404,
0x0d0028f4,
0x00377e10,
0xf401f400,
0x4001e4b1,
0x00c71bf5,
0x99f094bd,
0x37008004,
0x0009f602,
0x008104bd,
0x11cf02c0,
0xc1008200,
0x0022cf02,
0xf41f13c8,
0x23c8770b,
0x550bf41f,
0x12b220f9,
0x99f094bd,
0x37008007,
0x0009f602,
0x32f404bd,
0x0231f401,
0x0008367e,
0x99f094bd,
0x17008007,
0x0009f602,
0x20fc04bd,
0x99f094bd,
0x37008006,
0x0009f602,
0x31f404bd,
0x08367e01,
0xf094bd00,
0x00800699,
0x09f60217,
0xf404bd00,
/* 0x0522: chsw_prev_no_next */
0x20f92f0e,
0x32f412b2,
0x0232f401,
0x0008367e,
0x008020fc,
0x02f602c0,
0xf404bd00,
/* 0x053e: chsw_no_prev */
0x23c8130e,
0x0d0bf41f,
0xf40131f4,
0x367e0232,
/* 0x054e: chsw_done */
0x01020008,
0x02c30080,
0xbd0002f6,
0xf094bd04,
0x00800499,
0x09f60217,
0xf504bd00,
/* 0x056b: main_not_ctx_switch */
0xb0ff2a0e,
0x1bf401e4,
0x7ef2b20c,
0xf40007d6,
/* 0x057a: main_not_ctx_chan */
0xe4b0400e,
0x2c1bf402,
0x99f094bd,
0x37008007,
0x0009f602,
0x32f404bd,
0x0232f401,
0x0008367e,
0x99f094bd,
0x17008007,
0x0009f602,
0x0ef404bd,
/* 0x05a9: main_not_ctx_save */
0x10ef9411,
0x7e01f5f0,
0xf50002f8,
/* 0x05b7: main_done */
0xbdfede0e,
0x1f29f024,
0x02300080,
0xbd0002f6,
0xcc0ef504,
/* 0x05c9: ih */
0xfe80f9fe,
0x80f90188,
0xa0f990f9,
0xd0f9b0f9,
0xf0f9e0f9,
0x004a04bd,
0x00aacf02,
0xf404abc4,
0x100d230b,
0xcf1a004e,
0x004f00ee,
0x00ffcf19,
0x0000047e,
0x0400b0b7,
0x0040010e,
0x000ef61d,
/* 0x060a: ih_no_fifo */
0xabe404bd,
0x0bf40100,
0x4e100d0c,
0x047e4001,
/* 0x061a: ih_no_ctxsw */
0xabe40000,
0x0bf40400,
0x01004b10,
0x448ebfb2,
0x8f7e4001,
/* 0x062e: ih_no_fwmthd */
0x044b0000,
0xffb0bd01,
0x0bf4b4ab,
0x0700800c,
0x000bf603,
/* 0x0642: ih_no_other */
0x004004bd,
0x000af601,
0xf0fc04bd,
0xd0fce0fc,
0xa0fcb0fc,
0x80fc90fc,
0xfc0088fe,
0x0032f480,
/* 0x0662: ctx_4170s */
0xf5f001f8,
0x8effb210,
0x7e404170,
0xf800008f,
/* 0x0671: ctx_4170w */
0x41708e00,
0x00657e40,
0xf0ffb200,
0x1bf410f4,
/* 0x0683: ctx_redswitch */
0x4e00f8f3,
0xe5f00200,
0x20e5f040,
0x8010e5f0,
0xf6018500,
0x04bd000e,
/* 0x069a: ctx_redswitch_delay */
0xf2b6080f,
0xfd1bf401,
0x0400e5f1,
0x0100e5f1,
0x01850080,
0xbd000ef6,
/* 0x06b3: ctx_86c */
0x8000f804,
0xf6022300,
0x04bd000f,
0x148effb2,
0x8f7e408a,
0xffb20000,
0x41a88c8e,
0x00008f7e,
/* 0x06d2: ctx_mem */
0x008000f8,
0x0ff60284,
/* 0x06db: ctx_mem_wait */
0x8f04bd00,
0xcf028400,
0xfffd00ff,
0xf61bf405,
/* 0x06ea: ctx_load */
0x94bd00f8,
0x800599f0,
0xf6023700,
0x04bd0009,
0xb87e0c0a,
0xf4bd0000,
0x02890080,
0xbd000ff6,
0xc1008004,
0x0002f602,
0x008004bd,
0x02f60283,
0x0f04bd00,
0x06d27e07,
0xc0008000,
0x0002f602,
0x0bfe04bd,
0x1f2af000,
0xb60424b6,
0x94bd0220,
0x800899f0,
0xf6023700,
0x04bd0009,
0x02810080,
0xbd0002f6,
0x0000d204,
0x25f08000,
0x88008002,
0x0002f602,
0x100104bd,
0xf0020042,
0x12fa0223,
0xbd03f805,
0x0899f094,
0x02170080,
0xbd0009f6,
0x81019804,
0x981814b6,
0x25b68002,
0x0512fd08,
0xbd1601b5,
0x0999f094,
0x02370080,
0xbd0009f6,
0x81008004,
0x0001f602,
0x010204bd,
0x02880080,
0xbd0002f6,
0x01004104,
0xfa0613f0,
0x03f80501,
0x99f094bd,
0x17008009,
0x0009f602,
0x94bd04bd,
0x800599f0,
0xf6021700,
0x04bd0009,
/* 0x07d6: ctx_chan */
0xea7e00f8,
0x0c0a0006,
0x0000b87e,
0xd27e050f,
0x00f80006,
/* 0x07e8: ctx_mmio_exec */
0x80410398,
0xf6028100,
0x04bd0003,
/* 0x07f6: ctx_mmio_loop */
0x34c434bd,
0x0e1bf4ff,
0xf0020045,
0x35fa0653,
/* 0x0807: ctx_mmio_pull */
0x9803f805,
0x4f98804e,
0x008f7e81,
0x0830b600,
0xf40112b6,
/* 0x081a: ctx_mmio_done */
0x0398df1b,
0x81008016,
0x0003f602,
0x00b504bd,
0x01004140,
0xfa0613f0,
0x03f80601,
/* 0x0836: ctx_xfer */
0x040e00f8,
0x03020080,
0xbd000ef6,
/* 0x0841: ctx_xfer_idle */
0x00008e04,
0x00eecf03,
0x2000e4f1,
0xf4f51bf4,
0x02f40611,
/* 0x0855: ctx_xfer_pre */
0x7e100f0c,
0xf40006b3,
/* 0x085e: ctx_xfer_pre_load */
0x020f1b11,
0x0006627e,
0x0006717e,
0x0006837e,
0x627ef4bd,
0xea7e0006,
/* 0x0876: ctx_xfer_exec */
0x01980006,
0x8024bd16,
0xf6010500,
0x04bd0002,
0x008e1fb2,
0x8f7e41a5,
0xfcf00000,
0x022cf001,
0xfd0124b6,
0xffb205f2,
0x41a5048e,
0x00008f7e,
0x0002167e,
0xfc8024bd,
0x02f60247,
0xf004bd00,
0x20b6012c,
0x4afc8003,
0x0002f602,
0xacf004bd,
0x06a5f001,
0x0c98000b,
0x010d9800,
0x3d7e000e,
0x080a0001,
0x0000ec7e,
0x00020a7e,
0x0a1201f4,
0x00b87e0c,
0x7e050f00,
0xf40006d2,
/* 0x08f2: ctx_xfer_post */
0x020f2d02,
0x0006627e,
0xb37ef4bd,
0x277e0006,
0x717e0002,
0xf4bd0006,
0x0006627e,
0x981011f4,
0x11fd4001,
0x070bf405,
0x0007e87e,
/* 0x091c: ctx_xfer_no_post_mmio */
/* 0x091c: ctx_xfer_done */
0x000000f8,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
};

1256
drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc.h
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File diff suppressed because it is too large Load Diff

1256
drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvd7.fuc.h
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File diff suppressed because it is too large Load Diff

1212
drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc.h
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File diff suppressed because it is too large Load Diff

1212
drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvf0.fuc.h
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File diff suppressed because it is too large Load Diff

141
drivers/gpu/drm/nouveau/core/engine/graph/fuc/macros.fuc
View File

@@ -28,28 +28,135 @@
#define GF117 0xd7 #define GF117 0xd7
#define GK100 0xe0 #define GK100 0xe0
#define GK110 0xf0 #define GK110 0xf0
#define GK208 0x108
#define NV_PGRAPH_FECS_INTR_ACK 0x409004
#define NV_PGRAPH_FECS_INTR 0x409008
#define NV_PGRAPH_FECS_INTR_FWMTHD 0x00000400
#define NV_PGRAPH_FECS_INTR_CHSW 0x00000100
#define NV_PGRAPH_FECS_INTR_FIFO 0x00000004
#define NV_PGRAPH_FECS_INTR_MODE 0x40900c
#define NV_PGRAPH_FECS_INTR_MODE_FIFO 0x00000004
#define NV_PGRAPH_FECS_INTR_MODE_FIFO_LEVEL 0x00000004
#define NV_PGRAPH_FECS_INTR_MODE_FIFO_EDGE 0x00000000
#define NV_PGRAPH_FECS_INTR_EN_SET 0x409010
#define NV_PGRAPH_FECS_INTR_EN_SET_FIFO 0x00000004
#define NV_PGRAPH_FECS_INTR_ROUTE 0x40901c
#define NV_PGRAPH_FECS_ACCESS 0x409048
#define NV_PGRAPH_FECS_ACCESS_FIFO 0x00000002
#define NV_PGRAPH_FECS_FIFO_DATA 0x409064
#define NV_PGRAPH_FECS_FIFO_CMD 0x409068
#define NV_PGRAPH_FECS_FIFO_ACK 0x409074
#define NV_PGRAPH_FECS_CAPS 0x409108
#define NV_PGRAPH_FECS_SIGNAL 0x409400 #define NV_PGRAPH_FECS_SIGNAL 0x409400
#define NV_PGRAPH_FECS_IROUTE 0x409404
#define NV_PGRAPH_FECS_BAR_MASK0 0x40940c
#define NV_PGRAPH_FECS_BAR_MASK1 0x409410
#define NV_PGRAPH_FECS_BAR 0x409414
#define NV_PGRAPH_FECS_BAR_SET 0x409418
#define NV_PGRAPH_FECS_RED_SWITCH 0x409614
#define NV_PGRAPH_FECS_RED_SWITCH_ENABLE_ROP 0x00000400
#define NV_PGRAPH_FECS_RED_SWITCH_ENABLE_GPC 0x00000200
#define NV_PGRAPH_FECS_RED_SWITCH_ENABLE_MAIN 0x00000100
#define NV_PGRAPH_FECS_RED_SWITCH_POWER_ROP 0x00000040
#define NV_PGRAPH_FECS_RED_SWITCH_POWER_GPC 0x00000020
#define NV_PGRAPH_FECS_RED_SWITCH_POWER_MAIN 0x00000010
#define NV_PGRAPH_FECS_RED_SWITCH_PAUSE_GPC 0x00000002
#define NV_PGRAPH_FECS_RED_SWITCH_PAUSE_MAIN 0x00000001
#define NV_PGRAPH_FECS_MMCTX_SAVE_SWBASE 0x409700
#define NV_PGRAPH_FECS_MMCTX_LOAD_SWBASE 0x409704
#define NV_PGRAPH_FECS_MMCTX_LOAD_COUNT 0x40974c
#define NV_PGRAPH_FECS_MMCTX_SAVE_SWBASE 0x409700
#define NV_PGRAPH_FECS_MMCTX_LOAD_SWBASE 0x409704
#define NV_PGRAPH_FECS_MMCTX_BASE 0x409710
#define NV_PGRAPH_FECS_MMCTX_CTRL 0x409714
#define NV_PGRAPH_FECS_MMCTX_MULTI_STRIDE 0x409718
#define NV_PGRAPH_FECS_MMCTX_MULTI_MASK 0x40971c
#define NV_PGRAPH_FECS_MMCTX_QUEUE 0x409720
#define NV_PGRAPH_FECS_MMIO_CTRL 0x409728
#define NV_PGRAPH_FECS_MMIO_RDVAL 0x40972c
#define NV_PGRAPH_FECS_MMIO_WRVAL 0x409730
#define NV_PGRAPH_FECS_MMCTX_LOAD_COUNT 0x40974c
#if CHIPSET < GK110 #if CHIPSET < GK110
#define NV_PGRAPH_FECS_CC_SCRATCH_VAL(n) ((n) * 4 + 0x409800) #define NV_PGRAPH_FECS_CC_SCRATCH_VAL(n) ((n) * 4 + 0x409800)
#define NV_PGRAPH_FECS_CC_SCRATCH_SET(n) ((n) * 4 + 0x409820) #define NV_PGRAPH_FECS_CC_SCRATCH_SET(n) ((n) * 4 + 0x409820)
#define NV_PGRAPH_FECS_CC_SCRATCH_CLR(n) ((n) * 4 + 0x409840) #define NV_PGRAPH_FECS_CC_SCRATCH_CLR(n) ((n) * 4 + 0x409840)
#define NV_PGRAPH_FECS_UNK86C 0x40986c
#else #else
#define NV_PGRAPH_FECS_CC_SCRATCH_VAL(n) ((n) * 4 + 0x409800) #define NV_PGRAPH_FECS_CC_SCRATCH_VAL(n) ((n) * 4 + 0x409800)
#define NV_PGRAPH_FECS_CC_SCRATCH_CLR(n) ((n) * 4 + 0x409840) #define NV_PGRAPH_FECS_CC_SCRATCH_CLR(n) ((n) * 4 + 0x409840)
#define NV_PGRAPH_FECS_UNK86C 0x40988c
#define NV_PGRAPH_FECS_CC_SCRATCH_SET(n) ((n) * 4 + 0x4098c0) #define NV_PGRAPH_FECS_CC_SCRATCH_SET(n) ((n) * 4 + 0x4098c0)
#endif #endif
#define NV_PGRAPH_FECS_STRANDS_CNT 0x409880
#define NV_PGRAPH_FECS_STRAND_SAVE_SWBASE 0x409908
#define NV_PGRAPH_FECS_STRAND_LOAD_SWBASE 0x40990c
#define NV_PGRAPH_FECS_STRAND_WORDS 0x409910
#define NV_PGRAPH_FECS_STRAND_DATA 0x409918
#define NV_PGRAPH_FECS_STRAND_SELECT 0x40991c
#define NV_PGRAPH_FECS_STRAND_CMD 0x409928
#define NV_PGRAPH_FECS_STRAND_CMD_SEEK 0x00000001
#define NV_PGRAPH_FECS_STRAND_CMD_GET_INFO 0x00000002
#define NV_PGRAPH_FECS_STRAND_CMD_SAVE 0x00000003
#define NV_PGRAPH_FECS_STRAND_CMD_LOAD 0x00000004
#define NV_PGRAPH_FECS_STRAND_CMD_ACTIVATE_FILTER 0x0000000a
#define NV_PGRAPH_FECS_STRAND_CMD_DEACTIVATE_FILTER 0x0000000b
#define NV_PGRAPH_FECS_STRAND_CMD_ENABLE 0x0000000c
#define NV_PGRAPH_FECS_STRAND_CMD_DISABLE 0x0000000d
#define NV_PGRAPH_FECS_STRAND_FILTER 0x40993c
#define NV_PGRAPH_FECS_MEM_BASE 0x409a04
#define NV_PGRAPH_FECS_MEM_CHAN 0x409a0c
#define NV_PGRAPH_FECS_MEM_CMD 0x409a10
#define NV_PGRAPH_FECS_MEM_CMD_LOAD_CHAN 0x00000007
#define NV_PGRAPH_FECS_MEM_TARGET 0x409a20
#define NV_PGRAPH_FECS_MEM_TARGET_UNK31 0x80000000
#define NV_PGRAPH_FECS_MEM_TARGET_AS 0x0000001f
#define NV_PGRAPH_FECS_MEM_TARGET_AS_VM 0x00000001
#define NV_PGRAPH_FECS_MEM_TARGET_AS_VRAM 0x00000002
#define NV_PGRAPH_FECS_CHAN_ADDR 0x409b00
#define NV_PGRAPH_FECS_CHAN_NEXT 0x409b04
#define NV_PGRAPH_FECS_CHSW 0x409b0c
#define NV_PGRAPH_FECS_CHSW_ACK 0x00000001
#define NV_PGRAPH_FECS_INTR_UP_SET 0x409c1c #define NV_PGRAPH_FECS_INTR_UP_SET 0x409c1c
#define NV_PGRAPH_FECS_INTR_UP_EN 0x409c24
#define NV_PGRAPH_GPCX_GPCCS_INTR_ACK 0x41a004
#define NV_PGRAPH_GPCX_GPCCS_INTR 0x41a008
#define NV_PGRAPH_GPCX_GPCCS_INTR_FIFO 0x00000004
#define NV_PGRAPH_GPCX_GPCCS_INTR_EN_SET 0x41a010
#define NV_PGRAPH_GPCX_GPCCS_INTR_EN_SET_FIFO 0x00000004
#define NV_PGRAPH_GPCX_GPCCS_INTR_ROUTE 0x41a01c
#define NV_PGRAPH_GPCX_GPCCS_ACCESS 0x41a048
#define NV_PGRAPH_GPCX_GPCCS_ACCESS_FIFO 0x00000002
#define NV_PGRAPH_GPCX_GPCCS_FIFO_DATA 0x41a064
#define NV_PGRAPH_GPCX_GPCCS_FIFO_CMD 0x41a068
#define NV_PGRAPH_GPCX_GPCCS_FIFO_ACK 0x41a074
#define NV_PGRAPH_GPCX_GPCCS_UNITS 0x41a608
#define NV_PGRAPH_GPCX_GPCCS_RED_SWITCH 0x41a614
#define NV_PGRAPH_GPCX_GPCCS_RED_SWITCH_UNK11 0x00000800
#define NV_PGRAPH_GPCX_GPCCS_RED_SWITCH_ENABLE 0x00000200
#define NV_PGRAPH_GPCX_GPCCS_RED_SWITCH_POWER 0x00000020
#define NV_PGRAPH_GPCX_GPCCS_RED_SWITCH_PAUSE 0x00000002
#define NV_PGRAPH_GPCX_GPCCS_MYINDEX 0x41a618
#define NV_PGRAPH_GPCX_GPCCS_MMCTX_SAVE_SWBASE 0x41a700
#define NV_PGRAPH_GPCX_GPCCS_MMCTX_LOAD_SWBASE 0x41a704
#define NV_PGRAPH_GPCX_GPCCS_MMCTX_LOAD_COUNT 0x41a74c
#if CHIPSET < GK110 #if CHIPSET < GK110
#define NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_VAL(n) ((n) * 4 + 0x41a800) #define NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_VAL(n) ((n) * 4 + 0x41a800)
#define NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_SET(n) ((n) * 4 + 0x41a820) #define NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_SET(n) ((n) * 4 + 0x41a820)
#define NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_CLR(n) ((n) * 4 + 0x41a840) #define NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_CLR(n) ((n) * 4 + 0x41a840)
#define NV_PGRAPH_GPCX_GPCCS_UNK86C 0x41a86c
#else #else
#define NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_VAL(n) ((n) * 4 + 0x41a800) #define NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_VAL(n) ((n) * 4 + 0x41a800)
#define NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_CLR(n) ((n) * 4 + 0x41a840) #define NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_CLR(n) ((n) * 4 + 0x41a840)
#define NV_PGRAPH_GPCX_GPCCS_UNK86C 0x41a88c
#define NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_SET(n) ((n) * 4 + 0x41a8c0) #define NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_SET(n) ((n) * 4 + 0x41a8c0)
#endif #endif
#define NV_PGRAPH_GPCX_GPCCS_STRAND_SELECT 0x41a91c
#define NV_PGRAPH_GPCX_GPCCS_STRAND_CMD 0x41a928
#define NV_PGRAPH_GPCX_GPCCS_STRAND_CMD_SAVE 0x00000003
#define NV_PGRAPH_GPCX_GPCCS_STRAND_CMD_LOAD 0x00000004
#define NV_PGRAPH_GPCX_GPCCS_MEM_BASE 0x41aa04
#define mmctx_data(r,c) .b32 (((c - 1) << 26) | r) #define mmctx_data(r,c) .b32 (((c - 1) << 26) | r)
#define queue_init .skip 72 // (2 * 4) + ((8 * 4) * 2) #define queue_init .skip 72 // (2 * 4) + ((8 * 4) * 2)
@@ -65,24 +172,50 @@
#define T_LCHAN 8 #define T_LCHAN 8
#define T_LCTXH 9 #define T_LCTXH 9
#define nv_mkmm(rv,r) /* #if CHIPSET < GK208
*/ movw rv ((r) & 0x0000fffc) /* #define imm32(reg,val) /*
*/ sethi rv ((r) & 0x00ff0000) */ movw reg ((val) & 0x0000ffff) /*
*/ sethi reg ((val) & 0xffff0000)
#else
#define imm32(reg,val) /*
*/ mov reg (val)
#endif
#define nv_mkio(rv,r,i) /* #define nv_mkio(rv,r,i) /*
*/ nv_mkmm(rv, (((r) & 0xffc) << 6) | ((i) << 2)) */ imm32(rv, (((r) & 0xffc) << 6) | ((i) << 2))
#define hash #
#define fn(a) a
#if CHIPSET < GK208
#define call(a) call fn(hash)a
#else
#define call(a) lcall fn(hash)a
#endif
#define nv_iord(rv,r,i) /* #define nv_iord(rv,r,i) /*
*/ nv_mkio(rv,r,i) /* */ nv_mkio(rv,r,i) /*
*/ iord rv I[rv] */ iord rv I[rv]
#define nv_iowr(r,i,rv) /* #define nv_iowr(r,i,rv) /*
*/ nv_mkio($r0,r,i) /* */ nv_mkio($r0,r,i) /*
*/ iowr I[$r0] rv /* */ iowr I[$r0] rv /*
*/ clear b32 $r0 */ clear b32 $r0
#define nv_rd32(reg,addr) /*
*/ imm32($r14, addr) /*
*/ call(nv_rd32) /*
*/ mov b32 reg $r15
#define nv_wr32(addr,reg) /*
*/ mov b32 $r15 reg /*
*/ imm32($r14, addr) /*
*/ call(nv_wr32)
#define trace_set(bit) /* #define trace_set(bit) /*
*/ clear b32 $r9 /* */ clear b32 $r9 /*
*/ bset $r9 bit /* */ bset $r9 bit /*
*/ nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_SET(7), 0, $r9) */ nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_SET(7), 0, $r9)
#define trace_clr(bit) /* #define trace_clr(bit) /*
*/ clear b32 $r9 /* */ clear b32 $r9 /*
*/ bset $r9 bit /* */ bset $r9 bit /*

236
drivers/gpu/drm/nouveau/core/engine/graph/nv108.c Normal file
View File

@@ -0,0 +1,236 @@
/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
#include "nvc0.h"
/*******************************************************************************
* Graphics object classes
******************************************************************************/
static struct nouveau_oclass
nv108_graph_sclass[] = {
{ 0x902d, &nouveau_object_ofuncs },
{ 0xa140, &nouveau_object_ofuncs },
{ 0xa197, &nouveau_object_ofuncs },
{ 0xa1c0, &nouveau_object_ofuncs },
{}
};
/*******************************************************************************
* PGRAPH engine/subdev functions
******************************************************************************/
static struct nvc0_graph_init
nv108_graph_init_regs[] = {
{ 0x400080, 1, 0x04, 0x003083c2 },
{ 0x400088, 1, 0x04, 0x0001bfe7 },
{ 0x40008c, 1, 0x04, 0x00000000 },
{ 0x400090, 1, 0x04, 0x00000030 },
{ 0x40013c, 1, 0x04, 0x003901f7 },
{ 0x400140, 1, 0x04, 0x00000100 },
{ 0x400144, 1, 0x04, 0x00000000 },
{ 0x400148, 1, 0x04, 0x00000110 },
{ 0x400138, 1, 0x04, 0x00000000 },
{ 0x400130, 2, 0x04, 0x00000000 },
{ 0x400124, 1, 0x04, 0x00000002 },
{}
};
struct nvc0_graph_init
nv108_graph_init_unk58xx[] = {
{ 0x405844, 1, 0x04, 0x00ffffff },
{ 0x405850, 1, 0x04, 0x00000000 },
{ 0x405900, 1, 0x04, 0x00000000 },
{ 0x405908, 1, 0x04, 0x00000000 },
{ 0x405928, 1, 0x04, 0x00000000 },
{ 0x40592c, 1, 0x04, 0x00000000 },
{}
};
static struct nvc0_graph_init
nv108_graph_init_gpc[] = {
{ 0x418408, 1, 0x04, 0x00000000 },
{ 0x4184a0, 3, 0x04, 0x00000000 },
{ 0x418604, 1, 0x04, 0x00000000 },
{ 0x418680, 1, 0x04, 0x00000000 },
{ 0x418714, 1, 0x04, 0x00000000 },
{ 0x418384, 2, 0x04, 0x00000000 },
{ 0x418814, 3, 0x04, 0x00000000 },
{ 0x418b04, 1, 0x04, 0x00000000 },
{ 0x4188c8, 2, 0x04, 0x00000000 },
{ 0x4188d0, 1, 0x04, 0x00010000 },
{ 0x4188d4, 1, 0x04, 0x00000201 },
{ 0x418910, 1, 0x04, 0x00010001 },
{ 0x418914, 1, 0x04, 0x00000301 },
{ 0x418918, 1, 0x04, 0x00800000 },
{ 0x418980, 1, 0x04, 0x77777770 },
{ 0x418984, 3, 0x04, 0x77777777 },
{ 0x418c04, 1, 0x04, 0x00000000 },
{ 0x418c64, 2, 0x04, 0x00000000 },
{ 0x418c88, 1, 0x04, 0x00000000 },
{ 0x418cb4, 2, 0x04, 0x00000000 },
{ 0x418d00, 1, 0x04, 0x00000000 },
{ 0x418d28, 2, 0x04, 0x00000000 },
{ 0x418f00, 1, 0x04, 0x00000400 },
{ 0x418f08, 1, 0x04, 0x00000000 },
{ 0x418f20, 2, 0x04, 0x00000000 },
{ 0x418e00, 1, 0x04, 0x00000000 },
{ 0x418e08, 1, 0x04, 0x00000000 },
{ 0x418e1c, 2, 0x04, 0x00000000 },
{ 0x41900c, 1, 0x04, 0x00000000 },
{ 0x419018, 1, 0x04, 0x00000000 },
{}
};
static struct nvc0_graph_init
nv108_graph_init_tpc[] = {
{ 0x419d0c, 1, 0x04, 0x00000000 },
{ 0x419d10, 1, 0x04, 0x00000014 },
{ 0x419ab0, 1, 0x04, 0x00000000 },
{ 0x419ac8, 1, 0x04, 0x00000000 },
{ 0x419ab8, 1, 0x04, 0x000000e7 },
{ 0x419abc, 2, 0x04, 0x00000000 },
{ 0x419ab4, 1, 0x04, 0x00000000 },
{ 0x419aa8, 2, 0x04, 0x00000000 },
{ 0x41980c, 1, 0x04, 0x00000010 },
{ 0x419844, 1, 0x04, 0x00000000 },
{ 0x419850, 1, 0x04, 0x00000004 },
{ 0x419854, 2, 0x04, 0x00000000 },
{ 0x419c98, 1, 0x04, 0x00000000 },
{ 0x419ca8, 1, 0x04, 0x00000000 },
{ 0x419cb0, 1, 0x04, 0x01000000 },
{ 0x419cb4, 1, 0x04, 0x00000000 },
{ 0x419cb8, 1, 0x04, 0x00b08bea },
{ 0x419c84, 1, 0x04, 0x00010384 },
{ 0x419cbc, 1, 0x04, 0x281b3646 },
{ 0x419cc0, 2, 0x04, 0x00000000 },
{ 0x419c80, 1, 0x04, 0x00000230 },
{ 0x419ccc, 2, 0x04, 0x00000000 },
{ 0x419c0c, 1, 0x04, 0x00000000 },
{ 0x419e00, 1, 0x04, 0x00000080 },
{ 0x419ea0, 1, 0x04, 0x00000000 },
{ 0x419ee4, 1, 0x04, 0x00000000 },
{ 0x419ea4, 1, 0x04, 0x00000100 },
{ 0x419ea8, 1, 0x04, 0x00000000 },
{ 0x419eb4, 1, 0x04, 0x00000000 },
{ 0x419ebc, 2, 0x04, 0x00000000 },
{ 0x419edc, 1, 0x04, 0x00000000 },
{ 0x419f00, 1, 0x04, 0x00000000 },
{ 0x419ed0, 1, 0x04, 0x00003234 },
{ 0x419f74, 1, 0x04, 0x00015555 },
{ 0x419f80, 4, 0x04, 0x00000000 },
{}
};
static int
nv108_graph_fini(struct nouveau_object *object, bool suspend)
{
struct nvc0_graph_priv *priv = (void *)object;
static const struct {
u32 addr;
u32 data;
} magic[] = {
{ 0x020520, 0xfffffffc },
{ 0x020524, 0xfffffffe },
{ 0x020524, 0xfffffffc },
{ 0x020524, 0xfffffff8 },
{ 0x020524, 0xffffffe0 },
{ 0x020530, 0xfffffffe },
{ 0x02052c, 0xfffffffa },
{ 0x02052c, 0xfffffff0 },
{ 0x02052c, 0xffffffc0 },
{ 0x02052c, 0xffffff00 },
{ 0x02052c, 0xfffffc00 },
{ 0x02052c, 0xfffcfc00 },
{ 0x02052c, 0xfff0fc00 },
{ 0x02052c, 0xff80fc00 },
{ 0x020528, 0xfffffffe },
{ 0x020528, 0xfffffffc },
};
int i;
nv_mask(priv, 0x000200, 0x08001000, 0x00000000);
nv_mask(priv, 0x0206b4, 0x00000000, 0x00000000);
for (i = 0; i < ARRAY_SIZE(magic); i++) {
nv_wr32(priv, magic[i].addr, magic[i].data);
nv_wait(priv, magic[i].addr, 0x80000000, 0x00000000);
}
return nouveau_graph_fini(&priv->base, suspend);
}
static struct nvc0_graph_init *
nv108_graph_init_mmio[] = {
nv108_graph_init_regs,
nvf0_graph_init_unk40xx,
nvc0_graph_init_unk44xx,
nvc0_graph_init_unk78xx,
nvc0_graph_init_unk60xx,
nvd9_graph_init_unk64xx,
nv108_graph_init_unk58xx,
nvc0_graph_init_unk80xx,
nvf0_graph_init_unk70xx,
nvf0_graph_init_unk5bxx,
nv108_graph_init_gpc,
nv108_graph_init_tpc,
nve4_graph_init_unk,
nve4_graph_init_unk88xx,
NULL
};
#include "fuc/hubnv108.fuc5.h"
static struct nvc0_graph_ucode
nv108_graph_fecs_ucode = {
.code.data = nv108_grhub_code,
.code.size = sizeof(nv108_grhub_code),
.data.data = nv108_grhub_data,
.data.size = sizeof(nv108_grhub_data),
};
#include "fuc/gpcnv108.fuc5.h"
static struct nvc0_graph_ucode
nv108_graph_gpccs_ucode = {
.code.data = nv108_grgpc_code,
.code.size = sizeof(nv108_grgpc_code),
.data.data = nv108_grgpc_data,
.data.size = sizeof(nv108_grgpc_data),
};
struct nouveau_oclass *
nv108_graph_oclass = &(struct nvc0_graph_oclass) {
.base.handle = NV_ENGINE(GR, 0x08),
.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nvc0_graph_ctor,
.dtor = nvc0_graph_dtor,
.init = nve4_graph_init,
.fini = nv108_graph_fini,
},
.cclass = &nv108_grctx_oclass,
.sclass = nv108_graph_sclass,
.mmio = nv108_graph_init_mmio,
.fecs.ucode = &nv108_graph_fecs_ucode,
.gpccs.ucode = &nv108_graph_gpccs_ucode,
}.base;

166
drivers/gpu/drm/nouveau/core/engine/graph/nv50.c
View File

@@ -304,12 +304,28 @@ nv84_graph_tlb_flush(struct nouveau_engine *engine)
return timeout ? -EBUSY : 0; return timeout ? -EBUSY : 0;
} }
static const struct nouveau_enum nv50_mp_exec_error_names[] = { static const struct nouveau_bitfield nv50_mp_exec_errors[] = {
{ 3, "STACK_UNDERFLOW", NULL }, { 0x01, "STACK_UNDERFLOW" },
{ 4, "QUADON_ACTIVE", NULL }, { 0x02, "STACK_MISMATCH" },
{ 8, "TIMEOUT", NULL }, { 0x04, "QUADON_ACTIVE" },
{ 0x10, "INVALID_OPCODE", NULL }, { 0x08, "TIMEOUT" },
{ 0x40, "BREAKPOINT", NULL }, { 0x10, "INVALID_OPCODE" },
{ 0x20, "PM_OVERFLOW" },
{ 0x40, "BREAKPOINT" },
{}
};
static const struct nouveau_bitfield nv50_mpc_traps[] = {
{ 0x0000001, "LOCAL_LIMIT_READ" },
{ 0x0000010, "LOCAL_LIMIT_WRITE" },
{ 0x0000040, "STACK_LIMIT" },
{ 0x0000100, "GLOBAL_LIMIT_READ" },
{ 0x0001000, "GLOBAL_LIMIT_WRITE" },
{ 0x0010000, "MP0" },
{ 0x0020000, "MP1" },
{ 0x0040000, "GLOBAL_LIMIT_RED" },
{ 0x0400000, "GLOBAL_LIMIT_ATOM" },
{ 0x4000000, "MP2" },
{} {}
}; };
@@ -396,6 +412,60 @@ static const struct nouveau_bitfield nv50_graph_intr_name[] = {
{} {}
}; };
static const struct nouveau_bitfield nv50_graph_trap_prop[] = {
{ 0x00000004, "SURF_WIDTH_OVERRUN" },
{ 0x00000008, "SURF_HEIGHT_OVERRUN" },
{ 0x00000010, "DST2D_FAULT" },
{ 0x00000020, "ZETA_FAULT" },
{ 0x00000040, "RT_FAULT" },
{ 0x00000080, "CUDA_FAULT" },
{ 0x00000100, "DST2D_STORAGE_TYPE_MISMATCH" },
{ 0x00000200, "ZETA_STORAGE_TYPE_MISMATCH" },
{ 0x00000400, "RT_STORAGE_TYPE_MISMATCH" },
{ 0x00000800, "DST2D_LINEAR_MISMATCH" },
{ 0x00001000, "RT_LINEAR_MISMATCH" },
{}
};
static void
nv50_priv_prop_trap(struct nv50_graph_priv *priv,
u32 ustatus_addr, u32 ustatus, u32 tp)
{
u32 e0c = nv_rd32(priv, ustatus_addr + 0x04);
u32 e10 = nv_rd32(priv, ustatus_addr + 0x08);
u32 e14 = nv_rd32(priv, ustatus_addr + 0x0c);
u32 e18 = nv_rd32(priv, ustatus_addr + 0x10);
u32 e1c = nv_rd32(priv, ustatus_addr + 0x14);
u32 e20 = nv_rd32(priv, ustatus_addr + 0x18);
u32 e24 = nv_rd32(priv, ustatus_addr + 0x1c);
/* CUDA memory: l[], g[] or stack. */
if (ustatus & 0x00000080) {
if (e18 & 0x80000000) {
/* g[] read fault? */
nv_error(priv, "TRAP_PROP - TP %d - CUDA_FAULT - Global read fault at address %02x%08x\n",
tp, e14, e10 | ((e18 >> 24) & 0x1f));
e18 &= ~0x1f000000;
} else if (e18 & 0xc) {
/* g[] write fault? */
nv_error(priv, "TRAP_PROP - TP %d - CUDA_FAULT - Global write fault at address %02x%08x\n",
tp, e14, e10 | ((e18 >> 7) & 0x1f));
e18 &= ~0x00000f80;
} else {
nv_error(priv, "TRAP_PROP - TP %d - Unknown CUDA fault at address %02x%08x\n",
tp, e14, e10);
}
ustatus &= ~0x00000080;
}
if (ustatus) {
nv_error(priv, "TRAP_PROP - TP %d -", tp);
nouveau_bitfield_print(nv50_graph_trap_prop, ustatus);
pr_cont(" - Address %02x%08x\n", e14, e10);
}
nv_error(priv, "TRAP_PROP - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
tp, e0c, e18, e1c, e20, e24);
}
static void static void
nv50_priv_mp_trap(struct nv50_graph_priv *priv, int tpid, int display) nv50_priv_mp_trap(struct nv50_graph_priv *priv, int tpid, int display)
{ {
@@ -420,8 +490,8 @@ nv50_priv_mp_trap(struct nv50_graph_priv *priv, int tpid, int display)
oplow = nv_rd32(priv, addr + 0x70); oplow = nv_rd32(priv, addr + 0x70);
ophigh = nv_rd32(priv, addr + 0x74); ophigh = nv_rd32(priv, addr + 0x74);
nv_error(priv, "TRAP_MP_EXEC - " nv_error(priv, "TRAP_MP_EXEC - "
"TP %d MP %d: ", tpid, i); "TP %d MP %d:", tpid, i);
nouveau_enum_print(nv50_mp_exec_error_names, status); nouveau_bitfield_print(nv50_mp_exec_errors, status);
pr_cont(" at %06x warp %d, opcode %08x %08x\n", pr_cont(" at %06x warp %d, opcode %08x %08x\n",
pc&0xffffff, pc >> 24, pc&0xffffff, pc >> 24,
oplow, ophigh); oplow, ophigh);
@@ -468,59 +538,18 @@ nv50_priv_tp_trap(struct nv50_graph_priv *priv, int type, u32 ustatus_old,
nv50_priv_mp_trap(priv, i, display); nv50_priv_mp_trap(priv, i, display);
ustatus &= ~0x04030000; ustatus &= ~0x04030000;
} }
if (ustatus && display) {
nv_error("%s - TP%d:", name, i);
nouveau_bitfield_print(nv50_mpc_traps, ustatus);
pr_cont("\n");
ustatus = 0;
}
break; break;
case 8: /* TPDMA error */ case 8: /* PROP error */
{ if (display)
u32 e0c = nv_rd32(priv, ustatus_addr + 4); nv50_priv_prop_trap(
u32 e10 = nv_rd32(priv, ustatus_addr + 8); priv, ustatus_addr, ustatus, i);
u32 e14 = nv_rd32(priv, ustatus_addr + 0xc); ustatus = 0;
u32 e18 = nv_rd32(priv, ustatus_addr + 0x10);
u32 e1c = nv_rd32(priv, ustatus_addr + 0x14);
u32 e20 = nv_rd32(priv, ustatus_addr + 0x18);
u32 e24 = nv_rd32(priv, ustatus_addr + 0x1c);
/* 2d engine destination */
if (ustatus & 0x00000010) {
if (display) {
nv_error(priv, "TRAP_TPDMA_2D - TP %d - Unknown fault at address %02x%08x\n",
i, e14, e10);
nv_error(priv, "TRAP_TPDMA_2D - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
i, e0c, e18, e1c, e20, e24);
}
ustatus &= ~0x00000010;
}
/* Render target */
if (ustatus & 0x00000040) {
if (display) {
nv_error(priv, "TRAP_TPDMA_RT - TP %d - Unknown fault at address %02x%08x\n",
i, e14, e10);
nv_error(priv, "TRAP_TPDMA_RT - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
i, e0c, e18, e1c, e20, e24);
}
ustatus &= ~0x00000040;
}
/* CUDA memory: l[], g[] or stack. */
if (ustatus & 0x00000080) {
if (display) {
if (e18 & 0x80000000) {
/* g[] read fault? */
nv_error(priv, "TRAP_TPDMA - TP %d - Global read fault at address %02x%08x\n",
i, e14, e10 | ((e18 >> 24) & 0x1f));
e18 &= ~0x1f000000;
} else if (e18 & 0xc) {
/* g[] write fault? */
nv_error(priv, "TRAP_TPDMA - TP %d - Global write fault at address %02x%08x\n",
i, e14, e10 | ((e18 >> 7) & 0x1f));
e18 &= ~0x00000f80;
} else {
nv_error(priv, "TRAP_TPDMA - TP %d - Unknown CUDA fault at address %02x%08x\n",
i, e14, e10);
}
nv_error(priv, "TRAP_TPDMA - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
i, e0c, e18, e1c, e20, e24);
}
ustatus &= ~0x00000080;
}
}
break; break;
} }
if (ustatus) { if (ustatus) {
@@ -727,11 +756,11 @@ nv50_graph_trap_handler(struct nv50_graph_priv *priv, u32 display,
status &= ~0x080; status &= ~0x080;
} }
/* TPDMA: Handles TP-initiated uncached memory accesses: /* PROP: Handles TP-initiated uncached memory accesses:
* l[], g[], stack, 2d surfaces, render targets. */ * l[], g[], stack, 2d surfaces, render targets. */
if (status & 0x100) { if (status & 0x100) {
nv50_priv_tp_trap(priv, 8, 0x408e08, 0x408708, display, nv50_priv_tp_trap(priv, 8, 0x408e08, 0x408708, display,
"TRAP_TPDMA"); "TRAP_PROP");
nv_wr32(priv, 0x400108, 0x100); nv_wr32(priv, 0x400108, 0x100);
status &= ~0x100; status &= ~0x100;
} }
@@ -760,7 +789,7 @@ nv50_graph_intr(struct nouveau_subdev *subdev)
u32 mthd = (addr & 0x00001ffc); u32 mthd = (addr & 0x00001ffc);
u32 data = nv_rd32(priv, 0x400708); u32 data = nv_rd32(priv, 0x400708);
u32 class = nv_rd32(priv, 0x400814); u32 class = nv_rd32(priv, 0x400814);
u32 show = stat; u32 show = stat, show_bitfield = stat;
int chid; int chid;
engctx = nouveau_engctx_get(engine, inst); engctx = nouveau_engctx_get(engine, inst);
@@ -778,21 +807,26 @@ nv50_graph_intr(struct nouveau_subdev *subdev)
nv_error(priv, "DATA_ERROR "); nv_error(priv, "DATA_ERROR ");
nouveau_enum_print(nv50_data_error_names, ecode); nouveau_enum_print(nv50_data_error_names, ecode);
pr_cont("\n"); pr_cont("\n");
show_bitfield &= ~0x00100000;
} }
if (stat & 0x00200000) { if (stat & 0x00200000) {
if (!nv50_graph_trap_handler(priv, show, chid, (u64)inst << 12, if (!nv50_graph_trap_handler(priv, show, chid, (u64)inst << 12,
engctx)) engctx))
show &= ~0x00200000; show &= ~0x00200000;
show_bitfield &= ~0x00200000;
} }
nv_wr32(priv, 0x400100, stat); nv_wr32(priv, 0x400100, stat);
nv_wr32(priv, 0x400500, 0x00010001); nv_wr32(priv, 0x400500, 0x00010001);
if (show) { if (show) {
nv_error(priv, "%s", ""); show &= show_bitfield;
nouveau_bitfield_print(nv50_graph_intr_name, show); if (show) {
pr_cont("\n"); nv_error(priv, "%s", "");
nouveau_bitfield_print(nv50_graph_intr_name, show);
pr_cont("\n");
}
nv_error(priv, nv_error(priv,
"ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n", "ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
chid, (u64)inst << 12, nouveau_client_name(engctx), chid, (u64)inst << 12, nouveau_client_name(engctx),

3
drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c
View File

@@ -901,6 +901,9 @@ nvc0_graph_init_ctxctl(struct nvc0_graph_priv *priv)
} }
return 0; return 0;
} else
if (!oclass->fecs.ucode) {
return -ENOSYS;
} }
/* load HUB microcode */ /* load HUB microcode */

10
drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h
View File

@@ -205,6 +205,11 @@ extern struct nvc0_graph_init nve4_graph_init_regs[];
extern struct nvc0_graph_init nve4_graph_init_unk[]; extern struct nvc0_graph_init nve4_graph_init_unk[];
extern struct nvc0_graph_init nve4_graph_init_unk88xx[]; extern struct nvc0_graph_init nve4_graph_init_unk88xx[];
extern struct nvc0_graph_init nvf0_graph_init_unk40xx[];
extern struct nvc0_graph_init nvf0_graph_init_unk70xx[];
extern struct nvc0_graph_init nvf0_graph_init_unk5bxx[];
extern struct nvc0_graph_init nvf0_graph_init_tpc[];
int nvc0_grctx_generate(struct nvc0_graph_priv *); int nvc0_grctx_generate(struct nvc0_graph_priv *);
void nvc0_grctx_generate_main(struct nvc0_graph_priv *, struct nvc0_grctx *); void nvc0_grctx_generate_main(struct nvc0_graph_priv *, struct nvc0_grctx *);
void nvc0_grctx_generate_mods(struct nvc0_graph_priv *, struct nvc0_grctx *); void nvc0_grctx_generate_mods(struct nvc0_graph_priv *, struct nvc0_grctx *);
@@ -266,6 +271,11 @@ extern struct nvc0_graph_init nve4_grctx_init_unk80xx[];
extern struct nvc0_graph_init nve4_grctx_init_unk90xx[]; extern struct nvc0_graph_init nve4_grctx_init_unk90xx[];
extern struct nouveau_oclass *nvf0_grctx_oclass; extern struct nouveau_oclass *nvf0_grctx_oclass;
extern struct nvc0_graph_init nvf0_grctx_init_unk44xx[];
extern struct nvc0_graph_init nvf0_grctx_init_unk5bxx[];
extern struct nvc0_graph_init nvf0_grctx_init_unk60xx[];
extern struct nouveau_oclass *nv108_grctx_oclass;
#define mmio_data(s,a,p) do { \ #define mmio_data(s,a,p) do { \
info->buffer[info->buffer_nr] = round_up(info->addr, (a)); \ info->buffer[info->buffer_nr] = round_up(info->addr, (a)); \

10
drivers/gpu/drm/nouveau/core/engine/graph/nvf0.c
View File

@@ -41,7 +41,7 @@ nvf0_graph_sclass[] = {
* PGRAPH engine/subdev functions * PGRAPH engine/subdev functions
******************************************************************************/ ******************************************************************************/
static struct nvc0_graph_init struct nvc0_graph_init
nvf0_graph_init_unk40xx[] = { nvf0_graph_init_unk40xx[] = {
{ 0x40415c, 1, 0x04, 0x00000000 }, { 0x40415c, 1, 0x04, 0x00000000 },
{ 0x404170, 1, 0x04, 0x00000000 }, { 0x404170, 1, 0x04, 0x00000000 },
@@ -60,7 +60,7 @@ nvf0_graph_init_unk58xx[] = {
{} {}
}; };
static struct nvc0_graph_init struct nvc0_graph_init
nvf0_graph_init_unk70xx[] = { nvf0_graph_init_unk70xx[] = {
{ 0x407010, 1, 0x04, 0x00000000 }, { 0x407010, 1, 0x04, 0x00000000 },
{ 0x407040, 1, 0x04, 0x80440424 }, { 0x407040, 1, 0x04, 0x80440424 },
@@ -68,7 +68,7 @@ nvf0_graph_init_unk70xx[] = {
{} {}
}; };
static struct nvc0_graph_init struct nvc0_graph_init
nvf0_graph_init_unk5bxx[] = { nvf0_graph_init_unk5bxx[] = {
{ 0x405b44, 1, 0x04, 0x00000000 }, { 0x405b44, 1, 0x04, 0x00000000 },
{ 0x405b50, 1, 0x04, 0x00000000 }, { 0x405b50, 1, 0x04, 0x00000000 },
@@ -114,7 +114,7 @@ nvf0_graph_init_gpc[] = {
{} {}
}; };
static struct nvc0_graph_init struct nvc0_graph_init
nvf0_graph_init_tpc[] = { nvf0_graph_init_tpc[] = {
{ 0x419d0c, 1, 0x04, 0x00000000 }, { 0x419d0c, 1, 0x04, 0x00000000 },
{ 0x419d10, 1, 0x04, 0x00000014 }, { 0x419d10, 1, 0x04, 0x00000014 },
@@ -243,6 +243,6 @@ nvf0_graph_oclass = &(struct nvc0_graph_oclass) {
.cclass = &nvf0_grctx_oclass, .cclass = &nvf0_grctx_oclass,
.sclass = nvf0_graph_sclass, .sclass = nvf0_graph_sclass,
.mmio = nvf0_graph_init_mmio, .mmio = nvf0_graph_init_mmio,
.fecs.ucode = 0 ? &nvf0_graph_fecs_ucode : NULL, .fecs.ucode = &nvf0_graph_fecs_ucode,
.gpccs.ucode = &nvf0_graph_gpccs_ucode, .gpccs.ucode = &nvf0_graph_gpccs_ucode,
}.base; }.base;

22
drivers/gpu/drm/nouveau/core/include/core/class.h
View File

@@ -230,9 +230,26 @@ struct nve0_channel_ind_class {
#define NV04_DISP_CLASS 0x00000046 #define NV04_DISP_CLASS 0x00000046
#define NV04_DISP_MTHD 0x00000000
#define NV04_DISP_MTHD_HEAD 0x00000001
#define NV04_DISP_SCANOUTPOS 0x00000000
struct nv04_display_class { struct nv04_display_class {
}; };
struct nv04_display_scanoutpos {
s64 time[2];
u32 vblanks;
u32 vblanke;
u32 vtotal;
u32 vline;
u32 hblanks;
u32 hblanke;
u32 htotal;
u32 hline;
};
/* 5070: NV50_DISP /* 5070: NV50_DISP
* 8270: NV84_DISP * 8270: NV84_DISP
* 8370: NVA0_DISP * 8370: NVA0_DISP
@@ -252,6 +269,11 @@ struct nv04_display_class {
#define NVE0_DISP_CLASS 0x00009170 #define NVE0_DISP_CLASS 0x00009170
#define NVF0_DISP_CLASS 0x00009270 #define NVF0_DISP_CLASS 0x00009270
#define NV50_DISP_MTHD 0x00000000
#define NV50_DISP_MTHD_HEAD 0x00000003
#define NV50_DISP_SCANOUTPOS 0x00000000
#define NV50_DISP_SOR_MTHD 0x00010000 #define NV50_DISP_SOR_MTHD 0x00010000
#define NV50_DISP_SOR_MTHD_TYPE 0x0000f000 #define NV50_DISP_SOR_MTHD_TYPE 0x0000f000
#define NV50_DISP_SOR_MTHD_HEAD 0x00000018 #define NV50_DISP_SOR_MTHD_HEAD 0x00000018

4
drivers/gpu/drm/nouveau/core/include/core/device.h
View File

@@ -38,7 +38,8 @@ enum nv_subdev_type {
NVDEV_SUBDEV_THERM, NVDEV_SUBDEV_THERM,
NVDEV_SUBDEV_CLOCK, NVDEV_SUBDEV_CLOCK,
NVDEV_ENGINE_DMAOBJ, NVDEV_ENGINE_FIRST,
NVDEV_ENGINE_DMAOBJ = NVDEV_ENGINE_FIRST,
NVDEV_ENGINE_FIFO, NVDEV_ENGINE_FIFO,
NVDEV_ENGINE_SW, NVDEV_ENGINE_SW,
NVDEV_ENGINE_GR, NVDEV_ENGINE_GR,
@@ -70,6 +71,7 @@ struct nouveau_device {
const char *dbgopt; const char *dbgopt;
const char *name; const char *name;
const char *cname; const char *cname;
u64 disable_mask;
enum { enum {
NV_04 = 0x04, NV_04 = 0x04,

1
drivers/gpu/drm/nouveau/core/include/engine/fifo.h
View File

@@ -109,6 +109,7 @@ extern struct nouveau_oclass *nv50_fifo_oclass;
extern struct nouveau_oclass *nv84_fifo_oclass; extern struct nouveau_oclass *nv84_fifo_oclass;
extern struct nouveau_oclass *nvc0_fifo_oclass; extern struct nouveau_oclass *nvc0_fifo_oclass;
extern struct nouveau_oclass *nve0_fifo_oclass; extern struct nouveau_oclass *nve0_fifo_oclass;
extern struct nouveau_oclass *nv108_fifo_oclass;
void nv04_fifo_intr(struct nouveau_subdev *); void nv04_fifo_intr(struct nouveau_subdev *);
int nv04_fifo_context_attach(struct nouveau_object *, struct nouveau_object *); int nv04_fifo_context_attach(struct nouveau_object *, struct nouveau_object *);

1
drivers/gpu/drm/nouveau/core/include/engine/graph.h
View File

@@ -69,6 +69,7 @@ extern struct nouveau_oclass *nvd7_graph_oclass;
extern struct nouveau_oclass *nvd9_graph_oclass; extern struct nouveau_oclass *nvd9_graph_oclass;
extern struct nouveau_oclass *nve4_graph_oclass; extern struct nouveau_oclass *nve4_graph_oclass;
extern struct nouveau_oclass *nvf0_graph_oclass; extern struct nouveau_oclass *nvf0_graph_oclass;
extern struct nouveau_oclass *nv108_graph_oclass;
extern const struct nouveau_bitfield nv04_graph_nsource[]; extern const struct nouveau_bitfield nv04_graph_nsource[];
extern struct nouveau_ofuncs nv04_graph_ofuncs; extern struct nouveau_ofuncs nv04_graph_ofuncs;

23
drivers/gpu/drm/nouveau/core/include/subdev/bar.h
View File

@@ -4,8 +4,7 @@
#include <core/subdev.h> #include <core/subdev.h>
#include <core/device.h> #include <core/device.h>
#include <subdev/fb.h> struct nouveau_mem;
struct nouveau_vma; struct nouveau_vma;
struct nouveau_bar { struct nouveau_bar {
@@ -29,27 +28,7 @@ nouveau_bar(void *obj)
return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_BAR]; return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_BAR];
} }
#define nouveau_bar_create(p,e,o,d) \
nouveau_bar_create_((p), (e), (o), sizeof(**d), (void **)d)
#define nouveau_bar_init(p) \
nouveau_subdev_init(&(p)->base)
#define nouveau_bar_fini(p,s) \
nouveau_subdev_fini(&(p)->base, (s))
int nouveau_bar_create_(struct nouveau_object *, struct nouveau_object *,
struct nouveau_oclass *, int, void **);
void nouveau_bar_destroy(struct nouveau_bar *);
void _nouveau_bar_dtor(struct nouveau_object *);
#define _nouveau_bar_init _nouveau_subdev_init
#define _nouveau_bar_fini _nouveau_subdev_fini
extern struct nouveau_oclass nv50_bar_oclass; extern struct nouveau_oclass nv50_bar_oclass;
extern struct nouveau_oclass nvc0_bar_oclass; extern struct nouveau_oclass nvc0_bar_oclass;
int nouveau_bar_alloc(struct nouveau_bar *, struct nouveau_object *,
struct nouveau_mem *, struct nouveau_object **);
void nv84_bar_flush(struct nouveau_bar *);
#endif #endif

66
drivers/gpu/drm/nouveau/core/include/subdev/bios/ramcfg.h Normal file
View File

@@ -0,0 +1,66 @@
#ifndef __NVBIOS_RAMCFG_H__
#define __NVBIOS_RAMCFG_H__
struct nouveau_bios;
struct nvbios_ramcfg {
unsigned rammap_11_08_01:1;
unsigned rammap_11_08_0c:2;
unsigned rammap_11_08_10:1;
unsigned rammap_11_11_0c:2;
unsigned ramcfg_11_01_01:1;
unsigned ramcfg_11_01_02:1;
unsigned ramcfg_11_01_04:1;
unsigned ramcfg_11_01_08:1;
unsigned ramcfg_11_01_10:1;
unsigned ramcfg_11_01_20:1;
unsigned ramcfg_11_01_40:1;
unsigned ramcfg_11_01_80:1;
unsigned ramcfg_11_02_03:2;
unsigned ramcfg_11_02_04:1;
unsigned ramcfg_11_02_08:1;
unsigned ramcfg_11_02_10:1;
unsigned ramcfg_11_02_40:1;
unsigned ramcfg_11_02_80:1;
unsigned ramcfg_11_03_0f:4;
unsigned ramcfg_11_03_30:2;
unsigned ramcfg_11_03_c0:2;
unsigned ramcfg_11_03_f0:4;
unsigned ramcfg_11_04:8;
unsigned ramcfg_11_06:8;
unsigned ramcfg_11_07_02:1;
unsigned ramcfg_11_07_04:1;
unsigned ramcfg_11_07_08:1;
unsigned ramcfg_11_07_10:1;
unsigned ramcfg_11_07_40:1;
unsigned ramcfg_11_07_80:1;
unsigned ramcfg_11_08_01:1;
unsigned ramcfg_11_08_02:1;
unsigned ramcfg_11_08_04:1;
unsigned ramcfg_11_08_08:1;
unsigned ramcfg_11_08_10:1;
unsigned ramcfg_11_08_20:1;
unsigned ramcfg_11_09:8;
unsigned timing[11];
unsigned timing_20_2e_03:2;
unsigned timing_20_2e_30:2;
unsigned timing_20_2e_c0:2;
unsigned timing_20_2f_03:2;
unsigned timing_20_2c_003f:6;
unsigned timing_20_2c_1fc0:7;
unsigned timing_20_30_f8:5;
unsigned timing_20_30_07:3;
unsigned timing_20_31_0007:3;
unsigned timing_20_31_0078:4;
unsigned timing_20_31_0780:4;
unsigned timing_20_31_0800:1;
unsigned timing_20_31_7000:3;
unsigned timing_20_31_8000:1;
};
u8 nvbios_ramcfg_count(struct nouveau_bios *);
u8 nvbios_ramcfg_index(struct nouveau_bios *);
#endif

26
drivers/gpu/drm/nouveau/core/include/subdev/bios/rammap.h
View File

@@ -1,11 +1,25 @@
#ifndef __NVBIOS_RAMMAP_H__ #ifndef __NVBIOS_RAMMAP_H__
#define __NVBIOS_RAMMAP_H__ #define __NVBIOS_RAMMAP_H__
u16 nvbios_rammap_table(struct nouveau_bios *, u8 *ver, u8 *hdr, struct nvbios_ramcfg;
u8 *cnt, u8 *len, u8 *snr, u8 *ssz);
u16 nvbios_rammap_entry(struct nouveau_bios *, int idx, u32 nvbios_rammapTe(struct nouveau_bios *, u8 *ver, u8 *hdr,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len); u8 *cnt, u8 *len, u8 *snr, u8 *ssz);
u16 nvbios_rammap_match(struct nouveau_bios *, u16 khz,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len); u32 nvbios_rammapEe(struct nouveau_bios *, int idx,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len);
u32 nvbios_rammapEm(struct nouveau_bios *, u16 mhz,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len);
u32 nvbios_rammapEp(struct nouveau_bios *, u16 mhz,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
struct nvbios_ramcfg *);
u32 nvbios_rammapSe(struct nouveau_bios *, u32 data,
u8 ever, u8 ehdr, u8 ecnt, u8 elen, int idx,
u8 *ver, u8 *hdr);
u32 nvbios_rammapSp(struct nouveau_bios *, u32 data,
u8 ever, u8 ehdr, u8 ecnt, u8 elen, int idx,
u8 *ver, u8 *hdr,
struct nvbios_ramcfg *);
#endif #endif

12
drivers/gpu/drm/nouveau/core/include/subdev/bios/timing.h
View File

@@ -1,8 +1,14 @@
#ifndef __NVBIOS_TIMING_H__ #ifndef __NVBIOS_TIMING_H__
#define __NVBIOS_TIMING_H__ #define __NVBIOS_TIMING_H__
u16 nvbios_timing_table(struct nouveau_bios *, struct nvbios_ramcfg;
u8 *ver, u8 *hdr, u8 *cnt, u8 *len);
u16 nvbios_timing_entry(struct nouveau_bios *, int idx, u8 *ver, u8 *hdr); u16 nvbios_timingTe(struct nouveau_bios *,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *snr, u8 *ssz);
u16 nvbios_timingEe(struct nouveau_bios *, int idx,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len);
u16 nvbios_timingEp(struct nouveau_bios *, int idx,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
struct nvbios_ramcfg *);
#endif #endif

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