scsi: hisi_sas: Ignore the error code between phy down to phy up
Several error codes will be generated between PHY down to up. This issue was introduced by HW design. The designers came to the conclusion that we should ignore these errors. Signed-off-by: Jiaxing Luo <luojiaxing@huawei.com> Signed-off-by: John Garry <john.garry@huawei.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
这个提交包含在:
@@ -911,8 +911,14 @@ static void enable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
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static void disable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
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{
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u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
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u32 irq_msk = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2_MSK);
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static const u32 msk = BIT(CHL_INT2_RX_DISP_ERR_OFF) |
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BIT(CHL_INT2_RX_CODE_ERR_OFF) |
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BIT(CHL_INT2_RX_INVLD_DW_OFF);
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u32 state;
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hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2_MSK, msk | irq_msk);
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cfg &= ~PHY_CFG_ENA_MSK;
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hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
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@@ -923,6 +929,15 @@ static void disable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
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cfg |= PHY_CFG_PHY_RST_MSK;
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hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
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}
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udelay(1);
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hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_INVLD_DW);
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hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DISP_ERR);
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hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_CODE_ERR);
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hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2, msk);
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hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2_MSK, irq_msk);
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}
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static void start_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
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