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UPSTREAM: usb: dwc3: core: Revise GHWPARAMS9 offset

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During our predesign phase for DWC_usb32, the GHWPARAMS9 register offset
was 0xc680. We revised our final design, and the GHWPARAMS9 offset is
now moved to 0xc6e8 on release.

Fixes: 16710380d3aa ("usb: dwc3: Capture new capability register GHWPARAMS9")
Cc: <stable@vger.kernel.org>
Signed-off-by: Thinh Nguyen <Thinh.Nguyen@synopsys.com>
Link: https://lore.kernel.org/r/1541737108266a97208ff827805be1f32852590c.1635202893.git.Thinh.Nguyen@synopsys.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
(cherry picked from commit 250fdabec6ffcaf895c5e0dedca62706ef10d8f6)
Bug: 187129171
Signed-off-by: Connor O'Brien <connoro@google.com>
Change-Id: Id22d3406f5e01d5dc7240ed43287004d768a6cf0
This commit is contained in:
Thinh Nguyen
2021-10-25 16:15:32 -07:00
committed by Connor O'Brien
parent f8b20495b7
commit e4757e9070
1 changed files with 1 additions and 1 deletions
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2
drivers/usb/dwc3/core.h
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@@ -144,7 +144,7 @@
#define DWC3_GHWPARAMS8 0xc600 #define DWC3_GHWPARAMS8 0xc600
#define DWC3_GUCTL3 0xc60c #define DWC3_GUCTL3 0xc60c
#define DWC3_GFLADJ 0xc630 #define DWC3_GFLADJ 0xc630
#define DWC3_GHWPARAMS9 0xc680 #define DWC3_GHWPARAMS9 0xc6e0
/* Device Registers */ /* Device Registers */
#define DWC3_DCFG 0xc700 #define DWC3_DCFG 0xc700