RDMA/mlx5: Fix the flow of a miss in the allocation of a cache ODP MR
[ Upstream commit 2f0e60d5e9f96341a0c8a01be8878cdb3b29ff20 ]
When an ODP MR cache entry is empty and trying to allocate it, increment
the ent->miss counter and call to queue_adjust_cache_locked() to verify
the entry is balanced.
Fixes: aad719dcf3
("RDMA/mlx5: Allow MRs to be created in the cache synchronously")
Link: https://lore.kernel.org/r/09503e295276dcacc92cb1d8aef1ad0961c99dc1.1644947594.git.leonro@nvidia.com
Signed-off-by: Aharon Landau <aharonl@nvidia.com>
Signed-off-by: Leon Romanovsky <leonro@nvidia.com>
Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:

committed by
Greg Kroah-Hartman

parent
279f318bd7
commit
e462b0f518
@@ -575,6 +575,8 @@ struct mlx5_ib_mr *mlx5_mr_cache_alloc(struct mlx5_ib_dev *dev,
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ent = &cache->ent[entry];
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ent = &cache->ent[entry];
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spin_lock_irq(&ent->lock);
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spin_lock_irq(&ent->lock);
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if (list_empty(&ent->head)) {
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if (list_empty(&ent->head)) {
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queue_adjust_cache_locked(ent);
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ent->miss++;
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spin_unlock_irq(&ent->lock);
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spin_unlock_irq(&ent->lock);
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mr = create_cache_mr(ent);
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mr = create_cache_mr(ent);
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if (IS_ERR(mr))
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if (IS_ERR(mr))
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