Merge tag 'tty-5.4-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty
Pull tty/serial driver updates from Greg KH: "Even in this age, people are still making new serial port silicon, why... Anyway, here's the TTY and Serial driver update for 5.4-rc1. Lots of changes in here for a number of embedded serial port devices that are being worked on because people really like to see those console logs... Other than that, nothing major here, no core tty changes that anyone should care about. All of these have been in linux-next for a while with no reported issues" * tag 'tty-5.4-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty: (125 commits) serial: tegra: Add PIO mode support serial: tegra: report clk rate errors serial: tegra: add support to adjust baud rate serial: tegra: DT for Adjusted baud rates serial: tegra: add support to use 8 bytes trigger serial: tegra: set maximum num of uart ports to 8 serial: tegra: check for FIFO mode enabled status dt-binding: serial: tegra: add new chips serial: tegra: report error to upper tty layer serial: tegra: flush the RX fifo on frame error serial: tegra: avoid reg access when clk disabled serial: tegra: add support to ignore read serial: sprd: correct the wrong sequence of arguments dt-bindings: serial: Convert riscv,sifive-serial to json-schema serial: max310x: turn off transmitter before activating AutoCTS or auto transmitter flow control serial: max310x: Properly set flags in AutoCTS mode tty: serial: fix platform_no_drv_owner.cocci warnings dt-bindings: serial: Document Freescale LINFlexD UART serial: fsl_linflexuart: Update compatible string tty: n_gsm: avoid recursive locking with async port hangup ...
This commit is contained in:
Linus Torvalds
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* Freescale LINFlexD UART
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The LINFlexD controller implements several LIN protocol versions, as well as
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support for full-duplex UART communication through 8-bit and 9-bit frames.
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See chapter 47 ("LINFlexD") in the reference manual[1].
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Required properties:
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- compatible :
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- "fsl,s32v234-linflexuart" for LINFlexD configured in UART mode, which
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is compatible with the one integrated on S32V234 SoC
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- reg : Address and length of the register set for the device
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- interrupts : Should contain uart interrupt
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Example:
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uart0: serial@40053000 {
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compatible = "fsl,s32v234-linflexuart";
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reg = <0x0 0x40053000 0x0 0x1000>;
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interrupts = <0 59 4>;
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};
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[1] https://www.nxp.com/webapp/Download?colCode=S32V234RM
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@@ -1,7 +1,12 @@
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NVIDIA Tegra20/Tegra30 high speed (DMA based) UART controller driver.
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Required properties:
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- compatible : should be "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart".
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- compatible : should be,
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"nvidia,tegra20-hsuart" for Tegra20,
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"nvidia,tegra30-hsuart" for Tegra30,
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"nvidia,tegra186-hsuart" for Tegra186,
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"nvidia,tegra194-hsuart" for Tegra194.
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- reg: Should contain UART controller registers location and length.
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- interrupts: Should contain UART controller interrupts.
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- clocks: Must contain one entry, for the module clock.
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@@ -19,6 +24,37 @@ Required properties:
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Optional properties:
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- nvidia,enable-modem-interrupt: Enable modem interrupts. Should be enable
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only if all 8 lines of UART controller are pinmuxed.
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- nvidia,adjust-baud-rates: List of entries providing percentage of baud rate
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adjustment within a range.
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Each entry contains sets of 3 values. Range low/high and adjusted rate.
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<range_low range_high adjusted_rate>
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When baud rate set on controller falls within the range mentioned in this
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field, baud rate will be adjusted by percentage mentioned here.
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Ex: <9600 115200 200>
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Increase baud rate by 2% when set baud rate falls within range 9600 to 115200
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Baud Rate tolerance:
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Standard UART devices are expected to have tolerance for baud rate error by
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-4 to +4 %. All Tegra devices till Tegra210 had this support. However,
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Tegra186 chip has a known hardware issue. UART Rx baud rate tolerance level
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is 0% to +4% in 1-stop config. Otherwise, the received data will have
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corruption/invalid framing errors. Parker errata suggests adjusting baud
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rate to be higher than the deviations observed in Tx.
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Tx deviation of connected device can be captured over scope (or noted from
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its spec) for valid range and Tegra baud rate has to be set above actual
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Tx baud rate observed. To do this we use nvidia,adjust-baud-rates
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As an example, consider there is deviation observed in Tx for baud rates as
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listed below.
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0 to 9600 has 1% deviation
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9600 to 115200 2% deviation
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This slight deviation is expcted and Tegra UART is expected to handle it. Due
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to the issue stated above, baud rate on Tegra UART should be set equal to or
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above deviation observed for avoiding frame errors.
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Property should be set like this
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nvidia,adjust-baud-rates = <0 9600 100>,
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<9600 115200 200>;
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Example:
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@@ -33,4 +69,5 @@ serial@70006000 {
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reset-names = "serial";
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dmas = <&apbdma 8>, <&apbdma 8>;
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dma-names = "rx", "tx";
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nvidia,adjust-baud-rates = <1000000 4000000 136>; /* 1.36% shift */
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};
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@@ -1,33 +0,0 @@
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SiFive asynchronous serial interface (UART)
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Required properties:
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- compatible: should be something similar to
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"sifive,<chip>-uart" for the UART as integrated
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on a particular chip, and "sifive,uart<version>" for the
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general UART IP block programming model. Supported
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compatible strings as of the date of this writing are:
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"sifive,fu540-c000-uart" for the SiFive UART v0 as
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integrated onto the SiFive FU540 chip, or "sifive,uart0"
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for the SiFive UART v0 IP block with no chip integration
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tweaks (if any)
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- reg: address and length of the register space
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- interrupts: Should contain the UART interrupt identifier
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- clocks: Should contain a clock identifier for the UART's parent clock
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UART HDL that corresponds to the IP block version numbers can be found
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here:
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https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/uart
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Example:
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uart0: serial@10010000 {
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compatible = "sifive,fu540-c000-uart", "sifive,uart0";
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interrupt-parent = <&plic0>;
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interrupts = <80>;
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reg = <0x0 0x10010000 0x0 0x1000>;
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clocks = <&prci PRCI_CLK_TLCLK>;
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};
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62
Documentation/devicetree/bindings/serial/sifive-serial.yaml
Normal file
62
Documentation/devicetree/bindings/serial/sifive-serial.yaml
Normal file
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# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/serial/sifive-serial.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: SiFive asynchronous serial interface (UART)
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maintainers:
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- Pragnesh Patel <pragnesh.patel@sifive.com>
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- Paul Walmsley <paul.walmsley@sifive.com>
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- Palmer Dabbelt <palmer@sifive.com>
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allOf:
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- $ref: /schemas/serial.yaml#
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properties:
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compatible:
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items:
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- const: sifive,fu540-c000-uart
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- const: sifive,uart0
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description:
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Should be something similar to "sifive,<chip>-uart"
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for the UART as integrated on a particular chip,
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and "sifive,uart<version>" for the general UART IP
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block programming model.
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UART HDL that corresponds to the IP block version
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numbers can be found here -
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https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/uart
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clocks:
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maxItems: 1
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/sifive-fu540-prci.h>
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serial@10010000 {
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compatible = "sifive,fu540-c000-uart", "sifive,uart0";
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interrupt-parent = <&plic0>;
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interrupts = <80>;
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reg = <0x0 0x10010000 0x0 0x1000>;
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clocks = <&prci PRCI_CLK_TLCLK>;
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};
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...
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@@ -20,6 +20,11 @@ Optional properties:
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linux,rs485-enabled-at-boot-time: see rs485.txt.
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- dmas: phandle(s) to DMA controller node(s). Refer to stm32-dma.txt
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- dma-names: "rx" and/or "tx"
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- wakeup-source: bool flag to indicate this device has wakeup capabilities
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- interrupt-names, if optional wake-up interrupt is used, should be:
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- "event": the name for the interrupt line of the USART instance
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- "wakeup" the name for the optional wake-up interrupt
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Examples:
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usart4: serial@40004c00 {
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