net: filter: cleanup A/X name usage
The macro 'A' used in internal BPF interpreter:
#define A regs[insn->a_reg]
was easily confused with the name of classic BPF register 'A', since
'A' would mean two different things depending on context.
This patch is trying to clean up the naming and clarify its usage in the
following way:
- A and X are names of two classic BPF registers
- BPF_REG_A denotes internal BPF register R0 used to map classic register A
in internal BPF programs generated from classic
- BPF_REG_X denotes internal BPF register R7 used to map classic register X
in internal BPF programs generated from classic
- internal BPF instruction format:
struct sock_filter_int {
__u8 code; /* opcode */
__u8 dst_reg:4; /* dest register */
__u8 src_reg:4; /* source register */
__s16 off; /* signed offset */
__s32 imm; /* signed immediate constant */
};
- BPF_X/BPF_K is 1 bit used to encode source operand of instruction
In classic:
BPF_X - means use register X as source operand
BPF_K - means use 32-bit immediate as source operand
In internal:
BPF_X - means use 'src_reg' register as source operand
BPF_K - means use 32-bit immediate as source operand
Suggested-by: Chema Gonzalez <chema@google.com>
Signed-off-by: Alexei Starovoitov <ast@plumgrid.com>
Acked-by: Daniel Borkmann <dborkman@redhat.com>
Acked-by: Chema Gonzalez <chema@google.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Tento commit je obsažen v:
Alexei Starovoitov
odevzdal
David S. Miller
David S. Miller
rodič
7b0dcbd879
revize
e430f34ee5
@@ -59,12 +59,12 @@
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#define BPF_R10 regs[BPF_REG_10]
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/* Named registers */
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#define A regs[insn->a_reg]
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#define X regs[insn->x_reg]
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#define DST regs[insn->dst_reg]
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#define SRC regs[insn->src_reg]
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#define FP regs[BPF_REG_FP]
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#define ARG1 regs[BPF_REG_ARG1]
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#define CTX regs[BPF_REG_CTX]
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#define K insn->imm
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#define IMM insn->imm
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/* No hurry in this branch
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*
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@@ -264,7 +264,7 @@ static unsigned int __sk_run_filter(void *ctx, const struct sock_filter_int *ins
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FP = (u64) (unsigned long) &stack[ARRAY_SIZE(stack)];
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ARG1 = (u64) (unsigned long) ctx;
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/* Register for user BPF programs need to be reset first. */
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/* Registers used in classic BPF programs need to be reset first. */
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regs[BPF_REG_A] = 0;
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regs[BPF_REG_X] = 0;
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@@ -274,16 +274,16 @@ select_insn:
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/* ALU */
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#define ALU(OPCODE, OP) \
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ALU64_##OPCODE##_X: \
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A = A OP X; \
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DST = DST OP SRC; \
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CONT; \
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ALU_##OPCODE##_X: \
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A = (u32) A OP (u32) X; \
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DST = (u32) DST OP (u32) SRC; \
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CONT; \
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ALU64_##OPCODE##_K: \
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A = A OP K; \
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DST = DST OP IMM; \
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CONT; \
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ALU_##OPCODE##_K: \
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A = (u32) A OP (u32) K; \
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DST = (u32) DST OP (u32) IMM; \
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CONT;
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ALU(ADD, +)
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@@ -296,92 +296,92 @@ select_insn:
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ALU(MUL, *)
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#undef ALU
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ALU_NEG:
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A = (u32) -A;
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DST = (u32) -DST;
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CONT;
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ALU64_NEG:
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A = -A;
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DST = -DST;
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CONT;
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ALU_MOV_X:
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A = (u32) X;
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DST = (u32) SRC;
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CONT;
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ALU_MOV_K:
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A = (u32) K;
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DST = (u32) IMM;
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CONT;
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ALU64_MOV_X:
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A = X;
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DST = SRC;
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CONT;
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ALU64_MOV_K:
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A = K;
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DST = IMM;
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CONT;
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ALU64_ARSH_X:
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(*(s64 *) &A) >>= X;
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(*(s64 *) &DST) >>= SRC;
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CONT;
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ALU64_ARSH_K:
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(*(s64 *) &A) >>= K;
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(*(s64 *) &DST) >>= IMM;
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CONT;
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ALU64_MOD_X:
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if (unlikely(X == 0))
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if (unlikely(SRC == 0))
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return 0;
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tmp = A;
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A = do_div(tmp, X);
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tmp = DST;
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DST = do_div(tmp, SRC);
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CONT;
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ALU_MOD_X:
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if (unlikely(X == 0))
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if (unlikely(SRC == 0))
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return 0;
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tmp = (u32) A;
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A = do_div(tmp, (u32) X);
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tmp = (u32) DST;
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DST = do_div(tmp, (u32) SRC);
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CONT;
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ALU64_MOD_K:
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tmp = A;
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A = do_div(tmp, K);
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tmp = DST;
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DST = do_div(tmp, IMM);
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CONT;
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ALU_MOD_K:
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tmp = (u32) A;
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A = do_div(tmp, (u32) K);
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tmp = (u32) DST;
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DST = do_div(tmp, (u32) IMM);
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CONT;
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ALU64_DIV_X:
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if (unlikely(X == 0))
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if (unlikely(SRC == 0))
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return 0;
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do_div(A, X);
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do_div(DST, SRC);
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CONT;
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ALU_DIV_X:
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if (unlikely(X == 0))
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if (unlikely(SRC == 0))
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return 0;
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tmp = (u32) A;
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do_div(tmp, (u32) X);
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A = (u32) tmp;
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tmp = (u32) DST;
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do_div(tmp, (u32) SRC);
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DST = (u32) tmp;
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CONT;
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ALU64_DIV_K:
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do_div(A, K);
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do_div(DST, IMM);
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CONT;
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ALU_DIV_K:
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tmp = (u32) A;
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do_div(tmp, (u32) K);
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A = (u32) tmp;
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tmp = (u32) DST;
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do_div(tmp, (u32) IMM);
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DST = (u32) tmp;
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CONT;
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ALU_END_TO_BE:
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switch (K) {
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switch (IMM) {
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case 16:
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A = (__force u16) cpu_to_be16(A);
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DST = (__force u16) cpu_to_be16(DST);
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break;
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case 32:
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A = (__force u32) cpu_to_be32(A);
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DST = (__force u32) cpu_to_be32(DST);
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break;
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case 64:
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A = (__force u64) cpu_to_be64(A);
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DST = (__force u64) cpu_to_be64(DST);
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break;
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}
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CONT;
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ALU_END_TO_LE:
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switch (K) {
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switch (IMM) {
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case 16:
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A = (__force u16) cpu_to_le16(A);
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DST = (__force u16) cpu_to_le16(DST);
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break;
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case 32:
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A = (__force u32) cpu_to_le32(A);
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DST = (__force u32) cpu_to_le32(DST);
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break;
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case 64:
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A = (__force u64) cpu_to_le64(A);
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DST = (__force u64) cpu_to_le64(DST);
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break;
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}
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CONT;
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@@ -401,85 +401,85 @@ select_insn:
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insn += insn->off;
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CONT;
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JMP_JEQ_X:
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if (A == X) {
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if (DST == SRC) {
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insn += insn->off;
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CONT_JMP;
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}
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CONT;
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JMP_JEQ_K:
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if (A == K) {
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if (DST == IMM) {
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insn += insn->off;
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CONT_JMP;
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}
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CONT;
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JMP_JNE_X:
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if (A != X) {
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if (DST != SRC) {
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insn += insn->off;
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CONT_JMP;
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}
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CONT;
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JMP_JNE_K:
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if (A != K) {
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if (DST != IMM) {
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insn += insn->off;
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CONT_JMP;
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}
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CONT;
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JMP_JGT_X:
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if (A > X) {
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if (DST > SRC) {
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insn += insn->off;
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CONT_JMP;
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}
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CONT;
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JMP_JGT_K:
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if (A > K) {
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if (DST > IMM) {
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insn += insn->off;
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CONT_JMP;
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}
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CONT;
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JMP_JGE_X:
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if (A >= X) {
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if (DST >= SRC) {
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insn += insn->off;
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CONT_JMP;
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}
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CONT;
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JMP_JGE_K:
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if (A >= K) {
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if (DST >= IMM) {
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insn += insn->off;
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CONT_JMP;
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}
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CONT;
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JMP_JSGT_X:
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if (((s64) A) > ((s64) X)) {
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if (((s64) DST) > ((s64) SRC)) {
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insn += insn->off;
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CONT_JMP;
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}
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CONT;
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JMP_JSGT_K:
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if (((s64) A) > ((s64) K)) {
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if (((s64) DST) > ((s64) IMM)) {
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insn += insn->off;
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CONT_JMP;
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}
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CONT;
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JMP_JSGE_X:
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if (((s64) A) >= ((s64) X)) {
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if (((s64) DST) >= ((s64) SRC)) {
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insn += insn->off;
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CONT_JMP;
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}
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CONT;
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JMP_JSGE_K:
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if (((s64) A) >= ((s64) K)) {
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if (((s64) DST) >= ((s64) IMM)) {
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insn += insn->off;
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CONT_JMP;
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}
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CONT;
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JMP_JSET_X:
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if (A & X) {
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if (DST & SRC) {
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insn += insn->off;
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CONT_JMP;
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}
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CONT;
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JMP_JSET_K:
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if (A & K) {
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if (DST & IMM) {
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insn += insn->off;
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CONT_JMP;
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}
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@@ -488,15 +488,15 @@ select_insn:
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return BPF_R0;
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/* STX and ST and LDX*/
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#define LDST(SIZEOP, SIZE) \
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STX_MEM_##SIZEOP: \
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*(SIZE *)(unsigned long) (A + insn->off) = X; \
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CONT; \
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ST_MEM_##SIZEOP: \
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*(SIZE *)(unsigned long) (A + insn->off) = K; \
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CONT; \
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LDX_MEM_##SIZEOP: \
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A = *(SIZE *)(unsigned long) (X + insn->off); \
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#define LDST(SIZEOP, SIZE) \
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STX_MEM_##SIZEOP: \
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*(SIZE *)(unsigned long) (DST + insn->off) = SRC; \
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CONT; \
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ST_MEM_##SIZEOP: \
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*(SIZE *)(unsigned long) (DST + insn->off) = IMM; \
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CONT; \
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LDX_MEM_##SIZEOP: \
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DST = *(SIZE *)(unsigned long) (SRC + insn->off); \
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CONT;
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LDST(B, u8)
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@@ -504,16 +504,16 @@ select_insn:
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LDST(W, u32)
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LDST(DW, u64)
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#undef LDST
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STX_XADD_W: /* lock xadd *(u32 *)(A + insn->off) += X */
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atomic_add((u32) X, (atomic_t *)(unsigned long)
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(A + insn->off));
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STX_XADD_W: /* lock xadd *(u32 *)(dst_reg + off16) += src_reg */
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atomic_add((u32) SRC, (atomic_t *)(unsigned long)
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(DST + insn->off));
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CONT;
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STX_XADD_DW: /* lock xadd *(u64 *)(A + insn->off) += X */
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atomic64_add((u64) X, (atomic64_t *)(unsigned long)
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(A + insn->off));
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STX_XADD_DW: /* lock xadd *(u64 *)(dst_reg + off16) += src_reg */
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atomic64_add((u64) SRC, (atomic64_t *)(unsigned long)
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(DST + insn->off));
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CONT;
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LD_ABS_W: /* BPF_R0 = ntohl(*(u32 *) (skb->data + K)) */
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off = K;
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LD_ABS_W: /* BPF_R0 = ntohl(*(u32 *) (skb->data + imm32)) */
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off = IMM;
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load_word:
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/* BPF_LD + BPD_ABS and BPF_LD + BPF_IND insns are
|
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* only appearing in the programs where ctx ==
|
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@@ -527,51 +527,51 @@ load_word:
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* BPF_R6-BPF_R9, and store return value into BPF_R0.
|
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*
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* Implicit input:
|
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* ctx
|
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* ctx == skb == BPF_R6 == CTX
|
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*
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* Explicit input:
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* X == any register
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* K == 32-bit immediate
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* SRC == any register
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* IMM == 32-bit immediate
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*
|
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* Output:
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* BPF_R0 - 8/16/32-bit skb data converted to cpu endianness
|
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*/
|
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ptr = load_pointer((struct sk_buff *) ctx, off, 4, &tmp);
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ptr = load_pointer((struct sk_buff *) CTX, off, 4, &tmp);
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if (likely(ptr != NULL)) {
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BPF_R0 = get_unaligned_be32(ptr);
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CONT;
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}
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return 0;
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LD_ABS_H: /* BPF_R0 = ntohs(*(u16 *) (skb->data + K)) */
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off = K;
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LD_ABS_H: /* BPF_R0 = ntohs(*(u16 *) (skb->data + imm32)) */
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off = IMM;
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load_half:
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ptr = load_pointer((struct sk_buff *) ctx, off, 2, &tmp);
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ptr = load_pointer((struct sk_buff *) CTX, off, 2, &tmp);
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if (likely(ptr != NULL)) {
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BPF_R0 = get_unaligned_be16(ptr);
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CONT;
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}
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|
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return 0;
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LD_ABS_B: /* BPF_R0 = *(u8 *) (ctx + K) */
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off = K;
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LD_ABS_B: /* BPF_R0 = *(u8 *) (skb->data + imm32) */
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off = IMM;
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load_byte:
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ptr = load_pointer((struct sk_buff *) ctx, off, 1, &tmp);
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ptr = load_pointer((struct sk_buff *) CTX, off, 1, &tmp);
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if (likely(ptr != NULL)) {
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BPF_R0 = *(u8 *)ptr;
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CONT;
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}
|
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|
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return 0;
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LD_IND_W: /* BPF_R0 = ntohl(*(u32 *) (skb->data + X + K)) */
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off = K + X;
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LD_IND_W: /* BPF_R0 = ntohl(*(u32 *) (skb->data + src_reg + imm32)) */
|
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off = IMM + SRC;
|
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goto load_word;
|
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LD_IND_H: /* BPF_R0 = ntohs(*(u16 *) (skb->data + X + K)) */
|
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off = K + X;
|
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LD_IND_H: /* BPF_R0 = ntohs(*(u16 *) (skb->data + src_reg + imm32)) */
|
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off = IMM + SRC;
|
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goto load_half;
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LD_IND_B: /* BPF_R0 = *(u8 *) (skb->data + X + K) */
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off = K + X;
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LD_IND_B: /* BPF_R0 = *(u8 *) (skb->data + src_reg + imm32) */
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off = IMM + SRC;
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goto load_byte;
|
||||
|
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default_label:
|
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@@ -675,7 +675,7 @@ static bool convert_bpf_extensions(struct sock_filter *fp,
|
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case SKF_AD_OFF + SKF_AD_PROTOCOL:
|
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BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff, protocol) != 2);
|
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|
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/* A = *(u16 *) (ctx + offsetof(protocol)) */
|
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/* A = *(u16 *) (CTX + offsetof(protocol)) */
|
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*insn++ = BPF_LDX_MEM(BPF_H, BPF_REG_A, BPF_REG_CTX,
|
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offsetof(struct sk_buff, protocol));
|
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/* A = ntohs(A) [emitting a nop or swap16] */
|
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@@ -741,7 +741,7 @@ static bool convert_bpf_extensions(struct sock_filter *fp,
|
||||
BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff, vlan_tci) != 2);
|
||||
BUILD_BUG_ON(VLAN_TAG_PRESENT != 0x1000);
|
||||
|
||||
/* A = *(u16 *) (ctx + offsetof(vlan_tci)) */
|
||||
/* A = *(u16 *) (CTX + offsetof(vlan_tci)) */
|
||||
*insn++ = BPF_LDX_MEM(BPF_H, BPF_REG_A, BPF_REG_CTX,
|
||||
offsetof(struct sk_buff, vlan_tci));
|
||||
if (fp->k == SKF_AD_OFF + SKF_AD_VLAN_TAG) {
|
||||
@@ -760,13 +760,13 @@ static bool convert_bpf_extensions(struct sock_filter *fp,
|
||||
case SKF_AD_OFF + SKF_AD_NLATTR_NEST:
|
||||
case SKF_AD_OFF + SKF_AD_CPU:
|
||||
case SKF_AD_OFF + SKF_AD_RANDOM:
|
||||
/* arg1 = ctx */
|
||||
/* arg1 = CTX */
|
||||
*insn++ = BPF_MOV64_REG(BPF_REG_ARG1, BPF_REG_CTX);
|
||||
/* arg2 = A */
|
||||
*insn++ = BPF_MOV64_REG(BPF_REG_ARG2, BPF_REG_A);
|
||||
/* arg3 = X */
|
||||
*insn++ = BPF_MOV64_REG(BPF_REG_ARG3, BPF_REG_X);
|
||||
/* Emit call(ctx, arg2=A, arg3=X) */
|
||||
/* Emit call(arg1=CTX, arg2=A, arg3=X) */
|
||||
switch (fp->k) {
|
||||
case SKF_AD_OFF + SKF_AD_PAY_OFFSET:
|
||||
*insn = BPF_EMIT_CALL(__skb_get_pay_offset);
|
||||
@@ -941,12 +941,12 @@ do_pass:
|
||||
*/
|
||||
*insn++ = BPF_MOV32_IMM(BPF_REG_TMP, fp->k);
|
||||
|
||||
insn->a_reg = BPF_REG_A;
|
||||
insn->x_reg = BPF_REG_TMP;
|
||||
insn->dst_reg = BPF_REG_A;
|
||||
insn->src_reg = BPF_REG_TMP;
|
||||
bpf_src = BPF_X;
|
||||
} else {
|
||||
insn->a_reg = BPF_REG_A;
|
||||
insn->x_reg = BPF_REG_X;
|
||||
insn->dst_reg = BPF_REG_A;
|
||||
insn->src_reg = BPF_REG_X;
|
||||
insn->imm = fp->k;
|
||||
bpf_src = BPF_SRC(fp->code);
|
||||
}
|
||||
|
||||
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