arm64: Introduce VA_BITS and translation level options
This patch adds virtual address space size and a level of translation tables to kernel configuration. It facilicates introduction of different MMU options, such as 4KB + 4 levels, 16KB + 4 levels and 64KB + 3 levels, easily. The idea is based on the discussion with Catalin Marinas: http://www.spinics.net/linux/lists/arm-kernel/msg319552.html Signed-off-by: Jungseok Lee <jays.lee@samsung.com> Reviewed-by: Sungjinn Chung <sungjinn.chung@samsung.com> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Tested-by: Jungseok Lee <jungseoklee85@gmail.com>
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Catalin Marinas

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@@ -26,7 +26,7 @@
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#define check_pgt_cache() do { } while (0)
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#ifndef CONFIG_ARM64_64K_PAGES
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#ifndef CONFIG_ARM64_2_LEVELS
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static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long addr)
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{
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@@ -44,7 +44,7 @@ static inline void pud_populate(struct mm_struct *mm, pud_t *pud, pmd_t *pmd)
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set_pud(pud, __pud(__pa(pmd) | PMD_TYPE_TABLE));
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}
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#endif /* CONFIG_ARM64_64K_PAGES */
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#endif /* CONFIG_ARM64_2_LEVELS */
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extern pgd_t *pgd_alloc(struct mm_struct *mm);
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extern void pgd_free(struct mm_struct *mm, pgd_t *pgd);
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