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clk: samsung: exynos3250: Register DMC clk provider

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Add clock provider for clocks in DMC domain including EPLL and BPLL. The
DMC clocks are necessary for Exynos3 devfreq driver.

The DMC clock domain uses different address space (0x105C0000) than
standard clock domain (0x10030000 - 0x10050000). The difference is huge
enough to add new DT node for the clock provider, rather than extending
existing address space.

Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
This commit is contained in:
Krzysztof Kozlowski
2014-09-02 15:21:15 +02:00
committed by Tomasz Figa
parent 22842d244a
commit e3c3f19bc6
2 changed files with 222 additions and 0 deletions
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27
include/dt-bindings/clock/exynos3250.h
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@@ -255,4 +255,31 @@
*/
#define CLK_NR_CLKS 248
/*
* CMU DMC
*/
#define CLK_FOUT_BPLL 1
#define CLK_FOUT_EPLL 2
/* Muxes */
#define CLK_MOUT_MPLL_MIF 8
#define CLK_MOUT_BPLL 9
#define CLK_MOUT_DPHY 10
#define CLK_MOUT_DMC_BUS 11
#define CLK_MOUT_EPLL 12
/* Dividers */
#define CLK_DIV_DMC 16
#define CLK_DIV_DPHY 17
#define CLK_DIV_DMC_PRE 18
#define CLK_DIV_DMCP 19
#define CLK_DIV_DMCD 20
/*
* Total number of clocks of main CMU.
* NOTE: Must be equal to last clock ID increased by one.
*/
#define NR_CLKS_DMC 21
#endif /* _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H */